138 IEEE TRANSACTIONS ON COMPUTERS, VOL. 69, NO.

1, JANUARY 2020

Fast and Efficient Convolutional

Accelerator for Edge Computing
Arash Ardakani , Carlo Condo , and Warren J. Gross , Senior Member, IEEE

Abstract—Convolutional neural networks (CNNs) are a vital approach in machine learning. However, their high complexity and energy
consumption make them challenging to embed in mobile applications at the edge requiring real-time processes such as smart phones.
In order to meet the real-time constraint of edge devices, recently proposed custom hardware CNN accelerators have exploited parallel
processing elements (PEs) to increase throughput. However, this straightforward parallelization of PEs and high memory bandwidth
require high data movement, leading to large energy consumption. As a result, only a certain number of PEs can be instantiated when
designing bandwidth-limited custom accelerators targeting edge devices. While most bandwidth-limited designs claim a peak
performance of a few hundred giga operations per second, their average runtime performance is substantially lower than their roofline
when applied to state-of-the-art CNNs such as AlexNet, VGGNet and ResNet, as a result of low resource utilization and arithmetic
intensity. In this work, we propose a zero-activation-skipping convolutional accelerator (ZASCA) that avoids noncontributory
multiplications with zero-valued activations. ZASCA employs a dataflow that minimizes the gap between its average and peak
performances while maximizing its arithmetic intensity for both sparse and dense representations of activations, targeting the bandwidth-
limited edge computing scenario. More precisely, ZASCA achieves a performance efficiency of up to 94 percent over a set of state-of-the-
art CNNs for image classification with dense representation where the performance efficiency is the ratio between the average runtime
performance and the peak performance. Using its zero-skipping feature, ZASCA can further improve the performance efficiency of the
state-of-the-art CNNs by up to 1.9
depending on the sparsity degree of activations. The implementation results in 65-nm TSMC CMOS
technology show that, compared to the most energy-efficient accelerator, ZASCA can process convolutions from 5.5
to 17.5
faster, and
is between 2.1
and 4.5
more energy efficient while occupying 2.1
less silicon area.

Index Terms—Convolutional neural network, machine learning, hardware accelerator, edge computing

1 INTRODUCTION
neural networks (DNNs), especially convolu-
D EEP
tional neural networks (CNNs) [1], have received tre-
mendous attention due to their ability to surpass human-
level accuracy on a wide range of complex tasks such as
recognition, classification and detection [2]. Depending
on their size and complexity, these networks achieve dif-
ferent degrees of classification/recognition accuracy. A
CNN is a stack of multiple convolutional layers followed
by fully-connected layers: convolutional layers extract
high level abstractions and features of raw data, whereas
fully-connected networks are used to learn non-linear
combinations of the extracted features. In 2012, a CNN
called AlexNet [3] was introduced: it is constituted of 5
convolutional layers followed by 3 fully-connected layers
and achieves 42.9 percent misclassification rate (MCR) on
the ImageNet dataset. AlexNet contains 2.3M weights and
58.6M weights in its convolutional and fully-connected
layers, respectively, performing 1332M operations (i.e.,
 A. Ardakani and W.J. Gross are with the Electrical and Computer Engineering
Department, McGill University, Montreal, QC H3A 0G4, Canada.
E-mail: arash.ardakani@mail.mcgill.ca, warren.gross@mcgill.ca.
 C. Condo is with the Mathematical and Algorithmic Sciences Lab, Huawei
Technologies Co. Ltd, Paris 75002, France. E-mail: carlo.condo@huawei.com.
Manuscript received 18 Sept. 2018; revised 26 Aug. 2019; accepted 11 Sept.
2019. Date of publication 16 Sept. 2019; date of current version 19 Dec. 2019.
(Corresponding author: Arash Ardakani.)
Recommended for acceptance by D. Marculescu.
Digital Object Identifier no. 10.1109/TC.2019.2941875
0018-9340 ß 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See ht_tp://www.ieee.org/publications_standards/publications/rights/index.html for more information.
666M multiply-accumulates (MACs)) in its convolutional
layers, and 117.2M operations (i.e., 58.6M MACs) in its
fully-connected layers. VGGNet-16 [4] is another well-
known CNN, containing 13 convolutional layers with
14.7M weights and 3 fully-connected layers with 124M
weights. VGGNet-16 performs 30.6G operations in its con-
volutional layers and 248M operations in its fully-
connected layers, achieving 27 percent MCR on Image-
Net. Recently, ResNets [5] achieved a lower complexity
and a better MCR by using residual connections. For
instance, ResNet-18 achieves a similar MCR to VGGNet-
16 (i.e., 27.88 percent on ImageNet) while performing
3.6G and 1M operations in its 17 convolutional layers
with 11M weights and 1 fully-connected layer with 1M
weights, respectively. Moreover, ResNet-50, containing
49 convolutional layers with 23.5M weights and 1 fully-
connected layer with 2M weights, achieved a better MCR
(i.e., 22.85 percent on ImageNet) by going even deeper.
ResNet-50 respectively performs 7G and 4M operations
within the two types of layers. All these CNNs have won
the ImageNet Large Scale Visual Recognition Challenge
(ILSVRC) [6].
Regardless of the fact that in almost all the aforementioned
CNNs the majority of weights is found in fully-connected
layers, the number of operations are dominated by convolu-
tions. As a result, the processing time of CNNs is also domi-
nated by the convolutional processes. This issue can easily be
addressed by exploiting parallel processing elements (PEs) to

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ARDAKANI ET AL.: FAST AND EFFICIENT CONVOLUTIONAL ACCELERATOR FOR EDGE COMPUTING
Fig. 1. The roofline model of Eyeriss, EEPS and DSIP tested on AlexNet
and VGG-16. The square points and dashed lines denote the average
runtime performance and the roofline (i.e., the peak performance),
respectively.
increase throughput. However, a straightforward paralleliza-
tion requires high data movement and bandwidth, leading to
high energy consumption [7].
During the past few years, many convolutional accelera-
tors with different dataflows have been introduced in litera-
ture [8], [9], [10], [11], [12], targeting edge devices. While these
ASIC architectures can successfully reduce the number of
memory access to the off-chip memory and meet the latency
constraints of small CNNs such as AlexNet within the edge
computing scenario, they fail to employ the full potential of
their architectures due to the limited data bandwidth of edge
devices, resulting in a low performance efficiency. In fact,
their bandwidth bottleneck and network topology (i.e., data-
flow) prevent them from providing the required parallelism
for their PEs right after each access to the off-chip memory.
Therefore, a great deal of time is wasted reading data from
memories. As a result, there is a huge gap between their peak
performance and average runtime performance. The peak
performance is defined as the maximum achievable number
of operations per second, roughly computed as
peak performance ¼ 2
#PE
f;
where #PE and f denote the number of PEs and nominal fre-
quency, respectively, and where each PE performs a single
MAC at each clock cycle. The runtime performance is also
defined as the number of operations per second obtained
when performing computations on a specific dataset.
Fig. 1 visually illustrates the above limitation of state-
of-the-art accelerators (i.e., Eyeriss [8], EEPS [13] and DSIP
[14]) using their roofline model that ties together their per-
formance and arithmetic intensity. The performance of an
accelerator is measured as the number of operations per
second while the arithmetic intensity is defined as the num-
ber of operations performed on a byte of accessed data from
the off-chip memory [15].
Fig. 1 shows that Eyeriss has the highest arithmetic inten-
sity when performing the convolutions of AlexNet and
VGG-16 and compared to EEPS and DSIP. However, there is
a huge gap between its peak performance (i.e., the roofline
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139
Fig. 2. The performance efficiency of Eyeriss, EEPS and DSIP tested on
AlexNet and VGG-16. Note that the performance efficiency of Eyeriss,
EEPS and DSIP is taken from their original papers.
denoted by a red dashed line) and runtime performance. We
measure the gap as the ratio between the average runtime
performance and the peak performance and refer to it as per-
formance efficiency. Fig. 2 shows the performance efficiency
of the aforementioned convolutional accelerators. The per-
formance efficiency of Eyeriss varies from 26 to 55 percent
when running AlexNet and VGG-16: from 45 to 74 percent of
its potential, hardware resources and energy are wasted. On
the other hand, EEPS and DSIP have a higher performance
efficiency while having a poor arithmetic intensity. More
precisely, these accelerators have only focused on maximiz-
ing one implementation aspect: either arithmetic intensity
(e.g., Eyeriss) or performance efficiency (e.g., EEPS and
DSIP) while an accelerator maximizing both aspects is miss-
ing in literature.
As a first attempt to increase the performance efficiency
and the arithmetic intensity, we presented a new dataflow,
called fully-connected inspired dataflow (FID), and its
architecture in [16] for filter sizes fixed to 3
3. However,
FID and its architecture suffer from lack of reconfigurability
and are only restricted to VGG-like networks where their fil-
ter sizes are fixed to 3
3 for all layers. It is worth mention-
ing that reconfigurability is of paramount importance in
designing a convolutional accelerator as filter sizes of each
layer can be different from others. For instance, AlexNet
consists of 5 layers of convolutions with filter sizes 11
11,
5
5 and 3
3.
Another key motivation for our work is exploiting the
intrinsic sparsity among activations incurred by using the rec-
tified linear unit (ReLU) as the non-linear function in order to
(1) avoid unnecessary MAC operations. More precisely, ReLUs
dynamically clamp all negatively-valued activations to zero
at runtime. As a result, the sparsity degree of each layer highly
relies on the network and dataset being used. Fig. 3 shows the
average sparsity degree of activations for AlexNet, VGG-16,
ResNet-18 and ResNet-50. The sparsity degree of activations
(i.e., the fraction of zeros in activations) suggests that noncon-
tributory multiplications/additions can be avoided to speed
up the convolutional computations. Moreover, reading zero-
valued activations can be skipped during DRAM accesses as
memory accesses directly contribute in total energy consump-
tion of systems [17], [18]. It is worth mentioning that the spar-
sity among activations is an intrinsic occurrence in neural
networks using the ReLU as their non-linear function. There-
fore, there is no approximation involved in their computa-
tions and skipping the noncontributory computations does
not incur any accuracy degradation.
Several recent convolutional accelerators specialized for
the inference computation in the cloud have also investigated
140 IEEE TRANSACTIONS ON COMPUTERS, VOL. 69, NO. 1, JANUARY 2020

TABLE 1
Convolutional Layer Computation Parameters

Name of Parameter Description

Hin /Win Height/Width of the input activation maps
Hout /Wout Height/Width of the output activation maps
Hf /Wf Height/Width of the filter plane
Cin =Cout No. of channels of the input/output
activation maps
Fig. 3. The average sparsity degree of convolutional layers for AlexNet, S Stride number
VGG-16, ResNet-18 and ResNet-50.

the sparsity among activations and weights to skip unneces-

of weights, also referred to as a filter. The main computational
sary computations. Cnvlutin [19] and Cambricon-X [20]
kernel of a convolutional layer involves high-dimensional
exploit the sparsity among activations and weights mainly to
convolutions. The convolutional layers take input pixels,
speed up the convolutional computations, respectively.
which are also called input activation maps, arranged in 3
SCNN [21] introduced a dataflow to exploit the sparsity
dimensions (i.e., height Hin , width Win and channel Cin ), and
among both activations and weights to reduce computation
generate output pixels, which are also called output activation
cycles and energy consumption. Despite the speedup that
maps, arranged in 3 dimensions (i.e., height Hout , width Wout
these accelerators achieve over their baseline, their power
and channel Cout ). This transformation is a result of the convo-
consumption is far beyond the power budget of edge systems
lution between the input activation maps and a set of Cout 3D
which is limited to a few hundred mW [22]. More precisely,
filters. More precisely, every single 2D Hout
Wout plane of
these accelerators exploit the straightforward parallelism and
the output activation maps is a result of the convolution
require high data bandwidth. However, the data bandwidth
between the 3D input activation maps with a set of 3D filters.
of most of the embedded and mobile devices is limited by the
In fact, a summation of multiple plane-wise 2D convolutions
bandwidth of the off-chip memory. For instance, most of
forms a 3D convolution. At the end, the results of 3D convolu-
the low-power DDRs (LPDDRs) such as LPDDR4 provide
tions are also added to 1D bias. In summary, the convolu-
the bit-width of up to 64 bits [23]. As a result, the bandwidth
tional processes with the input activation maps, the output
of state-of-the-art convolutional accelerators for mobile
activation maps, the filters and the bias matrices denoted as
devices is limited to 64 bits [8], [9], [13], [24]. Therefore, acce-
X, Y , W and B, respectively, can be expressed as
lerating convolutions while skipping the noncontributory
computations within the edge computing scenario is nontriv- Hf Wf
Cin X
X X
ial and missing. Y ðz; t; qÞ ¼ BðqÞ þ XðzS þ j; tS þ i; kÞ
W ðj; i; k; qÞ;
Motivated by the aforementioned statements, in this paper, k¼1 j¼1 i¼1

we present a zero-activation-skipping convolutional accelera-

Hout ¼ ðHin  Hf þ SÞ=S;
tor (ZASCA) that enables further improvements in the arith-
metic intensity and the performance efficiency over non-
Wout ¼ ðWin  Wf þ SÞ=S; (2)
zero-skipping accelerators for edge devices. To this end, we
first extend and generalize FID to support all type of filter
where 1  z  Hout , 1  t  Wout and 1  q  Cout . The
sizes used in state -of-the-art CNNs. We then propose a zero-
stride S represents the number of activation map pixels of
skipping paradigm based on the generalized FID (GFID) and
which the filter is shifted after each convolution. Contrary to
its architecture (i.e., ZASCA). ZASCA is optimized to achieve
the fully-connected layers, convolutional computations are
high arithmetic intensity, performance efficiency and energy
dominated by numerous MACs according to Eq. (2), leading
efficiency, while keeping the power consumption below the
to a high degree of computational complexity. The parame-
budget of mobile/embedded devices. Finally, we evaluate the
ters used in the convolutional process are summarized in
performance of ZASCA on state-of-the-art CNN models (i.e.,
Table 1.
AlexNet, VGGNet-16, ResNet-18 and ResNet-50) and show
that ZASCA performs the convolutional computations of
2.1 Fully-Connected Inspired Dataflow for
these CNNs with an 83 percent minimum performance
Convolutional Computations
efficiency when using dense representation (i.e., no zero-
activation-skipping). Using its zero-skipping feature, ZASCA In [16], FID was introduced. It can be used to efficiently per-
can further improve the performance efficiency by a factor of form the computations of convolutional layers with filter
1.9
. Finally, we show that the roofline model of ZASCA parameter Wf fixed to 3. Let us note that 2D convolution is
surpasses the roofline models of the state-of-the-art accelera- the weighted summation of each pixel of an input image
tors in terms of both performance efficiency and arithmetic with its neighboring pixels, and consider an input image as
intensity. a matrix X8
2 , a filter as a matrix W1
3 and an output as a
matrix Y6
2 , such that
2 PRELIMINARIES  
X1 X2 . . . X8
X¼ ; W ¼ ½ W1 W2 W3 ;
Inspired by the organization of the animal visual cortex, it was X9 X10 . . . X16
shown that the connectivity of neurons in convolutional  
layers can be mathematically described by a convolution Y1 Y2 . . . Y6
Y ¼ :
operation [25]. All neurons in a convolutional layer share a set Y7 Y8 . . . Y12

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ARDAKANI ET AL.: FAST AND EFFICIENT CONVOLUTIONAL ACCELERATOR FOR EDGE COMPUTING 141

2 3
TABLE 2 W1 0 0  0
The FID for Convolutional Computations 6
6 W2
..
.
7
7
)
6 .. 7
6 7
6 0 . 7 S:
6 7
6 7
6 . 7
6 . 7
6 . W1 7
6 .. 7
6 W2 0 . 7
6 7
6 7
6 WWf 0 7
6 7
6 .. .. 7
M¼6
6 0 . W1 . 7;
7 (3)
6 W2 7
6 7
6 WWf 0 7
6 7
6 .. 7
6 0 . W1 7
6 7
6 . 7
6 .. W2 7
6 7
6 .. 7
6 . WWf 7
6 7
6 7
6 .. .. .. 7
4 . . . 5
0  0  WWf

Considering each output pixel assigned to a neuron, Table 2
shows the convolutional process of this example in a way
similar to the fully-connected layer computations, where
input pixels are read sequentially at each clock cycle (CC)
and the neurons share the same input pixels. This example
considers Cin ¼ 1, Cout ¼ 1, Hin ¼ 2, Win ¼ 8, Hf ¼ 1, Wf ¼ 3
and S ¼ 1. Similar to the fully-connected dataflow, each neu-
ron loads a different weight at each time step, subsequently
accumulating the weighted input pixels. The number of time
steps required to perform the convolutional computations is
also equal to the number of input pixels, Hin
Win . When
passed to the next neuron belonging to the same row of the
output activation map, the weights need to be shifted by one
position. However, weight passing between neurons of dif-
ferent rows requires a shift of Wf positions, as can be
observed between clock cycles #6 and #9 for W1 denoted in
red in Table 2.
As shown in Table 2, three PEs (i.e., neurons) are suffi-
cient to perform the convolutions. In fact, there are only 3
active neurons at each time step. Each PE thus receives its
input at clock cycle 3
i þ 1, 3
i þ 2 and 3
i þ 3. Their
outputs are also valid after 3 clock cycles in the given exam-
ple. So far, we only considered a case with Hf ¼ 1. In case
of Hf ¼ 3, the procedure in Table 2 has to be repeated 2
times more: the first iteration with W1 , W2 and W3 , the sec-
ond with W4 , W5 and W6 , and the final one with W7 , W8 and
W9 . Similarly, for higher values of Cin , the process has to be
to repeated Cin times. Therefore, a memory is required to
store the partial values generated by the 3 neurons for each
output pixel. In general, N output pixels can be computed
using 3 neurons (i.e., PEs) and 3 separate N=3-element
SRAM memories working in parallel. The unit generating
the N output pixels of an output activation map is referred
to as a convolutional element (CE).
M can contain only Wf non-zero elements at most. The shift
amount within each row of the output activation map is
equal to S, denoted with a horizontal dashed line in the
matrix M. The number of columns of the matrix M indicates
the N output pixels that belong to the same row of the out-
put activation map, while the number of rows of M denotes
the required number of clock cycles. We use the GFID
matrix M to represent different filter sizes used in the state-
of-the-art CNNs. State-of-the-art networks such as LeNet,
ZFNet, AlexNet, GoogleNet, VGGNet, NIN and ResNet are
all constructed based on a combination of filter sizes of
11
11 with S ¼ 4, 7
7 with S ¼ 2, 5
5 with S ¼ 1, 5
5
with S ¼ 2, 3
3 with S ¼ 1, and 1
1 with S ¼ 1. All of
the aforementioned filter sizes and others can be easily rep-
resented using the matrix M. For instance, we represent
two filter sizes of 3
3 with S ¼ 1 and 7
7 with S ¼ 2
using the GFID below.
In Section 2.1, we showed that 3 PEs are sufficient to per-
form the convolutions for filter size of 3
3 with S ¼ 1.
Therefore, a CE containing only 3 neurons can perform the
convolutional computations. Considering a convolution of a
row of a filter map with its corresponding input pixels,
N þ 2 clock cycles are required to generate N output pixels
which belong to the same row of the output activation map.
For instance, in the given example in Table 2, 8 clock cycles
are required to generate the output pixels of the first row of
the output activation map (i.e., the first 6 output pixels).
This example can also be expressed using the GFID matrix
M as follows:

3 GENERALIZED FULLY-CONNECTED INSPIRED

DATAFLOW (GFID)
Let us define a generalized form of the FID by unrolling it The matrix M also confirms that there are only 3 active
over time as a matrix M:where each column of the matrix neurons at each time steps, highlighted in red. Considering

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142
TABLE 3
The Maximum Utilization Factor for Different Filter Sizes
[Wf ; S]
[1; 1] [3; 1] [5; 1] [5; 2] [7; 2]
Max UF 100% 100% 100% 83% 88%
T 1 3 5 3 4
filters with Wf ¼ 7 and S ¼ 2, the shift amounts within each
row of the output activation map is equal to 2 as shown in
the following matrix M:
While the higher stride value linearly decreases the number
of pixels in the output activation maps, it also reduces the
number of neurons required to perform the convolutional
computations. For instance, the above matrix M shows that
there are only 4 active neurons at each time step, while the
width of the filter Wf ¼ 7. According to the matrix M, 15
clock cycles are required to generate 5 output pixels in the
given example.
3.1 Utilization Factor for Different Filter Sizes
The number of clock cycles required to perform the convolu-
tions using GFID is equal to the number of input pixels. Con-
sidering Cin ¼ 1 and Hf ¼ 1, in order to generate N pixels of
an output activation map, S
N þ Wf  S clock cycles are
required to perform the convolutions according to Eq. (2).
Let us define the number of required PEs in the CE as T . The
number of pixels computed by each neuron is equal to N=T
when N is a multiple of T . Each neuron also requires Wf
clock cycles to generate an output pixel. Therefore, the utili-
zation factor of GFID can be expressed as
N

Wf
T However, the utilization factors of PEs for these cases
UF ¼
100:
S
N þ Wf  S
In Section 1, we discussed the importance of high per-
formance efficiency. The utilization factor of PEs in a convo-
lutional accelerator is also linearly proportional to its
performance efficiency. Any increase in the utilization fac-
tor of PEs exploited in the CE results in a higher perfor-
mance efficiency. Considering the fact that Wf and S are
usually small, a high UF is achieved for a large value of N.
In other words, the maximum achievable utilization factor
can be obtained as
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IEEE TRANSACTIONS ON COMPUTERS, VOL. 69, NO. 1, JANUARY 2020
Wf
UFmax ¼ lim UF ¼
100: (7)
N!1 T
S
Eq. (7) suggests that the highest performance efficiency is
[11; 4] obtained when N  ðWf  SÞ. Table 3 shows the maximum
utilization factors for filters with different filter sizes and
92%
3 stride values. Please note that Table 3 only shows the com-
monly used filter sizes while other filter sizes can be still
represented using the GFID.
4 GENERALIZED HARDWARE ARCHITECTURE
In Section 3, we showed that different filter sizes require dif-
ferent number of PEs per CE. In order to perform the com-
putations while achieving a high performance efficiency,
the number of PEs per CE has to be reconfigurable. In other
words, K instantiated PEs have to dynamically adapt to act
as a multiple of T PEs to achieve the maximum possible uti-
lization factor. The closed form solution for this strategy is
K ¼ LCMðTi Þ; i 2 f1; 3; 4; 5g; (8)
where LCM denotes the least common multiple. Using this
approach, 60 PEs are required to achieve the maximum pos-
sible utilization factor for all the network sizes listed in
Table 3. Depending on the required T , the 60 PEs can
dynamically behave as a set of T PEs. For instance, they can
act as 60, 20, 15 and 12 parallel CEs for T equal to 1, 3, 4 and
5, respectively, where each CE also contains 1, 3, 4 and 5
PEs. However, using 60 reconfigurable PEs is not trivial and
results in a complex architecture.
Observing commonly-used CNNs, we find out that T ¼ 1
and T ¼ 3 are the dominant minimum numbers of PEs.
More precisely, the two filters with Wf ¼ 5 and Wf ¼ 7 have
the least impact on the overall performance efficiency of
CNNs, since they are used in only one layer of CNNs. For
instance, the first layer of ResNets is fixed to the receptive
field of 7
7 and stride of S ¼ 2. The filter sizes of the
remaining layers are either fixed to 3
3 (for ResNet-18 and
ResNet-34) or a combination of 1
1 and 3
3 (for ResNet-
50, ResNet-101 and ResNet-152) [5]. Therefore, we use K ¼ 6
PEs inside the reconfigurable CE: the reason is twofold. First
of all, 6 PEs can be easily used as 2 and 6 CEs containing 3
and 1 PEs for T ¼ 3 and T ¼ 1, which are the dominant mini-
mum numbers of PEs for most of CNNs introduced in litera-
ture. Second, they can perform the computations for T ¼ 4
and T ¼ 5 with a minimum level of complexity for the
address generator unit. In this case, with K larger than what
strictly necessary, the number of clock cycles required to
perform the convolutional computations remains the same.
(6)
decreases. It is worth mentioning that while we only dis-
cussed about commonly-used filter sizes in CNNs, other fil-
ter sizes can be implemented using this approach.
Fig. 4 shows the architecture of the CE. It consists of two
main sub-blocks: the weight generator and K ¼ 6 PEs work-
ing in parallel. All the PEs share the same input activation
pixel while their weights are different. Each PE takes an
input activation map and its corresponding weight accord-
ing to the proposed GFID and performs the accumulation-
multiplication for the first row of the first input filter, i.e., W1 ,
W2 , . . ., WWf . This process takes Wf clock cycles and the
ARDAKANI ET AL.: FAST AND EFFICIENT CONVOLUTIONAL ACCELERATOR FOR EDGE COMPUTING
Fig. 4. The reconfigurable CE.
computed partial value is stored in a memory of L elements.
Afterwards, the PE starts the processing of another output
activation pixel, using the same weights. The convolutional
computations of the first row of the first input filter require
S
N þ Wf  S clock cycles, as discussed in Section 3.1.
Upon reaching this point, the partial value of the first output
activation pixel is read from the memory and the computa-
tions of the second row of the first input filter are performed
for S
N þ Wf  S clock cycles. In general, this procedure
is repeated for Hf times until the computations of the first fil-
ter are finished (i.e., upon completion of Hf
ðS
Nþ Wf 
SÞ clock cycles). At this point, the computation of the second
of the Cin filters starts. Upon completion of Cin
Hf
ðS

N þ Wf  SÞ clock cycles, the output value of each PE is
passed through the ReLU and the result is stored in the off-
chip memory. The ReLU as the non-linear function is nowa-
days a common choice in CNNs since ReLUs achieve a better
accuracy performance when compared to other non-linear
functions [3], [4], [5], [19], [21], [26], [27]. While we use
the ReLU as the non-linear function in this paper, other
non-linear functions can also be adopted in PEs.
4.1 Reconfigurable Weight Generator Unit
The weight generator unit provides each neuron an appro-
priate weight according to the proposed GFID. The weight
generator unit consists of 6 register sets where each set con-
tains 11 registers. The appropriate weight for each neuron
is provided by selecting among these shift registers. For
instance, we show the reconfigurability of the weight genera-
tor unit for the filter sizes of Wf ¼ 3 with S ¼ 1 and Wf ¼ 7
with S ¼ 2 as case-studies below.
4.1.1 Filters with Wf ¼ 3 and S ¼ 1
As discussed in Section 4, in case of Wf ¼ 3 and S ¼ 1, the
reconfigurable CE containing 6 neurons can function as two
CEs of 3 neurons each. Fig. 5a shows the weight generator
unit and its working path highlighted in black when using
Fig. 5. Involved hardware resources and paths in case of convolution computations for (a) Wf ¼ 3 and S ¼ 1, (b) Wf ¼ 7 and S ¼ 2.
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143
Wf ¼ 3 and S ¼ 1. It is worth noting that CEs are separated
using a dashed line. Each CE loads the weights of the first
row of the first filter (i.e., W1 , W2 and W3 ) through the input
ports denoted as In #1 and In #4 in Fig. 5a. These weights
then loop through the first register of each set to provide
one clock cycle delay for each neuron according to (3). Con-
sidering Eq. (6), the utilization factor of each neuron for this
case can be computed as
N
UF ¼ ; (9)
N þ2
which approaches 100 percent for large values of N.
4.1.2 Filters with Wf ¼ 7 and S ¼ 2
The convolutional computations for filters with Wf ¼ 5 and
S ¼ 1 are performed in a way similar to the convolutional
computations of the filters with Wf ¼ 3 and S ¼ 1, with the
difference that 4 neurons are active at each time step. There-
fore, 6 PEs are used to compute the convolutions for Wf ¼ 7
and S ¼ 2, while only 4 neurons are sufficient. As a result,
the reconfigurable CE functions as a single CE containing 6
PEs (see Fig. 5b). The CE loads the weights of the first row of
the first filter (i.e., W1 , W2 , . . ., and W7 ) through the input
port In #1 and they loop through the black paths in Fig. 5b. In
this scheme, the first two registers of each register set are
used to provide the required two delays for each PE, as
shown in Section 3. It is worth mentioning that while 12
registers are used in this case, only 7 of them contain the
weights. The utilization factor for this configuration is com-
puted as follows:
7N
UF ¼ : (10)
12N þ 30
Since 4 PEs are sufficient to perform the computations of
this case, using 6 neurons highly affects the utilization factor
and results in 53 percent for large values of N. However, the
final impact of this case when considering the computations
of the whole system is negligible due to the fact that this
configuration is usually used for one layer in the state-
of-the-art CNNs such as ResNets and GoogleNets.
4.1.3 Other Filters
Similar to the filter sizes of Wf ¼ 3 with S ¼ 1 and Wf ¼ 7
with S ¼ 2, any other filter size can also be implemented
using the proposed CE. Table 4 lists the maximum achievable
UF for commonly-used filter sizes in literature using the pro-
posed architecture. Comparing Table 4 with Table 3 shows
144
TABLE 4
The Maximum Utilization Factor for Different Filter
Sizes Using the Proposed CE
[Wf ; S]
[1; 1] [3; 1] [5; 1] [5; 2]
Max UF 100% 100% 83% 83%
that using K ¼ 6 PEs in parallel reduces the maximum
achievable UF for the filter sizes of Wf ¼ 5 with S ¼ 1
and Wf ¼ 7 with S ¼ 2 from 100 and 88 percent to 83 and
53 percent, respectively. However, the final impact of these
cases when considering the computations of the whole sys-
tem is negligible, as these configurations are normally used
for a few layers only in the state-of-the-art CNNs.
5 ZERO-ACTIVATION-SKIPPING CONVOLUTIONAL
ACCELERATOR
So far, we have introduced a reconfigurable CE that supports
different filter sizes with high utilization factors. We also
showed that the weight generator unit provides an appropri-
ate shift amount for each PE using shift registers. In fact, the
values of input weights (i.e., the values of each row of each
input filter) are circulated through the shift registers for Wf
clock cycles as discussed in Section 4. The size of the shift reg-
ister (i.e., the number of registers involved in the computa-
tion) varies depending on the filter size being used. For
instance, 3 registers are used for the convolutional computa-
tions for Wf ¼ 3 and S ¼ 1. More generally, the number of
registers required for the computations, which are hereafter
referred to as Nr , can be obtained by multiplication between
the required stride value and the number of PEs used in each
CE. Table 5 summarizes the number of involved registers in
the convolutional computations given Wf and S for com-
monly-used filter sizes while our architecture is not limited
to them.
Table 5 and Fig. 5 show that the position of weights in the
registers are unchanged after Nr clock cycles. This observa-
tion suggests that if any multiple of Nr activations in conse-
cutive order is equal to zero, we can skip their computations
using the proposed CE. Table 6a illustrates an example for
Wf ¼ 3 with S ¼ 1 when 6 consecutive activations are zero
(denoted in gray). According to Table 6a, the output values
Y5 , Y6 , Y7 and Y8 are zeros due to the multiplications with
zero-valued activations. Moreover, the output values Y3 and
Y4 are valid at clock cycles #4 since their remaining computa-
tions are noncontributory due to the multiplications with
zero-valued activations. As a result, the dataflow changes to
a simpler one as shown in Table 6b and the noncontributory
computations can be skipped without any impact on the
TABLE 5
The Number of Registers Used in the Convolutional
Process for Different Filter Sizes
[Wf ; S]
[1; 1] [3; 1] [5; 1] [5; 2]
# registers (Nr ) 1 3 6 6
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TABLE 6
The Complete Convolutional Process (a) without and
(b) with Skipping Zero-Valued Activations
[7; 2] [11; 4]
53% 92%
flow of weights through the registers. Similar approach can
be used for other filter sizes depending on their Nr value and
the number of consecutive zero-valued activations. There-
fore, noncontributory computations can be avoided using
the proposed method and CE. However, in order to take
advantage of zero-valued activations, an encoder/decoder is
required to specify the number of zero-valued activations to
the CE. Moreover, using the encoder/decoder allows us to
compress the activations in order to reduce memory accesses
to the off-chip memory.
The encoder can be easily realized using counters and
comparators to keep track of zero-valued activations as
shown in Fig. 6. The final output activations, which are
stored in the internal SRAM inside the CE, are first passed
to the ReLU and then to the encoder at each clock cycle. It is
worth noting that we use 15 bits for representation of the
value of input/output activations. The encoder starts count-
ing consecutive zero-valued activations right after detecting
the first zero-valued activation. The encoder passes its
incoming input directly to its output port along with a sin-
gle flag bit while counting the number of consecutive zero-
valued activations. As soon as the encoder detects that the
number of consecutive zero-valued activations is a multiple
of Nr denoted as n
Nr , it outputs the value of n using 15
bits along with a bit to distinguish between the zero and
non-zero activations. More precisely, the encoded word
[7; 2] [11; 4] denotes that the value of current activation and n upcoming
12 12 activations are zero when the flag bit is high. Otherwise, it
only denotes the value of non-zero activation. It is worth
ARDAKANI ET AL.: FAST AND EFFICIENT CONVOLUTIONAL ACCELERATOR FOR EDGE COMPUTING 145

TABLE 7
An Example of Encoding Procedure Given Nr ¼ 3
Encoder Write
CC
Input Output (Hex) Address
#1 128 0040 0
#2 0 0000 1
#3 0 0000 2
#4 0 0000 3
Fig. 6. The encoder.
#5 0 8001 2
#6 0 0000 3
mentioning that in case of detecting a multiple of Nr by the #7 0 0000 4
encoder, the value of n is overwritten into the memory ele- #8 0 8002 2
ment storing the second zero-valued activation of the corre- #9 0 0000 3
#10 512 0100 4
sponding sequence of zero-valued activations. Its appropriate #11 768 0180 5
address is also generated by the controller of the system. For
instance, Table 7 illustrates the encoding procedure given the
sequence f128; 0; 0; 0; 0; 0; 0; 0; 0; 512; 768g and Nr ¼ 3. Upon
the completion of the encoding procedure, the off-chip mem- Wf is also a small value compared to the processing time of
ory contains the consecutive encoded/compressed values convolutions for the first row of the first input filter (i.e.,
as f0040; 0000; 8002; 0000; 0100; 0180g in hexadecimal format. Wf ðS
N þ Wf  SÞ). More precisely, the input band-
The number of memory accesses to the off-chip memory for width from the ðWf Þth clock cycle to the ðS
N þ Wf  SÞth
the writing procedure using the encoded values is the same as clock cycle is occupied by input pixels only. Therefore, we
the dense model. can fill out this available bandwidth by pipelining the CEs
The decoder performs the inverse computations. It uses with up to bðS
N þ Wf  SÞ=Wf c stages, while the addi-
the flag bit to either skip the noncontributory computations tional latency overhead is negligible compared to the overall
or perform the computations of non-zero-valued activations. latency of the system.
In case of receiving a low flag bit, it passes the non-zero value
of activation to the CE. Otherwise, it first passes zero to the 5.2 Processing Time and Memory Accesses of
CE to store all the intermediate output values of neurons into ZASCA
their corresponding SRAM. It then passes the value of n to Earlier in Section 4 we showed that in convolutional pro-
the controller of the system to update the writing addresses cesses, a single CE computes N out of Hout
Wout pixels of
of the internal SRAMs in the CE. This unit is simply imple- one of Cout output activation maps within Cin
Hf
ðS

mented using multiplexers. N þ Wf  SÞ clock cycles. We also showed that the total num-
ber of weight passing occurrences for the computation of a
5.1 Exploiting Parallel CEs single convolutional layer is equal to Hout  1, which causes
While the proposed reconfigurable CE can efficiently per- additional ðWf  1Þ
ðHout  1Þ clock cycles for the compu-
form convolutional computations, using a single CE results tations of each row of the input filters. Considering p parallel
in a long latency and numerous memory accesses. To address CEs, the number of required clock cycles is expressed as
this issue, p CEs are instantiated in parallel to generate p out
of Cout output activation maps in parallel. Since the reconfig-  
Wout
Hout Cout
urable CE itself can function as up to 6 parallel CE, the upper CC ¼
ðS
N þ Wf  SÞ
Hf
Cin

N p
bound for the maximum number of CE is 6p in ZASCA.  
Therefore, the computational latency of ZASCA is effectively Cout
þ ðWf  1Þ
ðHout  1Þ
Hf
Cin
:
reduced by a p factor when compared to a single reconfigura- p
ble CE. Moreover, the memory accesses are reduced as well, (11)
since the input pixels are shared among the parallel CE, while
each CE is fed by a different set of weights. Eq. (11) suggests that the number of required clock cycles
Exploiting parallel CE requires an input bandwidth of for convolutional computations is independent of N for large
ð1 þ 6
P Þ
16 bits (6
p
16 for weights and 16 for input values of N (i.e., S
N  ðWf  SÞ) when not considering
pixels). However, most of the embedded and mobile devi- the weight passing overheads. In Section 5.1, we showed that
ces cannot provide such a high bandwidth. In fact, their input pixels are shared among all CEs and each pixel is read
bandwidth is limited by the bandwidth of the off-chip mem- at each clock cycle. This means that the number of memory
ory. For instance, most of the low-power DDRs (LPDDRs) accesses by input activation maps (MAimaps ) is equal to the
such as LPDDR4 provide the bit-width of up to 64 bits [23]. number of clock cycles required to complete the convolution.
As a result, the bandwidth of state-of-the-art convolutional On the other hand, the weights are read in the first Wf clock
accelerators for mobile devices is limited to 64 bits [8], [9], cycles out of a total of ðS
N þ Wf  SÞ. As a result, the
[13], [24]. To overcome this problem, ZASCA makes use of number of required memory accesses by filters to compute
pipelining. As discussed in Section 3, each input pixel is N out of Hout
Wout pixels of one out of Cout output activa-
read at each clock cycle while Wf weights are read only for tion map is equal to Cin
Hf
Wf . In general, the number
the first Wf clock cycles when performing the convolutional of memory accesses by filters (MAfilters ) can be computed as
process of the first row of the first input filter. The parameter follows:

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146
Fig. 7. The architecture of ZASCA and its layout.
 
Wout
Hout
MAfilters ¼ Hf
Wf
Cin

Cout :
N costs depending on p and N. Since the reconfigurable CE
Finally, the total number of memory accesses (MA) is a sum-
mation of memory accesses by filters, input activation maps
and output activation maps, where the number of memory
accesses by output activation maps (MAomaps ) is equal to
Wout
Hout
Cout . It is worth mentioning that so far, we
have computed the latency and memory access of ZASCA
performing on dense activations. Considering ZASCA per-
forming on sparse activations, the latency and number of
memory accesses by input activation maps (MAimaps ) are lin-
early reduced depending on the sparsity degree of activa-
tions. More precisely, the latency and number of memory
accesses by input activation maps are equal to (1 - Sp )
CC,
where Sp denotes the sparsity degree.
6 IMPLEMENTATION RESULTS
In this paper, we optimize ZASCA for a low-latency, low-
memory access implementation while keeping its power
consumption below the power budget of mobile devices,
limited to a few hundred mW [22]. Fig. 7 shows the architec-
ture of ZASCA, which consists of three main sub-blocks:
CEs, pipelining stages and encoder/decoder units. ZASCA
contains 32 reconfigurable CEs, each of which with 6 PEs.
Each PE is also associated with L ¼ 64 24-bit memory. The
pipelining stages provide the required amount of shifts
depending on the value of Wf using shift registers and mul-
tiplexers, as discussed in Section 5.1. The encoder/decoder
units also enable zero-activation-skipping convolutional
computations.
The p and N parameters do not only affect latency and
number of memory accesses, but also impact power and area
costs. Therefore, it is possible to obtain different trade-offs
between processing time, throughput and implementation
TABLE 8
The Effective Value of N and p in ZASCA
Depending on Wf and S
[Wf ; S]
[1; 1] [3; 1] [5; 1] [5; 2] [7; 2]
Neff 64 192 384 192 384
peff 192 64 32 64 32
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TABLE 9
The Main Characteristics of ZASCA
Technology TSMC 65nm GP CMOS
Core Area (Layout) 2.45 mm
2.45 mm
Gate Count (Including SRAMs) 1036 K
On-chip SRAMs 36.9 KBytes
Number of MAC Units 192
Supply Voltage 1V
Nominal Frequency 200 MHz
Peak Throughput (on dense activations) 76.8 G-ops/s
Arthmetic Precision 16-bit fixed-point
Supported CNN Sizes Filter Height (Hf ): 1-1024
Filter Width (Wf ): 1-11
# Filters (Cout ): 1-4096
# Channels (Cin ): 1-4096
Stride (S): 1-11
(12)
functions differently based on Wf and S, the effective values
of N and p vary for each case. Table 8 shows the effective val-
ues of N and p for commonly-used filter sizes in literature
while our architecture is not limited to them. The effective
values of N and p, denoted as Neff and peff respectively,
have to be used in all the equations reported in this paper
that rely on these two values.
6.1 Methodology
ZASCA was described in Verilog and placed and routed via
Cadence Virtuoso Layout Suite using TSMC 65 nm GP
CMOS technology. The resulting layout is shown in Fig. 7.
Artisan dual-port memory compiler was also used for the
implementation of internal SRAMs inside the CEs. ZASCA
works at a nominal frequency of 200 MHz for convolutional
processes. Table 9 lists a summary of the main characteris-
tics of ZASCA. For evaluation purposes, we use four state-
of-the-art CNNs: AlexNet, VGG-16, ResNet-18 and ResNet-
50 using [28], [29] in order to perform image classification
on ImageNet dataset [6]. We then evaluate ZASCA on
the aforementioned CNNs and show the implementation
results compared to the state-of-the-art Eyeriss, EEPS and
DSIP accelerators for edge devices. Eyeriss was fabricated
in TSMC 65 nm CMOS technology with a silicon area
of 12.52 mm2 (1,852 kgates) and tested on AlexNet and
VGGNet-16 [8], [24]. Since both Eyeriss and ZASCA were
implemented in TSMC 65 nm CMOS technology and use
16-bit fixed-point representations, a direct comparison of
these two implementations is fair. EEPS was fabricated in a
40-nm Low-Power (LP) technology with a silicon area of 2.4
mm2 and tested only on AlexNet. EEPS uses 16-bit MAC
units for the convolutions while modulating precision, fre-
quency and voltage to reduce its power/energy consump-
tion. For a fair comparison with EEPS, we perform a
technology scaling according to [14] only when comparing
in terms of power/energy consumption. DSIP was fabri-
cated in a 65-nm CMOS technology with a silicon area of
10.56 mm2 and tested only on AlexNet. Since both DSIP and
ZASCA were implemented in a 65 nm CMOS technology
[11; 4] and use 16-bit fixed-point representations, a direct comp-
arison of these two implementations is also fair. It is
192
64 worth mentioning that the implementation results of the
state-of-the-art Eyeriss, EEPS and DSIP accelerators were
ARDAKANI ET AL.: FAST AND EFFICIENT CONVOLUTIONAL ACCELERATOR FOR EDGE COMPUTING
Fig. 8. The breakdown of sparsity degree of CNNs when running on
ZASCA.
obtained from their original papers for comparison pur-
poses throughout this paper.
6.2 Sparsity Degree of Input Activations
As discussed in Section 1, the sparsity among activations is
an intrinsic occurrence in CNNs using the ReLU which
dynamically clamps all negatively-valued activations to
zero. Fig. 8 shows the breakdown of sparsity degree of acti-
vations in convolutional layers of AlexNet, VGG-16, ResNet-
18 and ResNet-50 when running on ZASCA. More spe-
cifically, we only considered the zero-valued activations
that can be skipped using ZASCA in our measurement of
the sparsity degree (see Section 5). The sparsity degrees were
measured over the validation set of ImageNet dataset. The
sparsity degree of each layer is linearly proportional to
the amount of speedup. For instance, 70 percent sparsity
degree denotes that 70 percent of MAC operations are
avoided on ZASCA and the computation time is reduced by
a factor of 2.3
.
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147
Fig. 9. The runtime performance of ZASCAD, ZASCAS, Eyeriss, EEPS
and DSIP. Note that the runtime performance of Eyeriss, EEPS and
DSIP is taken from their original papers.
6.3 Performance
We hereafter denote ZASCA performing convolutions on
dense activations as ZASCAD and ZASCA performing con-
volutions on sparse activations as ZASCAS. It is worth men-
tioning that the accuracy of the models using the dense
representation is the same as those using the sparse repre-
sentation for activations. Fig. 9 shows the performance of
ZASCAD and ZASCAS when running AlexNet, VGG-16,
ResNet-18 and ResNet-50 in terms of giga operations per sec-
ond compared to Eyeriss, EEPS and DSIP. It is worth noting
that Eyeriss was tested on AlexNet and VGG-16 while EEPS
and DSIP was only tested on AlexNet. Fig. 9 shows that ZAS-
CAD outperforms Eyeriss in terms of runtime performance
by factors of 1.4
and 3.1
when running AlexNet and
VGG-16, respectively. Skipping noncontributory computa-
tions further improves the runtime performance ranging
from 2
to 5.8
compared to Eyeriss. ZASCAD yields a
slightly better runtime performance compared to EEPS while
EEPS contains 64 more MAC units than ZASCA. Exploiting
the sparsity among the activations, ZASCAS performs the
convolutions of AlexNet 1.5
faster than EEPS. Finally, ZAS-
CAD and ZASCAS outperforms DSIP in terms of runtime
performance by factors of 2.7
and 4
, respectively.
As discussed in Section 5, all the PEs in ZASCA share the
same input activation pixel and the complete calculations of
each output pixel are performed serially, allowing all the PEs
to easily skip the noncontributory computations with zero-
valued input activation pixels. However, Eyeriss, EEPS and
DSIP rely on a 2D array of PEs and perform the computations
of each output pixel in a semi-parallel fashion. More pre-
cisely, the computations of each output pixel are split into
different parts where a certain number of these parts is per-
formed in parallel. The results of all the parts are then added
to make output pixels. In this way, PEs computing each part
take different activation pixels. In case of skipping the com-
putations with zero-valued input activation pixels of each
part, the runtime performance is still limited by the part con-
taining the least number of zero-valued input activation pix-
els. Note that having all the parts with the same number of
zero-valued input activation pixels is unlikely to happen
when exploiting the aforementioned approach. Moreover,
using batch sizes greater than 1 exacerbates the problem
since skipping the noncontributory computations is possible
only when all the batches contain zero-valued input activa-
tion pixels at the same time.
Eyeriss and DSIP use batch sizes greater than 1 to obtain
a lower number of memory accesses and to achieve a higher
energy efficiency. Using high batch sizes allows more filter
reuse and maximizes the utilization of all available PEs,
148
TABLE 10
The Total Latency of ZASCAD, ZASCAS,
Eyeriss, EEPS and DSIP
Latency (ms) / batch size
CNN AlexNet VGG-16 ResNet-18
ZASCAD 20.8/1 421.8/1 56/1
ZASCAS 14.2/1 246.8/1 30.4/1
Eyeriss [8] 115.3/4 4309.5/3 – –
EEPS [13] 21.3/1 – –
DSIP [14] 226.6/4 – –
Note that the total latency of Eyeriss, EEPS and DSIP is taken from their
original papers.
resulting in lower memory accesses and a higher energy
efficiency compared to the use of batch size of 1, as dis-
cussed in [7]. However, using this method results in a
higher computational latency. Increasing the number of PEs
is another way to improve the runtime performance at simi-
lar or better energy efficiency in existing dataflows [7]. The
choices of large batch sizes and large number of PEs aim at
better exploiting bandwidth and hardware resources, but
these are ineffective design choices when deploying to a
bandwidth-constrained edge computing device with a lim-
ited power budget. As a result, the number of PEs in Eyeriss
and DSIP is less than 200 with the maximum batch size of 4.
Moreover, Eyeriss, EEPS and DSIP use an on-chip SRAM
to store and reuse input activations in order to provide the
required parallelism for its processing units and reduce
memory accesses to the off-chip memory. However, such a
technique results in a long latency due to the bandwidth bot-
tleneck of the off-chip memory. Therefore, Eyeriss and DSIP
suffer from a high computational latency. On the other hand,
GFID enables ZASCA to perform the convolutional pro-
cesses right after fetching the first data from the off-chip
memory, which results in a low computational latency.
Table 10 summarizes the total latency (including the read-
ing/writing latency) of ZASCAD, ZASCAS, Eyeriss, EEPS
and DSIP. Eyeriss performs convolutional computations of
AlexNet and VGGNet-16 in 115.3 ms and 4.3 s while using a
batch size of 4 and 3, respectively. DSIP performs the convo-
lutions of AlexNet withing 226.6 ms when using a batch size
of 4. ZASCAD outperforms Eyeriss and DSIP in terms of
latency by factors ranging from 5.5
and 10.9
. Moreover,
ZASCAS further speeds up the computations by a factor of
1.7
on average compared to ZASCAD.
Fig. 10. The power consumption of ZASCAD, ZASCAS, Eyeriss, EEPS
and DSIP. Note that the runtime performance of Eyeriss, EEPS and
DSIP is taken from their original papers.
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ResNet-50
103.6/1
59.9/1
–
–
Fig. 11. The energy efficiency of ZASCAD, ZASCAS, Eyeriss, EEPS and
DSIP. Note that the energy efficiency of Eyeriss, EEPS and DSIP is
taken from their original papers.
Introduction of ResNet-18 was one of the first attempts on
the software side to reduce the computational complexity of
VGGNet-16 while keeping its accuracy performance almost
intact. In fact, ResNet-18 requires 8.5
less operations com-
pared to VGGNet-16. In this work, we showed that ZASCAD
also reflects a similar improvement factor (i.e., 7.5
) in the
total execution time compared to that of VGGNet-16 on the
hardware side when running ResNet-18. Moreover, using
the sparse representation for activations enables ZASCAS to
achieve the performance needed for real-time applications
(i.e., the minimum throughput of 30 frames per second)
when running ResNet-18.
6.4 Power and Energy Consumption
Fig. 10 reports average power consumption of ZASCAD,
ZASCAS, DSIP, EEPS and Eyeriss across AlexNet, VGG-16,
ResNet-18 and ResNet-50. Power consumptions of ZASCAD
and ZASCAS was obtained based on post-synthesis layout
by measuring actual switching activities over 100 images
randomly selected from the validation set. ZASCAD, ZAS-
CAS, Eyeriss and EEPS dissipate power ranging from 248 to
305 mW, meeting the power budget of edge devices. How-
ever, DSIP dissipates lower power due to its smaller number
of PEs when compared to the aforementioned accelerators.
Fig. 11 illustrates average energy consumption of ZAS-
CAD and ZASCAS compared to EEPS, DSIP and Eyeriss.
When performing the convolutional process of AlexNet on
dense activations, DSIP achieves the highest energy effi-
ciency when compared to ZASCAD, EEPS and Eyeriss.
However, ZASCAS outperforms DSIP by a factor of 1.4
.
Considering the inference computation of VGG-16, ZAS-
CAD is 2.7
energy efficient than Eyeriss while ZASCAS is
1.7
energy efficient than ZASCAD on average. Moreover,
ZASCAS achieves the highest energy efficiency among the
aforementioned accelerators when performing the convolu-
tions of ResNet-50.
6.5 Memory Accesses
Memory accesses to the off-chip DRAM play a crucial role in
the system energy efficiency as discussed in [8]. ZASCA
offers two techniques to reduce the number of memory
access. First, we showed that exploiting parallel tiles reduces
the number of accesses to input activations by a factor of p
(see Section 5.2). Second, ZASCA exploits sparsity among
activations to compress them using an encoder. As a result,
the number of memory accesses to input activations is
reduced depending on their sparsity degree. Fig. 12 shows
ARDAKANI ET AL.: FAST AND EFFICIENT CONVOLUTIONAL ACCELERATOR FOR EDGE COMPUTING
Fig. 12. The memory accesses of ZASCAD, ZASCAS, Eyeriss, EEPS
and DSIP. Note that the memory accesses of Eyeriss, EEPS and DSIP
is taken from their original papers.
the memory accesses to the off-chip DRAM for ZASCAD,
ZASCAS, DSIP, EEPS and Eyeriss. As discussed earlier, Eye-
riss and DSIP use high batch sizes to obtain a lower number
of memory accesses while this approach incurs a high
latency. However, ZASCAD obtains competitive memory
accesses while achieving up to 10.9
lower latency com-
pared to Eyeriss and DSIP. On the other hand, ZASCAS fur-
ther reduces memory access by a factor of 1.38
on average
over ZASCAD by compressing activations, resulting in the
lowest number of off-chip memory accesses when compared
with the state-of-the-art accelerators.
6.6 Roofline Model
The roofline model is commonly used to visually model the
performance of accelerators by showing their inherent hard-
ware limitations [15]. This model is obtained by tying arith-
metic intensity and the performance of a given accelerator,
where the arithmetic intensity is the number of operations
performed per byte of data accessed from the off-chip mem-
ory for each batch. It is worth noting that the performance
of architectures is bounded by their peak performance and
peak memory bandwidth. Since the memory bandwidth of
convolutional accelerator is fixed, we have only considered
the peak performance bound in the roofline model. The
roofline model of ZASCA along with the state-of-the-art
accelerators is depicted in Fig. 13, where the peak perfor-
mance bound of ZASCA and the state-of-the-art accelera-
tors are denoted using a solid line and dashed horizontal
lines, respectively. The roofline model shows that Eyeriss
Fig. 13. The roofline model of ZASCAD, ZASCAS, Eyeriss, EEPS and DSIP tested on AlexNet, VGG-16 and ResNet-50. The circles and solid/
dashed lines denote the average runtime performance and the peak performance bound, respectively.
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149
Fig. 14. The performance efficiency of ZASCAD, ZASCAS, Eyeriss,
EEPS and DSIP. Note that the performance efficiency of Eyeriss, EEPS
and DSIP is taken from their original papers.
achieves the highest arithmetic intensity among accelerators
performing convolutions on dense activations. This is mainly
because Eyeriss compresses sparse activations to reduce
memory accesses while still performing the convolutions on
dense activations. However, the main drawback of Eyeriss is
its poor performance. In fact, there is a huge gap between its
runtime performance and its peak performance bound as
denoted using an arrow in Fig. 13. The gap between the run-
time performance and the peak performance bound is com-
puted using the performance efficiency as shown in Fig. 14.
On the other hand, ZASCAD has a competitive arithmetic
intensity compared to Eyeriss while achieving the highest
performance efficiency among the state-of-the-art accelera-
tors. Performing the computations on sparse activations ena-
bles ZASCA to yields the highest arithmetic intensity and
performance efficiency. In fact, ZASCAS surpasses the peak
performance bound of ZASCA by skipping noncontributory
computations.
7 RELATED WORK
During the past few years, numerous works have been con-
ducted towards ASIC implementations of DNNs. However,
most of them were only tested on either small datasets or out-
dated CNNs which require order of magnitudes lower
parameters and computations [22], [30], [31], [32], [33], [34].
Recently, Google released a custom DNN processor tensor
processing unit (TPU) [35]. TPU is a programmable and
reconfigurable processor that can perform both fully-con-
nected and convolutional computations. However, its power
150
consumption exceeds the power budgets of embedded
devices [16].
Despite the existence of many works on accelerating
sparse multiplications [18], [36], [37], [38], [39], [40], only few
works have focused on exploiting sparsity to accelerate con-
volutional computations in CNNs, such as Cnvlutin [19],
Cambricon-X [20] and SCNN [21]. These architectures are
mainly designed to accelerate computations on the cloud
where unlimited data bandwidth is provided. Cnvlutin
relies on DaDianNao’s architecture [30] as its baseline and
achieves up to a 1.55
speedup by exploiting sparsity among
activations. Cambricon-X is a convolutional accelerator con-
taining 528 operators working at 1 GHz that can perform
convolutions of both dense and sparse models. As a result, it
can achieve a theoretical peak performance of 528 G-ops/s
when performing on dense models. Exploiting weight spar-
sity, it can skip ineffectual multiplications and speed up the
computations by up to a factor of 2.51
over its dense model,
yielding 544 G-ops/s at most [20]. Therefore, the highest
achievable performance efficiency of this accelerator is 41
and 103 percent when performing on dense and sparse mod-
els, respectively. However, ZASCA outperforms Cambri-
con-X in terms of performance efficiency by yielding the
peak performance efficiency of 94 and 168 percent when
performing on dense and sparse activations, respectively.
Finally, SCNN employs sparsity among both activations and
weights to reduce energy, latency and data transfer time.
Using this approach, SCNN managed to improve perfor-
mance and energy by factors of 2.7
and 2.3
compared to
its dense baseline, respectively. Despite the improvements
that these accelerators provide over their baseline, they fail
to meet the power and memory bandwidth constraint of
edge devices, which is limited to a few hundered mW [22].
However, ZASCA uses a substantially different dataflow
from the above designs and aims to accelerate convolutions
for low-power mobile devices at the edge. Moreover, since
no quantitative runtime result was provided, a direct com-
parison cannot be made with these works.
Recently, a few works have focused on minimizing
energy by modulating precision, frequency and supply volt-
age of their accelerator for each convolutional layer [9], [11],
[13]. In [9], a precision-scalable convolutional accelerator
(i.e., Envision), fabricated in 28 nm UTBB FD-SOI technol-
ogy, was introduced. This architecture dynamically adapts
itself depending on the required precision for each layer,
instead of using a fixed precision. More precisely, it exploits
a reconfigurable MAC which is able to perform a 16-bit, two
8-bit and four 4-bit multiplications/accumulations, depend-
ing on the required precision. As a result, using a dynamic
fixed-point technique allows to change frequency and sup-
ply voltage over time which results in a lower power/energy
consumption. Envision contains 256 reconfigurable MACs.
This accelerator performs the convolutional computations of
AlexNet to 21.3 ms (62.6 G-ops/s), and those of VGG-16 to
598.8 ms (51.3 G-ops/s), while its performance efficiency is
respectively limited to 38 and 32 percent on average. Similar
to Eyeriss, the low performance efficiency of Envision results
in a large gate count of 1950 kgates. More precisely, Envision
requires more parallelism to meet the timing constraint
of real-time edge devices, resulting in a large silicon area.
Despite the differences in the technology nodes and applied
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IEEE TRANSACTIONS ON COMPUTERS, VOL. 69, NO. 1, JANUARY 2020
circuit-level techniques, ZASCAS outperforms Envision in
terms of gate count (1.9
smaller), latency (1.5
and 2.4

lower), throughput (1.5
and 2.4
faster) and performance
efficiency (3.2
and 5
better).
In [12], a configurable accelerator framework (i.e., CAF)
was introduced. CAF was fabricated in 28 nm UTBB FD-SOI
technology with a silicon area of 34.9 mm2 and contains vari-
ous types of accelerators including 8 convolutional accel-
erator cores (the total of 288 MACs) for computer vision
applications. This architecture uses 16-bit fixed-point repre-
sentations and performs the convolutional computations
of AlexNet to 17.1 ms while consuming 61 mW at 0.575 V
and its performance efficiency is respectively limited to
67 percent. Despite the advanced technology nodes used in
CAF, ZASCAS outperforms this architecture in terms of
latency (1.2
lower), throughput (1.2
faster) and perfor-
mance efficiency (1.8
better).
As discussed in Section 6, ZASCAS outperforms Eyeriss
[8] in terms of gate count (1.8
smaller), latency (5.5
and
17.5
lower), throughput (2
and 5.8
faster), performance
efficiency (2.2
and 6.2
better) and energy efficiency (2.1

and 4.5
more efficient) while having roughly the same
number of memory accesses per batch. It is worth noting that
a direct comparison of ZASCA with the works published in
[9], [12] does not constitute a fair comparison, since they
dynamically modulate precision, frequency and supply volt-
age and use advanced technology nodes, which allows them
to instantiate more PEs while still having a low-power/
energy consumption. However, the introduced performance
efficiency metric can be used for a fair comparison as it
reflects the performance of the accelerators independent of
their technology nodes, precisions and optimization techni-
ques as shown in Fig. 14. It is worth mentioning that the cir-
cuit-level techniques used in [9], [11], [13] can also be used in
ZASCA to further improve its energy/power consumption.
When considering beyond standard CNNs, bottleneck
and depthwise separable convolutions are commonly used
nowadays due to computational considerations. The bottle-
neck convolutions were first introduced and used in very
deep residual networks such as ResNet-50 [5]. In the bottle-
neck architectures, each standard convolutional layer is usu-
ally sandwiched between two convolutional layers with the
filter size of 1
1. The first convolution is used to reduce the
dimensionality of inputs (i.e., the number of channels) and
the last one to restore it. In this way, a very deep network can
be achieved while using inexpensive 1
1 filters [26]. In this
work, we showed that ZASCA can successfully map the bot-
tleneck architecture used in ResNet-50 while skipping its
noncontributory computations with zero-valued input acti-
vation pixels. Using depthwise separable convolutions,
which is a building block of MobilNets [27], is another way
of reducing complexity of standard convolutions. In this
approach, each standard convolution is reformed into a
depthwise convolution followed by a pointwise convolution.
In the depthwise convolution, each input channel is associ-
ated with a separate 2D filter and the result of convolution
between each input channel and its filter constructs a single
output channel. On the other hand, the pointwise convolu-
tion is referred to the standard convolution with the filter
size of 1
1. Since each input activation channel contributes
only to one output activation channel in the depthwise
ARDAKANI ET AL.: FAST AND EFFICIENT CONVOLUTIONAL ACCELERATOR FOR EDGE COMPUTING
convolution, this convolutional process requires parallel
access to all the input activation channels and all the filters to
perform the computations in parallel. As a result, ZASCA
cannot fully exploit its available resources for this type of
convolution. More precisely, ZASCA can only perform the
depthwise convolutional computations of two output chan-
nels in parallel due to its limited data bandwidth. However,
the final impact of depthwise convolutional processes is neg-
ligible as the computational complexity of depthwise separa-
ble convolutions is dominated by the pointwise convolutions
[27]. Note that ZASCA can efficiently perform the pointwise
convolutional computations (see Section 4.1.3).
8 CONCLUSION
In this paper, we proposed ZASCA: an accelerator perform-
ing convolutions using either dense or sparse activations.
ZASCA exploits a dataflow (i.e., GFID) that allows to perform
the convolutional computations while reading input data
under the bandwidth bottleneck of edge devices, which maxi-
mizes its performance efficiency. Such a dataflow also enables
ZASCA to avoid noncontributory multiplications/accumula-
tions with zero-valued activations to further speedup the
computations. Compared to the state-of-the-art accelerator
for mobile devices, ZASCA enhances the latency, throughput,
energy efficiency and performance efficiency by up to 17.5
,
5.8
, 4.5
and 6.2
, respectively.
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Arash Ardakani received the BSc degree in elec-
trical engineering from the Sadjad University of
Technology, Mashhad, Iran, in 2011, and the MSc
degree from the Sharif University of Technology,
Tehran, Iran, in 2013. He is currently working
toward the PhD degree in electrical and computer
engineering at McGill University, Montre  al, QC,
Canada. His research interests include the VLSI
implementation of signal processing algorithms, in
particular channel coding schemes and machine
learning algorithms.
Carlo Condo received the MSc degree in electri-
cal and computer engineering from the Politecnico
di Torino and the University of Illinois at Chicago,
Chicago, Illinois, in 2010, and the PhD degree in
electronics and telecommunications engineering
from the Politecnico di Torino and IMT Atlantique,
in 2014. From 2015 to 2017, he was a post-
doctoral fellow with the ISIP Laboratory, McGill
University, where he was a McGill University dele-
gate at the 3GPP meetings for the fifth-generation
wireless systems standard (5G) in 2017. Since
2018, he has been a researcher with the Communication Algorithms
Design Team, Huawei Paris Research Center. His research is focused
on channel coding, design and implementation of encoder and decoder
architectures, digital signal processing, and machine learning.
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IEEE TRANSACTIONS ON COMPUTERS, VOL. 69, NO. 1, JANUARY 2020
Warren J. Gross (S’92–M’04–SM’10) received
the BASc degree in electrical engineering from
the University of Waterloo, Waterloo, ON, Can-
ada, in 1996, and the MASc and PhD degrees
from the University of Toronto, Toronto, ON,
Canada, in 1999 and 2003, respectively. He is a
professor and Louis-Ho faculty scholar in techno-
logical innovation with the Department of Electri-
cal and Computer Engineering, McGill University,
Montreal, QC, Canada. He currently serves as
chair of the department. His research interests
include the design and implementation of signal processing systems and
custom computer architectures. He served as the chair for the IEEE Sig-
nal Processing Society Technical Committee on Design and Implementa-
tion of Signal Processing Systems. He served as the general co-chair for
the IEEE GlobalSIP 2017 and the IEEE SiPS 2017 and the technical pro-
gram co-chair for SiPS 2012. He also served as an organizer for the
Workshop on Polar Coding in Wireless Communications at WCNC 2018
and WCNC 2017, the Symposium on Data Flow Algorithms and Architec-
ture for Signal Processing Systems (GlobalSIP 2014), and the IEEE ICC
2012 Workshop on Emerging Data Storage Technologies. He served as
an associate editor of the IEEE Transactions on Signal Processing and
as a senior area editor. He is a licensed professional engineer in the Prov-
ince of Ontario. He is a senior member of the IEEE.
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