{\rtf1 \ansi \ansicpg1252 \deff0 \stshfdbch2 \stshfloch0 \stshfhich0

\deflang1033 \deflangfe1033 {\fonttbl {\f0 \froman \fcharset0 \fprq2 {\*\panose

02020603050405020304}Times New Roman{\*\falt Times New Roman};}{\f2 \fnil
\fcharset134 \fprq0 {\*\panose 02010600030101010101}SimSun{\*\falt SimSun};}{\f3
\fnil \fcharset2 \fprq0 {\*\panose 05000000000000000000}Wingdings{\*\falt
Wingdings};}{\f4 \fswiss \fcharset0 \fprq0 {\*\panose
00000000000000000000}Helvetica{\*\falt Arial};}{\f5 \fswiss \fcharset0 \fprq0
{\*\panose 00000000000000000000}Helvetica-Bold{\*\falt Segoe Print};}}
{\colortbl;\red0\green0\blue0;\red128\green0\blue0;\red255\green0\blue0;\red0\green
128\blue0;\red128\green128\blue0;\red0\green255\blue0;\red255\green255\blue0;\red0\
green0\blue128;\red128\green0\blue128;\red0\green128\blue128;\red128\green128\blue1
28;\red192\green192\blue192;\red0\green0\blue255;\red255\green0\blue255;\red0\green
255\blue255;\red255\green255\blue255;\red0\green0\blue0;}{\stylesheet {\qj \li0
\ri0 \widctlpar \aspalpha \aspnum \adjustright \lin0 \rin0 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \f0 \snext0 \spriority0
Normal;}{\*\cs10 \rtlch \ltrch \snext10 \sunhideused \spriority99 Default Paragraph
Font;}}{\*\latentstyles \lsdstimax260 \lsdlockeddef0 \lsdsemihiddendef1
\lsdunhideuseddef1 \lsdqformatdef0 \lsdprioritydef99 {\lsdlockedexcept
\lsdsemihidden0 \lsdunhideused0 \lsdpriority0 \lsdlocked0 Normal;\lsdpriority99
\lsdlocked0 heading 1;\lsdpriority99 \lsdlocked0 heading 2;\lsdpriority99
\lsdlocked0 heading 3;\lsdpriority99 \lsdlocked0 heading 4;\lsdpriority99
\lsdlocked0 heading 5;\lsdpriority99 \lsdlocked0 heading 6;\lsdpriority99
\lsdlocked0 heading 7;\lsdpriority99 \lsdlocked0 heading 8;\lsdpriority99
\lsdlocked0 heading 9;\lsdpriority99 \lsdlocked0 index 1;\lsdpriority99 \lsdlocked0
index 2;\lsdpriority99 \lsdlocked0 index 3;\lsdpriority99 \lsdlocked0 index
4;\lsdpriority99 \lsdlocked0 index 5;\lsdpriority99 \lsdlocked0 index
6;\lsdpriority99 \lsdlocked0 index 7;\lsdpriority99 \lsdlocked0 index
8;\lsdpriority99 \lsdlocked0 index 9;\lsdpriority99 \lsdlocked0 toc
1;\lsdpriority99 \lsdlocked0 toc 2;\lsdpriority99 \lsdlocked0 toc
3;\lsdpriority99 \lsdlocked0 toc 4;\lsdpriority99 \lsdlocked0 toc
5;\lsdpriority99 \lsdlocked0 toc 6;\lsdpriority99 \lsdlocked0 toc
7;\lsdpriority99 \lsdlocked0 toc 8;\lsdpriority99 \lsdlocked0 toc
9;\lsdpriority99 \lsdlocked0 Normal Indent;\lsdpriority99 \lsdlocked0 footnote
text;\lsdpriority99 \lsdlocked0 annotation text;\lsdpriority99 \lsdlocked0
header;\lsdpriority99 \lsdlocked0 footer;\lsdpriority99 \lsdlocked0 index
heading;\lsdpriority99 \lsdlocked0 caption;\lsdpriority99 \lsdlocked0 table of
figures;\lsdpriority99 \lsdlocked0 envelope address;\lsdpriority99 \lsdlocked0
envelope return;\lsdpriority99 \lsdlocked0 footnote reference;\lsdpriority99
\lsdlocked0 annotation reference;\lsdpriority99 \lsdlocked0 line
number;\lsdpriority99 \lsdlocked0 page number;\lsdpriority99 \lsdlocked0 endnote
reference;\lsdpriority99 \lsdlocked0 endnote text;\lsdpriority99 \lsdlocked0 table
of authorities;\lsdpriority99 \lsdlocked0 macro;\lsdpriority99 \lsdlocked0 toa
heading;\lsdpriority99 \lsdlocked0 List;\lsdpriority99 \lsdlocked0 List
Bullet;\lsdpriority99 \lsdlocked0 List Number;\lsdpriority99 \lsdlocked0 List
2;\lsdpriority99 \lsdlocked0 List 3;\lsdpriority99 \lsdlocked0 List
4;\lsdpriority99 \lsdlocked0 List 5;\lsdpriority99 \lsdlocked0 List Bullet
2;\lsdpriority99 \lsdlocked0 List Bullet 3;\lsdpriority99 \lsdlocked0 List Bullet
4;\lsdpriority99 \lsdlocked0 List Bullet 5;\lsdpriority99 \lsdlocked0 List Number
2;\lsdpriority99 \lsdlocked0 List Number 3;\lsdpriority99 \lsdlocked0 List Number
4;\lsdpriority99 \lsdlocked0 List Number 5;\lsdpriority99 \lsdlocked0
Title;\lsdpriority99 \lsdlocked0 Closing;\lsdpriority99 \lsdlocked0
Signature;\lsdpriority99 \lsdlocked0 Default Paragraph Font;\lsdpriority99
\lsdlocked0 Body Text;\lsdpriority99 \lsdlocked0 Body Text Indent;\lsdpriority99
\lsdlocked0 List Continue;\lsdpriority99 \lsdlocked0 List Continue 2;\lsdpriority99
\lsdlocked0 List Continue 3;\lsdpriority99 \lsdlocked0 List Continue
4;\lsdpriority99 \lsdlocked0 List Continue 5;\lsdpriority99 \lsdlocked0 Message
Header;\lsdpriority99 \lsdlocked0 Subtitle;\lsdpriority99 \lsdlocked0
Salutation;\lsdpriority99 \lsdlocked0 Date;\lsdpriority99 \lsdlocked0 Body Text
First Indent;\lsdpriority99 \lsdlocked0 Body Text First Indent 2;\lsdpriority99
\lsdlocked0 Note Heading;\lsdpriority99 \lsdlocked0 Body Text 2;\lsdpriority99
\lsdlocked0 Body Text 3;\lsdpriority99 \lsdlocked0 Body Text Indent
2;\lsdpriority99 \lsdlocked0 Body Text Indent 3;\lsdpriority99 \lsdlocked0 Block
Text;\lsdpriority99 \lsdlocked0 Hyperlink;\lsdpriority99 \lsdlocked0
FollowedHyperlink;\lsdpriority99 \lsdlocked0 Strong;\lsdpriority99 \lsdlocked0
Emphasis;\lsdpriority99 \lsdlocked0 Document Map;\lsdpriority99 \lsdlocked0 Plain
Text;\lsdpriority99 \lsdlocked0 E-mail Signature;\lsdpriority99 \lsdlocked0 Normal
(Web);\lsdpriority99 \lsdlocked0 HTML Acronym;\lsdpriority99 \lsdlocked0 HTML
Address;\lsdpriority99 \lsdlocked0 HTML Cite;\lsdpriority99 \lsdlocked0 HTML
Code;\lsdpriority99 \lsdlocked0 HTML Definition;\lsdpriority99 \lsdlocked0 HTML
Keyboard;\lsdpriority99 \lsdlocked0 HTML Preformatted;\lsdpriority99 \lsdlocked0
HTML Sample;\lsdpriority99 \lsdlocked0 HTML Typewriter;\lsdpriority99 \lsdlocked0
HTML Variable;\lsdpriority99 \lsdlocked0 Normal Table;\lsdpriority99 \lsdlocked0
annotation subject;\lsdpriority99 \lsdlocked0 No List;\lsdpriority99 \lsdlocked0
1 / a / i;\lsdpriority99 \lsdlocked0 1 / 1.1 / 1.1.1;\lsdpriority99 \lsdlocked0
Article / Section;\lsdpriority99 \lsdlocked0 Table Simple 1;\lsdpriority99
\lsdlocked0 Table Simple 2;\lsdpriority99 \lsdlocked0 Table Simple 3;\lsdpriority99
\lsdlocked0 Table Classic 1;\lsdpriority99 \lsdlocked0 Table Classic
2;\lsdpriority99 \lsdlocked0 Table Classic 3;\lsdpriority99 \lsdlocked0 Table
Classic 4;\lsdpriority99 \lsdlocked0 Table Colorful 1;\lsdpriority99 \lsdlocked0
Table Colorful 2;\lsdpriority99 \lsdlocked0 Table Colorful 3;\lsdpriority99
\lsdlocked0 Table Columns 1;\lsdpriority99 \lsdlocked0 Table Columns
2;\lsdpriority99 \lsdlocked0 Table Columns 3;\lsdpriority99 \lsdlocked0 Table
Columns 4;\lsdpriority99 \lsdlocked0 Table Columns 5;\lsdpriority99 \lsdlocked0
Table Grid 1;\lsdpriority99 \lsdlocked0 Table Grid 2;\lsdpriority99 \lsdlocked0
Table Grid 3;\lsdpriority99 \lsdlocked0 Table Grid 4;\lsdpriority99 \lsdlocked0
Table Grid 5;\lsdpriority99 \lsdlocked0 Table Grid 6;\lsdpriority99 \lsdlocked0
Table Grid 7;\lsdpriority99 \lsdlocked0 Table Grid 8;\lsdpriority99 \lsdlocked0
Table List 1;\lsdpriority99 \lsdlocked0 Table List 2;\lsdpriority99 \lsdlocked0
Table List 3;\lsdpriority99 \lsdlocked0 Table List 4;\lsdpriority99 \lsdlocked0
Table List 5;\lsdpriority99 \lsdlocked0 Table List 6;\lsdpriority99 \lsdlocked0
Table List 7;\lsdpriority99 \lsdlocked0 Table List 8;\lsdpriority99 \lsdlocked0
Table 3D effects 1;\lsdpriority99 \lsdlocked0 Table 3D effects 2;\lsdpriority99
\lsdlocked0 Table 3D effects 3;\lsdpriority99 \lsdlocked0 Table
Contemporary;\lsdpriority99 \lsdlocked0 Table Elegant;\lsdpriority99 \lsdlocked0
Table Professional;\lsdpriority99 \lsdlocked0 Table Subtle 1;\lsdpriority99
\lsdlocked0 Table Subtle 2;\lsdpriority99 \lsdlocked0 Table Web 1;\lsdpriority99
\lsdlocked0 Table Web 2;\lsdpriority99 \lsdlocked0 Table Web 3;\lsdpriority99
\lsdlocked0 Balloon Text;\lsdpriority99 \lsdlocked0 Table Grid;\lsdpriority99
\lsdlocked0 Table Theme;\lsdpriority99 \lsdlocked0 Placeholder
Text;\lsdpriority99 \lsdlocked0 No Spacing;\lsdpriority99 \lsdlocked0 Light
Shading;\lsdpriority99 \lsdlocked0 Light List;\lsdpriority99 \lsdlocked0 Light
Grid;\lsdpriority99 \lsdlocked0 Medium Shading 1;\lsdpriority99 \lsdlocked0 Medium
Shading 2;\lsdpriority99 \lsdlocked0 Medium List 1;\lsdpriority99 \lsdlocked0
Medium List 2;\lsdpriority99 \lsdlocked0 Medium Grid 1;\lsdpriority99 \lsdlocked0
Medium Grid 2;\lsdpriority99 \lsdlocked0 Medium Grid 3;\lsdpriority99 \lsdlocked0
Dark List;\lsdpriority99 \lsdlocked0 Colorful Shading;\lsdpriority99 \lsdlocked0
Colorful List;\lsdpriority99 \lsdlocked0 Colorful Grid;\lsdpriority99 \lsdlocked0
Light Shading Accent 1;\lsdpriority99 \lsdlocked0 Light List Accent
1;\lsdpriority99 \lsdlocked0 Light Grid Accent 1;\lsdpriority99 \lsdlocked0 Medium
Shading 1 Accent 1;\lsdpriority99 \lsdlocked0 Medium Shading 2 Accent
1;\lsdpriority99 \lsdlocked0 Medium List 1 Accent 1;\lsdpriority99 \lsdlocked0 List
Paragraph;\lsdpriority99 \lsdlocked0 Quote;\lsdpriority99 \lsdlocked0 Intense
Quote;\lsdpriority99 \lsdlocked0 Medium List 2 Accent 1;\lsdpriority99 \lsdlocked0
Medium Grid 1 Accent 1;\lsdpriority99 \lsdlocked0 Medium Grid 2 Accent
1;\lsdpriority99 \lsdlocked0 Medium Grid 3 Accent 1;\lsdpriority99 \lsdlocked0 Dark
List Accent 1;\lsdpriority99 \lsdlocked0 Colorful Shading Accent
1;\lsdpriority99 \lsdlocked0 Colorful List Accent 1;\lsdpriority99 \lsdlocked0
Colorful Grid Accent 1;\lsdpriority99 \lsdlocked0 Light Shading Accent
2;\lsdpriority99 \lsdlocked0 Light List Accent 2;\lsdpriority99 \lsdlocked0 Light
Grid Accent 2;\lsdpriority99 \lsdlocked0 Medium Shading 1 Accent
2;\lsdpriority99 \lsdlocked0 Medium Shading 2 Accent 2;\lsdpriority99 \lsdlocked0
Medium List 1 Accent 2;\lsdpriority99 \lsdlocked0 Medium List 2 Accent
2;\lsdpriority99 \lsdlocked0 Medium Grid 1 Accent 2;\lsdpriority99 \lsdlocked0
Medium Grid 2 Accent 2;\lsdpriority99 \lsdlocked0 Medium Grid 3 Accent
2;\lsdpriority99 \lsdlocked0 Dark List Accent 2;\lsdpriority99 \lsdlocked0 Colorful
Shading Accent 2;\lsdpriority99 \lsdlocked0 Colorful List Accent
2;\lsdpriority99 \lsdlocked0 Colorful Grid Accent 2;\lsdpriority99 \lsdlocked0
Light Shading Accent 3;\lsdpriority99 \lsdlocked0 Light List Accent
3;\lsdpriority99 \lsdlocked0 Light Grid Accent 3;\lsdpriority99 \lsdlocked0 Medium
Shading 1 Accent 3;\lsdpriority99 \lsdlocked0
Medium Shading 2 Accent 3;\lsdpriority99 \lsdlocked0 Medium List 1 Accent
3;\lsdpriority99 \lsdlocked0 Medium List 2 Accent 3;\lsdpriority99 \lsdlocked0
Medium Grid 1 Accent 3;\lsdpriority99 \lsdlocked0 Medium Grid 2 Accent
3;\lsdpriority99 \lsdlocked0 Medium Grid 3 Accent 3;\lsdpriority99 \lsdlocked0 Dark
List Accent 3;\lsdpriority99 \lsdlocked0 Colorful Shading Accent
3;\lsdpriority99 \lsdlocked0 Colorful List Accent 3;\lsdpriority99 \lsdlocked0
Colorful Grid Accent 3;\lsdpriority99 \lsdlocked0 Light Shading Accent
4;\lsdpriority99 \lsdlocked0 Light List Accent 4;\lsdpriority99 \lsdlocked0 Light
Grid Accent 4;\lsdpriority99 \lsdlocked0 Medium Shading 1 Accent
4;\lsdpriority99 \lsdlocked0 Medium Shading 2 Accent 4;\lsdpriority99 \lsdlocked0
Medium List 1 Accent 4;\lsdpriority99 \lsdlocked0 Medium List 2 Accent
4;\lsdpriority99 \lsdlocked0 Medium Grid 1 Accent 4;\lsdpriority99 \lsdlocked0
Medium Grid 2 Accent 4;\lsdpriority99 \lsdlocked0 Medium Grid 3 Accent
4;\lsdpriority99 \lsdlocked0 Dark List Accent 4;\lsdpriority99 \lsdlocked0 Colorful
Shading Accent 4;\lsdpriority99 \lsdlocked0 Colorful List Accent
4;\lsdpriority99 \lsdlocked0 Colorful Grid Accent 4;\lsdpriority99 \lsdlocked0
Light Shading Accent 5;\lsdpriority99 \lsdlocked0 Light List Accent
5;\lsdpriority99 \lsdlocked0 Light Grid Accent 5;\lsdpriority99 \lsdlocked0 Medium
Shading 1 Accent 5;\lsdpriority99 \lsdlocked0 Medium Shading 2 Accent
5;\lsdpriority99 \lsdlocked0 Medium List 1 Accent 5;\lsdpriority99 \lsdlocked0
Medium List 2 Accent 5;\lsdpriority99 \lsdlocked0 Medium Grid 1 Accent
5;\lsdpriority99 \lsdlocked0 Medium Grid 2 Accent 5;\lsdpriority99 \lsdlocked0
Medium Grid 3 Accent 5;\lsdpriority99 \lsdlocked0 Dark List Accent 5;\lsdpriority99
\lsdlocked0 Colorful Shading Accent 5;\lsdpriority99 \lsdlocked0 Colorful List
Accent 5;\lsdpriority99 \lsdlocked0 Colorful Grid Accent 5;\lsdpriority99
\lsdlocked0 Light Shading Accent 6;\lsdpriority99 \lsdlocked0 Light List Accent
6;\lsdpriority99 \lsdlocked0 Light Grid Accent 6;\lsdpriority99 \lsdlocked0 Medium
Shading 1 Accent 6;\lsdpriority99 \lsdlocked0 Medium Shading 2 Accent
6;\lsdpriority99 \lsdlocked0 Medium List 1 Accent 6;\lsdpriority99 \lsdlocked0
Medium List 2 Accent 6;\lsdpriority99 \lsdlocked0 Medium Grid 1 Accent
6;\lsdpriority99 \lsdlocked0 Medium Grid 2 Accent 6;\lsdpriority99 \lsdlocked0
Medium Grid 3 Accent 6;\lsdpriority99 \lsdlocked0 Dark List Accent 6;\lsdpriority99
\lsdlocked0 Colorful Shading Accent 6;\lsdpriority99 \lsdlocked0 Colorful List
Accent 6;\lsdpriority99 \lsdlocked0 Colorful Grid Accent 6;}}{\*\generator WPS
Office}{\info {\author This PC}{\operator Do Hoang Anh (K15 HL)}{\creatim
\yr2021 \mo3 \dy3 \hr17 \min6 }{\revtim \yr2021 \mo3 \dy3 \hr17 \min31 }
{\version1 }{\nofpages1 }}\paperw12240 \paperh15840 \margl1260 \margr960 \margt1320
\margb780 \gutter0 \ftnbj \aenddoc \jcompress1 \viewkind1 \viewscale120
\viewscale120 \asianbrkrule \allowfieldendsel \snaptogridincell \hyphauto1
{\*\fchars !),.:;?]\'7d{\uc1 \u168 ?}{\uc1 \u183 ?}{\uc1 \u711 ?}{\uc1 \u713 ?}
{\uc1 \u8213 ?}{\uc1 \u8214 ?}{\uc1 \u8217 ?}{\uc1 \u8221 ?}{\uc1 \u8230 ?}{\uc1
\u8758 ?}{\uc1 \u12289 ?}{\uc1 \u12290 ?}{\uc1 \u12291 ?}{\uc1 \u12293 ?}{\uc1
\u12297 ?}{\uc1 \u12299 ?}{\uc1 \u12301 ?}{\uc1 \u12303 ?}{\uc1 \u12305 ?}{\uc1
\u12309 ?}{\uc1 \u12311 ?}{\uc1 \u65281 ?}{\uc1 \u65282 ?}{\uc1 \u65287 ?}{\uc1
\u65289 ?}{\uc1 \u65292 ?}{\uc1 \u65294 ?}{\uc1 \u65306 ?}{\uc1 \u65307 ?}{\uc1
\u65311 ?}{\uc1 \u65341 ?}{\uc1 \u65344 ?}{\uc1 \u65372 ?}{\uc1 \u65373 ?}{\uc1
\u65374 ?}{\uc1 \u65504 ?}}{\*\lchars ([\'7b{\uc1 \u183 ?}{\uc1 \u8216 ?}{\uc1
\u8220 ?}{\uc1 \u12296 ?}{\uc1 \u12298 ?}{\uc1 \u12300 ?}{\uc1 \u12302 ?}{\uc1
\u12304 ?}{\uc1 \u12308 ?}{\uc1 \u12310 ?}{\uc1 \u65288 ?}{\uc1 \u65294 ?}{\uc1
\u65339 ?}{\uc1 \u65371 ?}{\uc1 \u65505 ?}{\uc1 \u65509 ?}}\fet2 {\*\ftnsep
\pard \plain {\insrsid \chftnsep \par }}{\*\ftnsepc \pard \plain {\insrsid
\chftnsepc \par }}{\*\aftnsep \pard \plain {\insrsid \chftnsep \par }}
{\*\aftnsepc \pard \plain {\insrsid \chftnsepc \par }}\sectd \sbkpage
\pgwsxn10620 \pghsxn13140 \marglsxn1260 \margrsxn960 \margtsxn1320 \margbsxn780
\guttersxn0 \headery720 \footery720 \pgbrdropt0 \sectdefaultcl \endnhere \pard
\plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar
\aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360 \itap0
\fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 The _______ is a computer
subsystem that performs operations on data.}{\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 CPU}
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard
\plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar
\aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2
\rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 memory}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4
\hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 I/O
hardware}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
\par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 bus subsystem}{\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi360
\li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par
}\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 _______ is a stand-
alone storage location that holds data temporarily.}{\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240
\li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 An ALU}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 A register}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 A control unit}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4
\hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 A
tape drive}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par
}\pard \plain \qj \fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar
\aspalpha \aspnum \adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0
\lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr
\tx260 \tql \tx360 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch
\af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 _______ is
a unit that can add two inputs.}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0
\lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql
\tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 An ALU}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 A register}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 A control unit}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0
\lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql
\tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 A tape drive}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par
}\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 A register in a CPU
can hold _______.}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4
\cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 only data}{\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240
\li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 only instructions}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4
\hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 only
program counter values}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 data, instruction, or
program counter values}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf3 \par }\pard \plain \qj \fi360 \li0 \ri0 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin0 \rin0 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-360
\li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360 \itap0 \fs21 \kerning2 \rtlch
\ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 A control unit with five wires can define up to
_______ operations.}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0
\fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 5}{\fs24 \kerning2 \rtlch \ltrch
\dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0
\sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright
\lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich
\af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
10}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
\par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 16}{\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 32}
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 \par }\pard
\plain \qj \fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2
\hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \par }\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260
\tql \tx360 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 A word can be
_______ bits.}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4
\cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 only 8}{\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240
\li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 only 16}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 only 32}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf3 8, or 16, or 32}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf3 \par }\pard \plain \qj \fi360 \li0 \ri0 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin0 \rin0 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-360
\li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360 \itap0 \fs21 \kerning2 \rtlch
\ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 If the memory address space is 16 MB and the word
size is 8 bits, then _______ bits are needed to access each word.}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 8}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0
\fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 16}{\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240
\li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf3 24}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf3 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 32}{\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi360
\li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par
}\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 The data in _______ is
erased if the computer is powered down.}{\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch
\ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf3 RAM}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4
\hich \af4 \loch \f4 \cf3 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 ROM}
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard
\plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar
\aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2
\rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 a tape drive}{\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 a
CD-ROM}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
\par }\pard \plain \qj \fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar
\aspalpha \aspnum \adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0
\lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr
\tx260 \tql \tx360 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch
\af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 _______ is
a memory type with capacitors that need to be refreshed periodically.}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 SRAM}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0
\fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 DRAM}{\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240
\li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 ROM}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 CROM}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par
}\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 _______ is a memory
type with traditional flip-flop gates to hold data.}{\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240
\li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf3 SRAM}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0
\fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 DRAM}{\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240
\li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 ROM}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 CROM}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par
}\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 There are _______
bytes in 16 Terabytes.}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 2}{\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 \super1 16}{\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 \super1 \par }\pard \plain
\qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 2}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \super1 40}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \super1 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 2}{\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \super1 44}{\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \super1 \par }\pard \plain
\qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 2}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \super1 56}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \par }\pard \plain \qj \fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch
\ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-360 \li360 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin360
\rin0 \tqr \tx260 \tql \tx360 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich
\af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
_______ can be programmed and erased using electronic impulses but can remain in a
computer during erasure.}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0
\fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 ROM}{\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240
\li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 PROM}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0
\fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 EPROM}{\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240
\li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch
\af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 EEPROM}
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 \par }\pard
\plain \qj \fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2
\hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \par }\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260
\tql \tx360 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 _______ is a
type of memory in which the user, not the manufacturer, stores programs that cannot
be overwritten.}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
\par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 ROM}{\fs24 \kerning2 \rtlch \ltrch
\dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0
\sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright
\lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich
\af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3
PROM}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
\par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 EPROM}{\fs24 \kerning2 \rtlch \ltrch
\dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0
\sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright
\lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich
\af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
EEPROM}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
\par }\pard \plain \qj \fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar
\aspalpha \aspnum \adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0
\lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr
\tx260 \tql \tx360 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch
\af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 Main
memory in a computer usually consists of large amounts of ______ speed memory.}
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard
\plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar
\aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2
\rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 high}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0
\lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql
\tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 medium}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf3 low}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 very high speed }
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard
\plain \qj \fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2
\hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \par }\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260
\tql \tx360 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 A _______ is a
storage device to which the user can write information only once.}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 CD-ROM}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 CD-R}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 CD-RW}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 CD-RR}{\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi360
\li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par
}\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 A _______ is a storage
device that can undergo multiple writes and erasures.}{\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240
\li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 CD-ROM}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 CD-R}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf3 CD-RW}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf3 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 CD-RR}{\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi360
\li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par
}\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 The smallest storage
area on a magnetic disk that can be accessed at one time is a _______.}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 track}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 sector}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 frame}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 head}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par
}\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 If the memory has 2}
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \super1 32 }
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 words, the
address bus needs to have _______ wires.}{\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 8}
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard
\plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar
\aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2
\rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 16}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4
\hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 32}
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard
\plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar
\aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2
\rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 64}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4
\hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi360 \li0 \ri0 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin0 \rin0 \itap0
\fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-
360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360 \itap0 \fs21 \kerning2 \rtlch
\ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 A control bus with eight wires can define _______
operations.}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
\par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 8}{\fs24 \kerning2 \rtlch \ltrch
\dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0
\sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright
\lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich
\af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
16}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
\par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 256}{\fs24 \kerning2 \rtlch \ltrch
\dbch \af4 \hich \af4 \loch \f4 \cf3 \par }\pard \plain \qj \fi-240 \li600 \ri0
\sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright
\lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich
\af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
512}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard
\plain \qj \fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2
\hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \par }\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260
\tql \tx360 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 A _______
controller is a high-speed serial interface that transfers data in packets.}
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard
\plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar
\aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2
\rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 SCSI}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0
\lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql
\tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 USB}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 FireWire}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0
\lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql
\tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 USB and FireWire}
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 \par }\pard
\plain \qj \fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2
\hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \par }\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260
\tql \tx360 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 The three steps
in the running of a program on a computer are performed in the specific order
_______.}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
\par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 fetch, execute, and decode}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 decode, execute, and fetch}{\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3
fetch, decode, and execute}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf3 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 decode, fetch, and
execute}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
\par }\pard
\plain \qj \fi360 \li0 \ri0 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin0 \rin0 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2
\hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch
\f4 \cf0 \par }\pard \plain \qj \fi-360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280
\slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin360 \rin0 \tqr \tx260
\tql \tx360 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 In the _______
method for synchronizing the operation of the CPU with an I/O device, the I/O
device informs the CPU when it is ready for data transfer.}{\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-
240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 programmed I/O}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4
\hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3
interrupt-driven I/O}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4
\cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 DMA}{\fs24 \kerning2 \rtlch \ltrch
\dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0
\sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright
\lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich
\af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
isolated I/O}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
\par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-360
\li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360 \itap0 \fs21 \kerning2 \rtlch
\ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 In the _______ method for synchronizing the
operation of the CPU with an I/O device, the CPU is idle until the I/O operation is
finished.}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
\par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf3 programmed I/O}{\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-
240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf0 interrupt-driven I/O}{\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 DMA}
{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard
\plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar
\aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2
\rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 isolated I/O}{\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi360 \li0 \ri0 \lisb0
\lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin0 \rin0 \itap0
\fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2
\rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-
360 \li360 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum
\adjustright \lin360 \rin0 \tqr \tx260 \tql \tx360 \itap0 \fs21 \kerning2 \rtlch
\ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch
\af4 \hich \af4 \loch \f4 \cf0 In the _______ method for synchronizing the
operation of the CPU with an I/O device, a large block of data can be passed from
an I/O device to memory directly.}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4
\hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40
\lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600
\rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0
\loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0
programmed I/O}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4
\cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0
\widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21
\kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch
\ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 interrupt-driven I/O}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qj
\fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0 \sl280 \slmult0 \widctlpar \aspalpha
\aspnum \adjustright \lin600 \rin0 \tql \tx600 \itap0 \fs21 \kerning2 \rtlch \ltrch
\dbch \af2 \hich \af0 \loch \af0 {\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich
\af4 \loch \f4 \cf3 DMA}{\fs24 \kerning2 \rtlch \ltrch \dbch \af4 \hich \af4
\loch \f4 \cf0 \par }\pard \plain \qj \fi-240 \li600 \ri0 \sb40 \lisb0 \lisa0
\sl280 \slmult0 \widctlpar \aspalpha \aspnum \adjustright \lin600 \rin0 \tql \tx600
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 isolated I/O}{\fs24
\kerning2 \rtlch \ltrch \dbch \af4 \hich \af4 \loch \f4 \cf0 \par }\pard \plain \qc
\li0 \ri0 \lisb0 \lisa0 \widctlpar \aspalpha \aspnum \adjustright \lin0 \rin0
\tql \tx720 \tql \tx1440 \tql \tx2160 \tql \tx2880 \tql \tx3600 \tql \tx4320
\tql \tx5040 \tql \tx5760 \tql \tx6480 \tql \tx7200 \tql \tx7920 \tql \tx8640
\itap0 \fs21 \kerning2 \rtlch \ltrch \dbch \af2 \hich \af0 \loch \af0 {\b1 \fs24
\kerning2 \rtlch \ltrch \dbch \af5 \hich \af5 \loch \f5 \cf3 \par }}