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Rev. Rev. Issued: 00-10-03 Ta Document Format Langue Page No. of pages
Rev. Rev. Check 1:00-10- ZAB A4 E 1 13
Rev. Rev. Check 2:
Dept. 1 Dept. 2 Der.from/Repla.: Released: 00-10-11 Ta
Replaced by:
ICA 3BHS102402E62
2
CONTENT PAGE
3 LIMITERS......................................................................................................................................... 9
3.1 Computer representation.............................................................................................................................9
3.2 Short model description ............................................................................................................................. 10
3.3 List of limiter settings.................................................................................................................................. 11
4 BIBLIOGRAPHIC REFERENCES.................................................................................................. 12
3BHS102402E62
3
+
S X>0
- -
S X>0
fr o m o v e r - e x c it a io n
+ Up+ TB1 U p+
KR TC1 KR
lim ite r s ( O E L )
fr o m u n d e r - e x c ita io n + U p+
LV 1+sTC 2 1+sTC 1
lim ite r s ( U E L ) S
H V G a te 1+sTB 2 1+sTB 1 KR 1
G a te +
1 -
U T S U p- TB1 U p- U p-
1+sTR
M a c h in e KR TC1 KR
v o lt a g e [p .u .]
+
U ST Up+ TO B1 U p+
S ta b iliz in g KR TO C1 KR
s ig n a l
U _ V /H z fro m P S S
1+sTU C 2 1+sTU C 1
fro m V /H z LV
1+sTU B 2 1+sTU B 1
lim it e r G a te
U p- TUB1 U p-
KR TUC1 KR
U T s e t p o in t [ p .u .] + S Up+ TO B1 U p+
+ + KR TO C1 KR
Q T 1
K IR
M a c h in e 1+sTR 1+sTO C 2 1+sTO C 1
r e a c t iv e 1+sTO B 2 1+sTO B 1
p o w e r [p .u .]
U p- TO B1 Up-
KR TO C1 KR
PT 1
K IA
M a c h in e 1+sTR
a c t iv e
P S S 2A acc.
p o w e r [p .u .]
to IE E E 4 2 1 .5
1992
Dw 1
1+sTR IF
R o t o r a n g u la r m a c h in e
fr e q u e n c y d e v ia t io n fie ld
[p .u .] c u rre n t
VSC m ax SES [p .u .]
IT
KSC K ID
M a c h in e V VC m ax EF
c u rre n t [p .u .] + m a c h in e
KVC p X 2
S x + fie ld
+ 1 + +
cos
1
1+sTs S - p S
1 v o lt a g e
j - KE +sTE [p .u .]
M a c h in e +
p h a s e a n g le s in p S X 2 VC O M P E F m in
SHUNT
= a c o s (P .F .) + S E (E F )
U T
M a c h in e 1 .0
v o lta g e [p .u .]
3BHS102402E62
4
Stabilizing networks
All the required measuring values are submitted to first order transfer
functions that represent the measuring time constants for these signals. Since
the measuring time constants for the signals UT, QT, PT and are
approximately the same, all measuring time constants may be represented by
TR.
The actual value of machine terminal voltage UT is the main controlled
variable.
The actual value of reactive power QT at machine terminals is required for the
parallel operation with the grid and/other machines. The QT signal is weighted
with a factor KIR which can be adjusted either to obtain an droop
characteristic (KIR negative) or a reactive power compensation (KIR positive)
as normally required to compensate the voltage drop at the unit step up
transformer.
The PT signal represents the active power at machine terminals and is
normally not required. This path is mainly provided for special systems in
which a large resistive voltage drop is expected. In such cases the required
compensation may be adjusted with the factor KIA.
The voltage set point for UT is added to the reactive an active power
compensation signal. The result of this summation and the signal coming from
the V/Hz limiter (U_V/Hz) are applied to a lower value gate (LV gate) assuring
that the effective setpoint will not exceed the value of the signal U_V/Hz
coming from the V/Hz limiter.
The difference between the effective voltage set point and the filtered value of
the actual terminal voltage UT represents the voltage error signal.
3BHS102402E62
5
The voltage error signal and the signal from the under excitation limiters (UEL)
are applied to a higher value gate (HV Gate). Only the highest signal is
transmitted to the gate output.
The output of the HV Gate and the signal from the over excitation limiters
(OEL) are applied to a LV gate. This gate transmits the lowest input signal to
the output.
The output of the LV Gate is added to the stabilizing signal UST coming from
PSS. The resulting signal is applied to the main controller.
Three stabilizing networks are provided for operation in voltage control mode
(AVR), over excitation limiters control mode (OEL) and under excitation
limiters control mode (UEL). In reality, the hardware has only one lead lag
stabilizing network with three sets of selectable time constants for each one of
the three above operating conditions (AVR, OEL and UEL). This model
considers three separate networks because most of commercial programs for
power system studies do not allow dynamic changes of lead lag time
constants during program execution.
Each of the assumed stabilizing networks for the above mentioned operation
modes consist of two antiwindup lead lag filters and a common amplification
factor KR. This last factor determines the steady state gain of the control loop.
The lead lag filters are adjustable and are provided for optimum phase and
gain compensation in AVR, OEL and UEL operation modes. The limitation
signals depend on the positive and negative ceiling factors for the specific
plant (Up+, Up-).
Four different kinds of supplies for power stage are foreseen in this model.
a) Shunt supply from synchronous machine terminals.
b) Shunt supply with DC-side series compounding.
c) Shunt supply with AC-side vectorial compounding.
d) External supply (e.g. from PMG or auxiliary line)
The applicable supply system can be selected by means of the flags SHUNT,
VCOMP and the amplification factor KSC.
The gate control unit and the converter stage is represented by a first order
transfer function with a time constant Ts.
The multiplier at the output of the gate control and converter stage represents
the influence of the excitation system supply on the converter output.
In case that the model is used to represent a static excitation system the flag
SES shall be set to 1.0. With this setting, the exciter machine is by-passed
and the feedback that represents the voltage drop on converter output (KID) is
influenced by the synchronous machine field current.
In case of indirect excitation systems, the flag SES is set to 0.0 in order to
include exciter transfer function in the control loop. In this case the value of
the synchronous machine field voltage EF represents an approach for the
exciter field current.
3BHS102402E62
6
The simplified exciter machine model can be used to represent most common
types of exciter machine like brushless, DC, and AC exciters with stationary
diodes [1], [2].
3BHS102402E62
7
3BHS102402E62
8
+ +
V1 s.TW1 s.TW2 (1 s T8)
N
1+s.T1 1+s.T3 UST
1 + s.TW1 1 + s.TW2 (1 s T9)M Ks1 1+s.T2 1+s.T4
+ -
USTmin USTmin
Ks3
3BHS102402E62
9
3BHS102402E62
10
3 Limiters
3.1 Computer representation
M a c h in e
fre q u e n c y V / H z L im ite r
fT [p .u ] 1 x y
y = K V H Z .x + U _ fn -K V H Z UTM AX
1+ sTR
M a c h in e
-
U _ V /H Z
te r m in a l KVHZ S x>0 D e la y V o lt/H z
v o lta g e + 0
U T [p .u ] U _ fn T_V_Hz in f lu e n c e
UTM AX s ig n a l
to A V R
M a c h in e f ie ld
c u rre n t
[p .u .]
IF [p .u .]
M a x . f ie ld c u r r e n t lim it e r
1 -
S K IF m a x
1+ sTR
+ 2
+
S x p
Em axF
- y
KCF
1 x
KHF s x>y
x>0 0
IF m a x 1
IF m a x 2
IF th 1
S e t p o in t 2 f o r IF th 2
I F m a x lim it e r
( o p t io n )
LV
G a te
S ta to r
C u rre n t S t a t o r c u r r e n t lim it e r
IT [p .u .]
1 -
1+ sTR
S K IT in d
+ 2
+
S x p
E m axS
- y T o O E L lim it e r
KCS g a te o f A V R
1 x
KHS s x>y
x>0 0
IT m a x
T o U E L lim it e r
IT th g a te o f A V R
-
+
S K IT c a p
M in . f ie ld c u r r e n t lim ite r
+ HV
S K IF m in G a te
-
I F m in
G e n e ra to r
r e a c tiv e
pow er
1
P / Q lim it e r
Q T [p .u .] -
1+ sTR
S KPQ
G e n e ra to r +
te r m in a l
v o lta g e
U T [p .u .]
x2
G e n e ra to r
a c tiv e p o w e r
P T [p .u .] L o o k -u p
1
T a b le p
1+ sTR y n = f (xn)
3BHS102402E62
11
The Volt/Hz characteristic consists of a linear function that is defined by the settings
KVHZ and U_fn. The resulting characteristic represents the allowed maximum
voltage setpoint for the measured frequency. If the calculated value is higher than
the machine actual voltage UT, the V/Hz signal is switched to the LV-gate of the
AVR (ref to fig 1.) after an adjustable time delay T_V_HZ. The value UTmax limits
the setpoint to the maximum allowed machine voltage.
The maximum field current limiter has a maximum (IFmax) and a thermal (IFth)
limitation setpoint. Each of the limitation setpoints has two sets of parameters that
can be switched dynamically (option) by means of a logical signal. Normally the
active setpoint is IFmax that corresponds to the ceiling field current of the excitation
system. In case that the field current actual value exceeds the thermal limitation
setpoint, the square of the difference between the actual value and thermal limitation
setpoint will integrated proportionally to the heating time constant KHF. If the
integrator output reaches the value EmaxF, the active limiter setpoint is switched to
the thermal setpoint reducing the field current to the corresponding thermal limit. If
the actual field current value is reduced below the thermal limitation setpoint, the
square of the difference between the actual value and thermal limitation setpoint will
integrated proportionally to the field cooling time constant KCF. The KIFmax output
gain is intended for the optimizing of this control loop characteristic. The p.u. system
for field quantities is normally based on the field current value over the air gap
characteristic which gives rated machine voltage.
The stator current limiter operates like the maximum field current limiter however it
acts in both over and under excitation conditions. It has individual output gains for
over (KITind) and under excitation (KITcap) limitation conditions.
The minimum field current limiter has only one limitation setpoint IFmin and an
output gain factor KIFmin.
The P/Q limiter consists basically of a reactive power limiter with an adjustable look-
up table of reactive power setpoints. The look-up table is given by 5 reactive power
limitation values corresponding to 5 levels of active power (0.0, 0.25, 0.50, 0.75,1.00
p.u.). All intermediate values are calculated by linear interpolation. Since the stability
limits of the synchronous machine depend on the square of the terminal voltage, the
P/Q limitation characteristic is corrected with the square of the machine terminal
voltage. The difference between the actual reactive power and the calculated
septpoint builds the limitation signal that is submitted to a gain factor KPQ intended
for optimizing of limitation control characteristic.
3BHS102402E62
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1) IFn/IFag : Ratio between rated field current and field current at air gap line required to produce rated machine
stator voltage.
3BHS102402E62
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4 Bibliographic references
1. Paul M. Anderson, A. A. Fouad, Power System Control and Stability IEEE Press,
1993
2. Prabha Kundur, Power System Stability and Control, McGraw Hill, Inc, 1993
3BHS102402E62