FPGA IMPLEMENTATION OF A CHAOTIC OSCILLATOR USING RK4 METHOD

Luciana De Micco, Hilda A. Larrondo

Departamentos de Fı́sica y Electrónica

Facultad de Ingenierı́a, UNMdP
Juan B. Justo 4302
email: ldemicco@fi.mdp.edu.ar, larrondo@fi.mdp.edu.ar

ABSTRACT 1. INTRODUCTION
The dual deterministic-stochastic behavior of chaotic
CS have produced a deep change in our vision of nature
systems (CS) makes them extremely interesting in elec-
because of two opposite properties they have: (a) they
tronic engineering as CS may replace noise sources in
are deterministic because their dynamics is governed by
different applications. Consequently it is convenient to
a known mathematical model and (b) they are extremely
have hardware implementations for both, analog and dig-
sensitive to initial conditions, and consequently their long
ital versions. Discrete components, Micro Controllers,
term dynamics is unpredictable for finite precision im-
Digital Signal Processors (DSP) and Field Programmable
plementations, and it is better described by means of
Gate Arrays (FPGAs) are possible choices.
statistical tools. In summary, CS must be included in
For digital realizations the Ordinary Differential Equa-
the class of deterministic systems and also in the class
tions (ODE’s) are replaced by a discrete time system.
of stochastic systems.
Furthermore numerical values are expressed in a numer-
The deterministic-stochastic duality makes CS spe-
ical representation. It is well known that these two dis-
cially interesting for electronic engineering applications,
cretization processes may strongly affect the chaotic be-
since the signals generated by CS can be used as con-
havior of the system.
trolled noise sources; this is a strong motivation to study
In previous contributions we considered the use of
hardware implementations of CS.
the Euler’s algorithm in two different numerical repre-
It is important to remark that any digital realization
sentations: (a) integer arithmetics and (b) single floating
of CS requires both the time and the state variables to
point IEEE-754 standard. For applications that require a
be discrete. Time discretization forces the use of al-
good agreement between the analog chaotic system and
gorithms to replace the ordinary differential equations
its digital counterpart, more involved algorithms and/or
modelling the continuous system. State variables dis-
numerical representations must be used.
cretization is made by a numerical system selection. Dis-
Guided by numerical simulations, in this paper we
cretization of time and finite precision, can completely
propose an improvement replacing the Euler’s algorithm
change the dynamics of the system even destroying the
by the fourth order Runge Kutta algorithm (RK4). In
chaotic behavior [1, 2, 3].
order to diminish the required hardware a method based
Micro controllers, Digital Signal Processors and FPGAs
on blocks’ reusing is proposed. The procedure is exem-
may be used to design digital implementations of CS
plified on a Lorenz CS.
[4, 5, 6, 7, 8, 9, 10]. For simplicity we studied in pre-
The whole design was implemented onto a FPGA
c vious papers FPGA realizations of CS using the Euler
EP 3C120F 7 by Altera� , using only 12 % of its logic
algorithm with both integer arithmetics [11] and float-
elements, 13% of its embedded multipliers and 34 % of
ing point number representation [12]. If one is interested
its memory bits. The smallest Ciclone III device where
in a closer approximation of the continuous chaotic at-
our design fits is the EP 3C40U 484I7.
tractor, more involved algorithms are required. In this
The authors are CONICET researchers. This work have the fi- paper we choose the simplest improvement over the Eu-
nancial support of CONICET and Universidad Nacional de Mar del ler algorithm: the fourth order Runge-Kutta algorithm
Plata.
(RK4).
RK4 is a reasonably simple and robust integration
algorithm and in general it is a good candidate for the

978-1-4244-8848-3/11/$26.00 ©2011 IEEE

185
numerical solution of chaotic differential equations, when behavior as well as multi stability phenomena, such as
combined with an intelligent adaptive step-size routine multiple periods and stagnant dots [20, 21]. It is defined
[13]. by the following set of three coupled ODE’s:
The Lorenz’s system studied in this paper was also
implemented by other authors [14, 15]. In [14] the tool-
dx
box of the Xilinx System Generator is used under MAT- = fx = −δ(x − y) ,
LAB Simulink toolbox to convert the MATLAB Simulink dt
dy
model into the Xilinx System Generator model. Then = fy = Γx − y − xz , (1)
the VHDL code is obtained. One drawback is VHDL dt
automatic code generation tools are non-optimal. The dz
= fz = −bz + xy ,
integration operation was approximated with Euler’s al- dt
gorithm, using adding and delay blocks. The implemen- where fx , fy and fz are the components of the vector
tation proposed in [15] uses RK4 in a 32−bit fixed point →
−
field f and δ, Γ and b are parameters. In this paper
architecture. The application considered is a chaotic ran-
their values are:
dom key for data stream encryption that do not require
an exact reproduction of the continuous chaotic attrac- δ = 16; Γ = 45.92; b = 4; (2)
tor.
As hardware density of digital systems increases float- corresponding to a chaotic behavior. The RK4 discrete
ing point computations are becoming increasingly popu- system for the continuous system given by Eq. 1 is, [22]:
lar, particularly in applications where the variables have
a very large dynamic range, or high computing preci- x(n + 1) = x(n)+
sion is required. This is a reason to study in this paper 1 � (1) �
the implementation in a floating point arithmetics with + kx (n) + 2kx(2) (n) + 2kx(3) (n) + kx(4) (n)
6
the IEEE-754 single precision standard representation.
To reduce the area required on the FPGA, a reusing pro-
cedure of some functional blocks is proposed. y(n + 1) = y(n)+
The implementation presented in this paper was fully 1 � (1) �
developed with Quartus II 7.2� c
development software. ky (n) + 2ky(2) (n) + 2ky(3) (n) + ky(4) (n) , (3)
6
The simulation and physical implementation was made
c
on an Altera� Cyclone III EP 3C120 development kit.
The results correspond to the Lorenz system but the z(n + 1) = z(n)+
same methodology can be used for the hardware imple- 1 � (1) �
mentation of many others Lorenz like CS such as Rössler kz (n) + 2kz(2) (n) + 2kz(3) (n) + kz(4) (n)
6
[16], Chua [17], Chen [18], Lü [19] etc. Results are
compared with those previously obtained for the same where x(n), y(n), and z(n) are the time series that con-
system with Euler’s method and: (a) 16 bits integer arith- (i)
stitutes the output of the project, and the values of k• (n)
metic [11] and, (b) floating point single precision [12]. for i = 1, ..., 4 are:
The work is organized as follows: in section 2, the
Lorenz oscillator implemented in RK4 method is de- kx(1) (n) = h fx [x(n), y(n), z(n)]
tailed. Section 3 is about the architecture of the pro-
posed hardware implementation of the system. In sec-
tion 4 the results are depicted and discussed. Compar-
isons with previous implementations are made by repre- (1) (1)
senting the system in the plane entropy-statistical com- kx (n) ky (n)
kx(2) (n) = h fx [x(n) + , y(n) + ,
plexity C −H, as explained in [12]. Finally, conclusions 2 2
(1)
and remarks for future work are given in 5. kz (n)
z(n) + ]
2
2. THE LORENZ OSCILLATOR
IMPLEMENTED IN THE FOURTH ORDER
(2) (2)
RUNGE−KUTTA METHOD kx (n) ky (n)
kx(3) (n) = h fx [x(n) + , y(n) + ,
2 2
The Lorenz oscillator is a classical example of a continu- (2)
kz (n)
ous dynamical system exhibiting bifurcations and chaotic z(n) + ] (4)
2

186
 (1) (2) (3) (4)
clk 1/(34*4) produces the output 1/6 (k• + 2k• + k• + k• ) sent
1/34 to the second Adder to obtain the new value of x1 . Iden-
x(n)y(n)z(n) tical blocks are used for variables y and z. Once x1 , y1
c0=clk/34
Field c1=c0/4 1/6(k1+2k2+2k3+k4)

k +
function Slope + and z1 are known they are sent to the block Register and
generator f() Step1:k1
generator
the cycle starts again with Step 1.
Blocks k-generator and Field-function of Fig. 1 con-
Step1:0 34 cycles Step2: k2
Step2:k1/2 Step3: k3

stitute the brain of the RK4 solver and are reused as

Step3:k2/2 Step4: k4
Step4:k3 c1
Reg
explained above to reduce the required FPGA area and
k={kx ky kz}
x0 y0 z0
power consumption.
The block Field function requires at least 34 clock
Fig. 1. Datapath. cycles of the main clock (clk ) to finish all the calcula-
tions and give a valid result for f• (see Eq. 1). That
Step1 Step2 Step3 Step4 Step1 Step2 Step3 Step4 … Step1 Step2 Step3 Step4
is the reason c0 = clk /34. Furthermore four cycles
“Field
function” k1 k2 k3 k4 k1 k2 k3 k4 k1 k2 k3 k4 time
of c0 are required to get the new value of the time se-
output
c0 =clk/34 time to compute k
ries. Consequently the overall frequency turns out to be
c1 = c0 /4 = clk /136.
“Slope
generator” Slope0=0
Slope1=
1/6(k1+2k2+2k3+k4) SlopeN The Phase Locking Loop (PLL) was implemented
c
output
c1 =c0/4 with the ALT P LL block from the Altera� library, this
function is fully parameterizable and admits the gener-
x output x0 x1=x0+Slope1 xN=xN-1+SlopeN
ation of up to four simultaneous clock signals. These
time to compute x1 signals must be multiples and / or dividers of the input
clock. In this case we have employed this PLL to gen-
Fig. 2. Time diagram of the RK4 iteration process. erate the clock signals c0 and c1 . The hole system is
enabled by the signal locked, also coming from the PLL.
kx(4) (n) = h fx [x(n) + kx(3) (n), y(n) + ky(3) (n),
4. RESULTS
z(n) + kz(3) (n)]
The timing diagram for the outputs x, y and z as well as
where h is the step size. Similar expressions are ob-
all the clocks (clk = 125 M Hz, c0 � 3.676 M Hz and
tained for y and z.
the overall frequency c1 � 0.9 M Hz) are shown in Fig.
3. This Fig. is provided by the simulation software in
3. PROPOSED ARCHITECTURE the Quartus II� c
environment. Note that the values are
expressed by unsigned integers only in the representa-
A simplified scheme of the hardware implementation is c
tion generated by the Quartus� software, in spite they
shown in Fig. 1 with the corresponding time diagram for
are evaluated correctly as floating point numbers in the
the time series {x} shown in Fig. 2. Here, the four steps
IEEE − 754 standard.
required to complete the RK4 cycle are shown. The
At each rising edge of c1 the current value at the in-
process starts when the initial conditions for the state
put of the Register block is sampled and stored in the
variables {x0 , y0 , z0 } are loaded in the block Register.
latch until the next rising edge of c1 . The block Field
Here Step 1 of the cycle, shown in Fig. 2, starts. These (i)
fuction holds in its outputs the values of kx and after
values are simultaneously sent to the first and second
the transient time due to calculations (about 34 cycles
Adder. The block k- generator is loaded with a zero
(1) of clk ) these values are read by the block Slope gener-
value. The block Field function produces k = k•
ator as can be seen in Fig. 2. The compilation results
given by Eq. 4 and this value is fed back to the block c
(1) in Quartus II� show that the whole design uses 12%
k-generator, that produces the new k• /2 value, in Step of the logic elements of the device, 13% of the 9 bits
2. embedded multipliers and only 34% of the total mem-
(2)
The block Field function produces the value k• , ory bits, see Table 1. The design fits in a Cyclone III
(2)
that is fed back to the block k-generator to produce k• /2. EP 3C40U 484I7 of Altera� c
available in our lab.
This procedure repeats till the four k values are gener- In order to perform the hardware evaluation of the
(1) (4)
ated (each one in each Step) and k• to k• are avail- design on the Development Kit Board, SignalT ap II
able at the input of the block Slope generator. This block Embedded Logic Analyzer was used. This tool provided

187

Fig. 3. Timming diagram of the simulation in Quartus II� environment
Fig. 4. Signal Tap II outputs
c and then it reduces the FPGA memory bits required.
Table 1. Device utilization summary Altera� Cycone
III EP 3C120F 780C.
Total logic elements: 14290 out of 119088
Total memory bits: 1353646 out of 3981312
Embedded Multiplier
9-bit elements: 77 out of 576
c
by Altera� is a system- level debugging tool that cap-
tures and displays the signal behavior in real-time. It
allows one to detect interactions between hardware and
software in the system design. After capturing and sav-
ing the data in a SignalT ap II file they can be analyzed
and viewed in a waveform [23]. The clock signals c0 and
c1 as well as the outputs x, y and z are shown in Fig. 4.
In Figs. 5 and 6 the time series and the attractor
obtained by the hardware implementation are displayed,
using h = 0.005.
It is well known that chaotic systems are very sensi-
tive to initial conditions. Consequently it is not possible
to compare different realizations of the same system by
means of the respective time series. It was shown that
a statistical evaluation of the respective time series is a
better methodology [24, 2, 12]. The systematic statisti-
cal evaluation of different realizations in FPGA is a work
in progress, but preliminary results show that the imple-
mentation in RK4 presented here may be used to pro-
duce chaotic time series with the same statistical prop-
erties than those obtained by numerical integration with
more involved variable step methods, up to h = 0.05.
This value of h represents an important improvement
over our previous realization using the Euler algorithm
that required h ≤ 0.0045 [12]. This 10 times higher
h implies that the number of time intervals required to
cover a given evolution time is reduced in a factor 10
188
c
5. CONCLUSIONS
A method to implement in real time a chaotic dynamical
system onto a FPGA board is introduced. The method
is exemplified with a Lorenz chaotic system but the pro-
posed solution can be used for the hardware implemen-
tation of many others Lorenz like chaotic systems such
as Rössler, Chua, Chen, Lü...etc just by changing the
Field function block. The realization proposed here, with
the reusing procedure leaves free resources in the se-
lected FPGA as it uses 12% of the logic elements of the
device, 13% of the 9 bits embedded multipliers and only
34% of the total memory bits, see Table 1. The design
fits into a smaller Cyclone III device, the EP 3C40U 484I7.
The constraint to use even smaller Cyclone III devices is
the bits of memory requirement.
In view of the free resources it is possible an im-
provement of the proposed design. Our future work will
include the use of a fine and deeper pipelining and par-
allel computation, a variable step algorithm and double
precision representation.
6. ACKNOWLEDGEMENTS
This work have the financial support of Universidad Na-
cional del Mar del Plata and CONICET.
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