192

Area Optimization of CMOS Full Adder Design

Using 3T XOR
Somashekhar Malipatil1 , Vikas Maheshwari2 , and Marepally Bhanu Chandra3
1 Research
Scholar, Department of ECE, Sri Satya Sai University of Technology &
Medical Sciences (SSSUTMS), Sehore(MP), India
2 Department of ECE, Bharat Institute of Engineering & Technology, Hyderabad, India
3 Department of ECE, Koneru Lakshmaiah Education Foundation, Hyderabad, India
1 somashekhar49@gmail.com, 2 maheshwarivikas1982@gmail.com, 3 mbhanu.iiit@gmail.com

Abstract—GDI (Gate Diffusion Input) is a new technique of low
power digital circuit design is proposed. This technique allows
minimization of area and power consumption of digital circuits.
In this design XOR gate is designed using 3 transistors and
CMOS full adder is designed based on two 3T XOR and one
2T Mux. Using 8 transistors the full adder is designed in this
paper and voltage scaling also done by reducing supply voltage.
In this proposed full adder, the power consumption 4.604μW is
achieved and the total area is 144μm2 .
Index Terms—Low Power, Area, Full adder GDI, 3T XOR,
2T MUX, CMOS, 120nm Technology, Logic Gates, Microwind 2,
DSCH 2.
III. CMOS 8T Full Adder Design
The logic diagram of full adder is shown in fig. 1 and it
consists 2 XOR gates and one 2:1 Mux. In this paper the
CMOS XOR gate is designed using 3 transistors based on
GDI technique is shown in fig. 2. When any one of the input
is high, the output will become high. For example in the fig. 2
the inputs a = 1, b = 0 and output will become 1.
The 2T based 2:1 Multiplexer is shown in figure 3. When
select line sel = 0, the output will select ‘a’ and when select

I. Introduction
With Increasing demand for reliable battery life of digital
devices is also demanding for low power consumption digital
devices. It has become the major focussed work for designers
to design such digital devices in order to meet the requirements
of the latest advancements of the technology as these devices
mostly include phones, laptops, sensor nodes [1].
Significant parameters for designing any integrated cir-
cuit are area and power dissipation. Whenever technology
scales from μm to nm, the Vth of transistors is also mini-
mized this leads to sub threshold leakage current to increase
Fig. 1. Simplified Full adder using Mux.
exponentially.

II. Proposed Methodology-GDI

GDI approach allows implementation of a wide range
of complex logic functions using only two transistors. This
method is suitable for design of fast, low power circuits,
using reduced number of transistors. The dynamic power is
expressed as shown in equation 1.

Pd = αcv2 f (1)

Where α = switching activities

C = capacitance
V = supply voltage
f = frequency
In this design, dynamic power is minimized by reducing
switching activity and supply voltage 1.2 V. Fig. 2. 3T XOR using GDI.

978-1-7281-5284-4/20/$31.00 2020
c IEEE
Authorized licensed use limited to: Cornell University Library. Downloaded on September 26,2020 at 10:43:24 UTC from IEEE Xplore. Restrictions apply.

Fig. 3. 2T based 2:1 Mux using GDI.
Fig. 4. 8T Full Adder using GDI.
Fig. 5. 3T XOR 3D process.
line sel = 1, the output will sect ‘b’. The 2:1 Multiplexer is
designed using 2 transistors based on GDI technique is shown
in fig. 3.
The proposed 8 transistor full adder using GDI technique
is shown in fig. 4. In this full adder 2 XOR gates and one
2:1 Mux is used to design full adder. The fig. 4 shows full
Authorized licensed use limited to: Cornell University Library. Downloaded on September 26,2020 at 10:43:24 UTC from IEEE Xplore. Restrictions apply.
193
Fig. 6. 8T Full adder 3D process.
Fig. 7. Simulation of Full adder in DSCH 2.
Fig. 8. Simulation result of 3T XOR in DSCH 2.
adder when all the 3 inputs are high, the outputs sum = 1 and
carry = 1.
The fig. 5 shows the 3T XOR 3D process. To create IC 3D
process, it takes many process steps including initial substrate,
diffusion formation, and oxide growth.
IV. Results
In the figure 9, the BSIM4 model is used to analyze the
Ids versus Vds characteristics. The width of the transistor is
10μm and length is 0.120μm.
Area Analysis: the proposed full adder layout width is 20μm
and length is 7μm. The total area is 144μm2 .
194

TABLE II
Performance Comparison with Existing Work

Parameter Proposed work Mayur Agarwal [3] C.H. Chang [5]

Power 4.604 μW 20.25 μW 24.18 μW
Consumption
Area 144μm2 — —

Fig. 9. Ids Vds Characteristics.



Fig. 12. Power consumption comparison with existed work.

V. Conclusion
In this design XOR gate is designed using 3 transistors
and CMOS full adder is designed based on two 3T XOR and
one 2T Mux. Using 8 transistors the full adder is designed in
this paper and voltage scaling also done by reducing supply
voltage. In this proposed full adder, the power consumption
4.604μW is achieved and the total area is 144μm2 .

Fig. 10. Ids Versus Vgs characteristics. References

[1] Senthil Kumaran Varadharajan and Viswanathan Nallasamy, “Low Power
VLSI Circuits Design Strategies and Methodologies: A Literature
Review”, 2017 IEEE, 978-1-5090-5555-5/17/$31.00 2017c IEEE.
[2] Dr. B.T. Geetha et al., “Design Methodologies and Circuit Optimization
Techniques for Low Power CMOS design”, 2017 IEEE, 978-1-5386-
0814-2/17/$31.00 2017
c IEEE.
[3] Mayur Agarwal, Neha Agarwal, Md. Anis Alam, “A New Design of Low
Power High Speed Hybrid CMOS Full Adder”, 2014 International Con-
ference on Signal Processing and Integrated Networks (SPIN), pp. 448–
452, March 2014.
[4] Akshay Bhaskar et al., “A low power & high speed 10 tran-
sistor full adder using multi threshold technique”, 2016 IEEE,
Doi:10.1109/ICIINFS.2016.8262968.
[5] C.H. Chang, J. Gu, M. Zhang, “A Review of 0.18μ Full Adder Perfor-
mances for Tree Structured Arithmetic Circuits,” IEEE Transactions on
Very Large Scale Intergration Systems, vol. 14, no. 12, December 2006.
[6] A. Parveen and T. T. Selvi, “Power Efficient Design of Adiabatic
Fig. 11. Cgs and Cgd characteristics with respect to Vds. Approach for Low Power VLSI Circuits,” 2019 IEEE, pp. 1–4. doi:
10.1109/ICEES.2019.8719300.
[7] Somashekhar, “Design of a Low Power D-Flip Flop using AVL Tech-
nique,” International Journal of Advanced Research in Computer and
TABLE I Communication Engineering, vol. 4, no. 9, September 2015, DOI
Power Analysis of Proposed Full Adder with Voltage Scaling 10.17148/IJARCCE.2015.4962291.
[8] M. Mittal and A. P. S. Rathod, “Digital circuit optimization
using pass transistor logic architectures”, 2016 IEEE, pp. 1–5.
S.No. Supply Voltage Power Consumption Doi:10.1109/ETCT.2016.7882922.
1 1.8V 10.062μW [9] Malipatil, Somashekhar, “Review and Analysis of Glitch Reduction
2 1.2V 6.488μW for Low Power VLSI Circuits,” International Journal for Research in
3 1.0V 4.604μW Applied Science & Engineering Technology (IJRASET), ISSN: 2321–
9653, 2017.

Authorized licensed use limited to: Cornell University Library. Downloaded on September 26,2020 at 10:43:24 UTC from IEEE Xplore. Restrictions apply.