High Frequency VCO Design

1
 Outline

VCO fundamentals

Low-noise LC VCO topologies

VCO design methodology

Examples of mm-wave VCOs

2
 VCO Fundamentals: oscillator model

Vi Vo
A resonator

resistance
generator
Negative
RL
b
1<GG GL <1
Amplifier with selective (positive) feedback or
Negative resistance single-port in parallel with resonant tank
Transconductor with positive feedback and loaded with
resonant tank

3
 Oscillation condition: linear feedback model

Amplifier with (selective) feedback model Barkhausen's (or

Nyquist's) criterion
A V o s c , 
V osc= Vi
1 − V o s c ,  A V o s c , 

∣ o s c  A 0 ∣1 ; ∣ o s c  A V o s c ∣=1 ; P H A S E [ o s c  A ]=3 6 0 o

The amplitude of the oscillation is stabilized by the

nonlinearity of the transistors in the amplifier

4
 Example: Cross-coupled oscillator

1
A osc =−g m R p ×−g m R p   =1 o s c = g m R P 1
L C
gm g 'm W g 'm
1 g m R P = = =
1 1 1
g o g 'o W  g 'o
Q o s c L Q o s c L W Q o s c L
1
W
g ' m −g ' o Q o s c L
5
 Example: 60 GHz in 65-nm CMOS
Jopt = 0.15 mA/μm,
g'm = 1mS/μm; go= 0.2mS/μm,
L=50 pH, Q =10
Note: In reality Q=2...3 at 60 GHz

1 1
C= 2
= 10 2
=14 1fF
L 2  f osc  5 ×10 6.28 ×6 ×10 
−11

1 1
W> = =6 .6 3 μ m
(g ' m −g ' o )Q ωo s c L 0 .0 0 0 8 ×1 0 ×6 .2 8 ×6 ×1 0 1 0 ×5 ×1 0 −1 1

IDS >= 1mA

6
 Oscillation condition: negative resistance model

●
Negative resistance single-port model

∣R G 0 ∣3 R L o s c  ; R G V o s c R L  o s c =0 ; X G  V o s c , o s c X L o s c =0

∣G G 0 ∣3 G L o s c ; G G V o s c G L o s c =0 ; B G  V o s c , o s c B L o s c =0

●
The amplitude is stabilized by the nonlinearity of the negative
resistance device

7
 Methods to generate negative resistance

L
R<0
L R<0
C
R<0

1 ω2L −T
R≈ − ω R≈
gm T 2
 C
2
1  L 1
R≈ − L
g m  T 1 −2 C g d L  2 C g d C g s 
Adding reactive elements at appropriate transistor terminals (three
topologies above)
Cross-coupled structure with positive feedback

8
Example: 60-GHz VCO in 65-nm CMOS with
inductor between gate and ground

Assume W = 50 µm, gm= 50 mS, Cgs = 30 fF, Cgd =15 fF

Calculate minimum value for Gate-GND inductance

1
L 10 2 −1 5
=1 5 6 .5 1 p H
6 .2 8 ×6 ×1 0  1 5 3 0 ×1 0

L = 0.3 nH => R = -50.77 Ω (but Rs+Rg = 8 Ω)

9
 VCO Fundamentals: resonators
High Q (>1000) but not yet integrated in ICs

Dielectric puck (high R) -add varactor

ferroelectric materials for tunable resonators

Magnetic & widely (octave) tunable:

Ferrite YIG (yittrium-iron-garnet) sphere

MSW (magnetostatic wave) thin film

Low Q (<100) affording integration in ICs

Lumped LC - tunable with varactor C

T-line with varactor loading for tunability

10
 Resonator models
C

L L Cm RP

C RP C L
Lm
RS
Cp
t-line k t-line
RS

LC-tank Quartz crystal Dielectric resonator

R p≈R s Q 2

For inductor: Rp=w1LQ

11
VCO Fundamentals: phase noise definition

Phase noise is a measure of oscillator stability and refers to

short-term random fluctuations in f or f
Phase noise is defined as the single-sideband power at a
frequency offset fm from the carrier frequency fo measured in a
1Hz band compared to the carrier power

12
 Phase noise as noise mixing

Noise mixes with oscillator harmonics

*
〈I n f , I n f  〉
f

1/f noise
fm

fm fm fm

fOSC 2fOSC 3fOSC

f 0 fosc 2fosc 3fosc Freq
G
S V  0 G1
G2
fm
G3

f
fOSC 2fOSC 3fOSC

13
 Phase noise as frequency modulation

The output voltage of the oscillator can be expressed as:

v o t =V o s c c o s [o s c t  t ]
where q(t) represents the random phase fluctuation
Small phase fluctuations can be represented as:

f
resulting in  t = s in m t =p s in m t
fm

v o t =V o sc {cos o sc t cos [p sin m t ]−sin o sc t sin [p sin m t ]}

p
v o t ≈V o s c {
c o s o s c t − {c o s [o s c m t ]−c o s [o s c −m t ] }
2 }
14
 Leeson's linear phase noise model
Sqm(w m)
f c o rn e r
Sqm(w )
qm
Sqout(w )

q out
FkT  f
P AV S

〈 m , m 〉=F k T  f 1 
fm 
+ A=1 w corner wm f m = f − f OSC
Vi Vout
Noise-free
amplifier H(w m)
o u t f m ×H f m m =o u t f m 
H(w )

Bandpass filter wm

1 1
H  jf = h e n c e H  jf m ≈
f OSCf 2 fm QL
1 jQ
f OSC
−
f  1 j
f OSC
2 fm QL
1 j
f OSC f OSC
o u t f m =
m
1 −H f m 
= m
j
2 fm QL
=m 1 −j
2 f m QL  
f OSC
15
 Leeson's phase noise formula
2

P n o is e =〈o u t , o u t 〉=〈m , m 〉 1 

1 V o s c p
2
[  ]
f OSC
2 fm QL

  2 2 2

L (fm)=
P n o is e 2
P AV S
=
1 2
V
2

2 osc
=
 
4
p
=
2
=
FkT  f
rm s

2 Pavs [   ]
1
f osc
2Q L f m
1
f c o rn e r
fm 
QL = resonator loaded Q; Pavs = average signal power
Pnoise = noise power in a single sideband of 1 Hz
fm = frequency offset from fosc
F = transistor (amplifier) noise factor with respect to resonator
impedance @ resonance
fcorner = flicker noise corner frequency
f = noise measurement bandwidth = 1 Hz

16
 Leeson's phase noise formula

Indicates that there can be 4 regions in the L(f)

characteristics:
1/f L L
1/f2
1/f3 1/f3
1/f 3

f0 1/f2 1/f
kTF/Pa v s kTF/Pa v s

Low Q high Q

17
 Phase noise contributors

Resonator Q. Higher is better.

Oscillation amplitude. Higher is better.

Transistor noise. Lower is better.

Amplitude limitation mechanism (linearity). Avoid HBT saturation.

Bias supply, current tail & tuning control noise. (differential control
and topology is better).

Buffer amplifier (load) noise. Loading the tank directly is bad for
noise.

18
 VCO Fundamentals: frequency tuning

Want tunable oscillators:

osc
o s c =0 K V C O V c o n t
ω2 - ω1 = tuning range 2
V2 - V1 = control range
KVCO= VCO gain (sensitivity)


2−1
K VCO 
V2−V1 
Vcont
V1 V2

19
 VCO Fundamentals: specification
Center frequency: fosc
Tuning range: (f2 – f1)/fosc
large to cover process variation
small to reduce phase noise
KVCO increases with center frequency and lower supply
voltage. So does phase noise.
Want constant KVCO over tuning range in PLL design
Tuning linearity (important for PLLs)
Can use linearization techniques

20
 RF VCO Fundamentals: specification

Phase noise (dBc/Hz)

translates in jitter
easier to measure than jitter
Output amplitude/power, Pout
larger is better to reduce noise
trade-off with supply voltage and power
May vary across tuning range (bad)
Power dissipation: PDC

21
 RF VCO Fundamentals: specification

Supply rejection: pushing  o s c

lower is better  V s u p p ly
differential topology helps
Common mode rejection helps
Load mismatch rejection: pulling  o s c
 L
lower is better
Improved by better transistor isolation and/or buffer
amplifier between VCO and load
VCO figures of merit

2 2
f osc 1 f osc P AV S
FoM 1=
 
fm L  f P D C
FoM 2=
 
fm L  f P D C

22
 Outline

VCO fundamentals

Low-noise LC VCO topologies

VCO design methodology

Examples of mm-wave VCOs

23
 LC VCO topologies (invented before 1940)
Selective feedback (L, C, Transformer):
Colpitts (2C + 1L)
Clapp (2C+1LC)
Armstrong (1C + xfmr)
Hartley (1C + 2L)
Negative gm or cross-coupled with tuned amplifier and unity
feedback.

24
 LC VCO topologies: Selective feedback
Y3 Y3

2 2
1 1 gmV13

Y1 Y2 Y1 Y2
3 3

Y 1 Y 3 V1 0

[ ][ ] [ ]
−Y 3 −Y 1
G m −Y 3 Y 2 Y 3 −G m −Y 2 V2 = 0 V1, V2, or V3=0
−G m −Y 1 −Y 2 G m Y 1 Y 2 V 3 0

G m −Y 3
[ −G m −Y 1
−G m −Y 2
G m Y 1 Y 2
=0
] G m Y 3 Y 1 Y 2 Y 1 Y 3 Y 2 Y 3 =0

Gm B1 B1 1 1 1
G0
=− 1 
 
B3
=
B2
  =0
B1 B2 B3
25
 Colpitts topology
Use feedback or negative resistance model
RS is the loss resistance of the inductor

Cgd
In C1 V1
L
VOSC
C2
V1 VOSC RS

R<0

−gm o s c L
R= 2 R S=
 C1 C2 Q
26
 Colpitts topology
Analysis at oscillation condition is carried out using large signal
equivalent model for transistor
I 1 p⋅I B IA S
Gm is the large signal transconductance Gm≝ ≈
V1 V1
V1 is the amplitude of the fundamental voltage across C1
IBIAS is the transistor bias current
p =1..2 depends on current waveform

2
Gm C1 C2 L C1 C 2
2
o s c C 1 C 2
=R S o r G m R P =
C 1 C 2 
C C
1 2
≥4
1
f osc [
=2  L C g d 
] 
C 1 C 2
≈2 
C 1 C 2

2
∣I n∣
1 1
C 1 ≫C  C g s  to a v o id p u s h in g L f m = 2 × 2 × 2
V osc f m C1
C1
2
 
C2
1

27
Waveforms similar to class F-1 PA

28
 LC VCO topologies: Selective feedback

To reduce noise, V1 and V2 should be as large as possible

(limited by transistor breakdown)
VOSC can be larger than the supply voltage but not larger than
the transistor breakdown voltage
V1 depends on inductor (tank) Q and bias current

Gm 1 2 I B IA S Q C1 2 I B IA S Q
=
o s c C 1 C 2  Q V 1≈
o s c C 1 C 2  V o s c =V 1
  1
C2
=
C 2 o s c

2 2 2 2
∣I n∣ 1 1 ∣I n∣ o s c C2 1
L f m = 2 × 2 × 2
= 2 2 2 2
× 2
V osc f m C1 I f 4Q C1 C1
C1
2
 
C2
1
B IA S m

 
C2
1

29
Other selective feedback topologies

Clapp

Armstrong

30
 Differential Colpitts topology

Negative resistance transistors Q1,2

also act as buffer -> low noise.

HBT sized and biased for optimal noise

Emitter degeneration RE for linearity

Operation on 2nd. harmonic of the LC-

varactor tank is possible (push-push)

[L. Dauphinee, M. Copeland, ISCC 1997]

31
SiGe HBT Colpitts topology improvements
(C. Lee et al. CSICS-2004)

Add inductive peaking to improve gain at HF.

Replace current source tails with resistor RB and
capacitor CB to reduce noise at DC and 2fosc
(Winkler, ISSCC-2003, and RFIC 2003)
Replace resistive RE with inductive emitter
degeneration and add LE2 to reduce noise at fosc
and 2fosc respectively (Li et al. JSSC Feb. 2003)

1 1
f o s c a n d f o s c
2  L E1 C va r 2  L E 2 C v a r

Add common base output buffer to improve

isolation to load (Li et al. JSSC Feb. 2003)
Apply control voltage differentially.

32
 LC VCO topologies: Cross-coupled, no tail

Works well with both MOSFETs and HBTs

8 IBIAS (M 1)
Favoured in MOSFET implementations G m≈
π V out
pp

Oscillation condition: (gmRP)2 >1

−G m C gs Cdb
Y o u t=
2
+j ω
2( +
2
+2 C g d )
Oscillation frequency:
1
f osc=
2 π √ L (C +C g s +C d b +4 C g d )
Use feedback or negative conductance model

33
 n-MOS vs. CMOS LC VCOs with tail current
source

n-MOS differential cross- CMOS differential cross-

coupled VCO coupled VCO
Oscillation amplitude VDD Oscillation amplitude VDD/2

IBIAS=IT/2 8 IBIAS (M1)

Gm≈ π
V out
[C. Samori, IEEE Circuits Mag. Nov.2016]

34
Transconductor with tank model

[C. Samori, IEEE Circuits Mag. Nov. 2016]

35
Amplitude limiting with tail current source

[C. Samori, IEEE Circuits Mag. Nov.2016]

36
 MOS cross-coupled VCO topology (cont.)

ISS

Vosc=IBIASRp, (IBIAS sub of bias currents when no tail)

No built-in load buffering. Buffer amplifier loads tank.

Differential tuning control to reduce noise.

Highest frequency: 300 GHz in 65-nm CMOS [B. Razavi JSSC 2011]

In HBT case use de-coupling caps for separately biasing the bases 37
Symmetrical cross-coupled VCO topology

p-MOSFET and n-MOSFET cross-coupled pair to balance the output

signal shape and reduce 1/f noise which is severe in MOSFET
implementations

Swing is rail to rail => no danger of breakdown and reliability issues

Maximum frequency and phase noise is limited by p-MOSFET

performance (not in FinFET).

Poor power supply rejection unless current source is introduced,

preferably at the supply, preferably as resistor.

Best topology in nanoscale CMOS in terms of PN and PDC, FoM

38
 Quadrature VCOs: Cross-coupled
Two, weakly-coupled VCOs.
Output signals are 90o out of phase (in
0 180 theory): inv. with inductive load
Both tanks operate slightly off
resonance hence noisier than single
tank VCOs
Frequency control implemented in
current tails such that amplitude does
not change with oscillation frequency

90 270
Coupling must be at least 25%
8-phase topologies possible (see J.Lee
& Razavi ISSCC 2003)
Phase relationship difficult to guarantee
due to magnetic coupling of tank
inductors!
39
High Q resonator VCO topologies (hybrid ICs)

Reflection line
negative resistance (common
base/gate) transistor
resonator magnetically
coupled to emitter/source t-line
Negative resistance model is
R<0 preferred in analysis

LB
2
1  LB
R≈ −
R<0 gm T

40
High Q resonator VCO topologies (hybrid ICs)

Feedback
DR= dielectric resonator
MSW=magnetostatic
wave
resonator

41
Clapp crystal, DR oscillator topology

OUT
~~ ~~
t-line Z0 DR
C1 -R DR
C1 C1

BIAS
C2 C2
BIAS t-line Z0
C2

Infineon, IEEE BCTM 2008

42
YIG-tuned (YTO) oscillator

M. Van Delden et al., Infineon, IEEE RWS 2019

43
 Outline

VCO fundamentals

Low-noise LC VCO topologies

VCO design methodology

Examples of mm-wave VCOs

44
 Colpitts VCO design methodology (as LNA)

Design philosophy
Maximize oscillation amplitude Vosc on tank at resonance because
it will minimize phase noise.
i.e. set Vosc as the largest possible voltage allowed by the
technology/power supply
Tradeoff:
Low-power (maximum L, lowest bias current)
Low-phase noise (lowest L, high bias current)

Nallatamby et al., IEEE-trans. MTT, 2003

where In is the total noise current of transistor

45
 VCO design methodology: Low power

PDC is known, hence, in addition to VOSC, IBIAS is set.

(1) Bias transistor at JOPT to minimize phase noise:
W = IBIAS/JOPT; AE= IBIAS/JOPT
(2) RPMIN LMIN can now be calculated (cross-coupled)

V OSC R P M IN V OSC
R P M IN = L M IN = =
2 I B IA S Q O S C 2 I B IA S Q O S C

(3) Calculate Ceq 1

Ceq =
2O S C L

Note: Design verified first through small signal simulation of the

negative resistance and tuning range from S-params test bench.
46
 VCO design methodology: Low phase noise
(1) Select L as small as possible.
(2) Once L is selected, Ceq is known and assuming Q determined by
the back-end, Rp is also known.
(3) Since RP and VOSC are known, the minimum value of Gm can be
estimated
2
Gm RP C 1 C 2 
2
= 2 = > G m R P= ≥4
o s c C 1 C 2 Q C1 C2

an initial guess on IBIAS can be made assuming C1=C2= 2Ceq

C1

Gm ≈
2 I B IA S
=
2 I B IA S
 
1
C2
=2
I B IA S
C 1 L 2o s c
V1 V OSC V OSC
(4) Bias at JOPT for minimum phase noise => W, AE
47
 VCO design methodology: Low phase noise (ii)

(5) Select C1 = C'1 + Cgs(be) >> Cgs (be)

C ' 1 C ' g s W C ' 2 C ' s b W 

C e q =C ' g d W 
C ' 1 C ' 2 C ' g s C ' s b W

C ' 1 C b e C ' 2
C e q =C b c 
C ' 1 C ' 2 C b e

(6) Iterate (3) – (5) to account for layout parasitics.

Note: Design verified first through small signal simulation of the

negative resistance and tuning range from S-params test bench.
48
Simulation and design test bench: Colpitts

49
Simulation and design test bench: cross-coupled

50
Colpitts VCO design (continued)

• Choose LS large (AC open)

• Add RSS, CSS and LSS for bias and

noise de-coupling
• VCTRL can be digital (DCO)

51
 Design Example: 80-GHz Colpitts DCO

C =C ' A C C W u n it

C fF
C M IN ≈ C ' AC C ≈1 .5
2 m

C T =2 n −1 C M IN C −C M IN b 0 b 1 2 1 b 2 2 2 ... b n −1 2 n −1 

[M. Khanpour, M.A.Sc. Thesis, Univ. of Toronto, 2008]

52
Design optimization

53
Simulated vs. meas. tuning curve

54
 DCO measurements: PN, pushing

Phase noise: -85 dBc/Hz to -92 dBc/Hz @1MHz Pushing < 100
MHz/V

For VDD=1.1-1.3V
Pushing < LSB=31MHz

55
Cross-coupled VCO – Design

• Choose LTANK

• Bias transistors at optimum noise

current density (0.15-0.2 mA/m)

• Size transistors to provide adequate

negative resistance

• Calculate CVAR from operating

frequency
• Provide buffer to “shelter” tank
• VCTRL can be digital (DCO)
56
 Outline

VCO fundamentals

Low-noise LC VCO topologies

VCO design methodology

Examples of mm-wave VCOs

57
Example: 60/30 GHz CMOS Cross-Coupled
VCOs in 45nm SOI CMOS

60-GHz VCO 30-GHz VCO

2mA-3.6mA/0.65V-1.2V

60-GHz Buffer 60-GHz Doubler

[Shopov et al, IEEE Trans. MTT, Dec. 2017]

58
 Example: 60/30 GHz CMOS Cross-Coupled
VCOs in 45nm SOI CMOS

[Shopov et al, IMS 2017]

59
Comparison of 60GHz 45nm SOI, 22nm FDSOI
and SiGe HBT Cross-coupled VCOs

60
 60-GHz Colpitts-Clapp DCO

PDC= 25.8 mW, Pout = 3dBm

PN @ 1MHz : -110 dBc/Hz
[E. Laskin et al. RFIC 2011]

61
80-GHz 22nm FDSOI Colpitts VCO

VCO: 36mA/0.8V = 29 mW,

Buffer: 22mA/2.4V = 53 mW
Pout = 9-11 dBm with buffer
[A. Zandieh et al. Trans. MTT 2021]

62
110-GHz Armstrong VCO

PDC= 36 mW, Pout = 1dBm

PN @ 1MHz : -104 dBc/Hz
E. Laskin, Ph.D. Thesis 2010
63
 120-GHz Colpitts VCO

PDC= 76 mW, Pout = 6dBm

PN @ 1MHz : -111 dBc/Hz
E. Laskin, Ph.D. Thesis 2010
250-GHz recently demo-ed
64
0.2V Folded Class F 4GHz VCO in 22nm FDSOI

[O. El-Assar and G.M. Rebeiz, ISSCC 2019]

65
0.2V Folded Class-F 4GHz VCO in 22nm FDSOI

[O. El-Assar and G.M. Rebeiz, ISSCC 2019]

66
0.2V Folded Class F 4GHz VCO in 22nm FDSOI

[O. El-Assar and G.M. Rebeiz, ISSCC 2019]

67
0.2V Folded Class F 4GHz VCO in 22nm FDSOI

[O. El-Assar and G.M. Rebeiz, ISSCC 2019]

68
0.2V Folded Class-F 4GHz VCO in 22nm FDSOI

[O. El-Assar and G.M. Rebeiz, ISSCC 2019]

69
 Summary

VCOs are critical blocks in both radio and optical fiber systems

VCO design methodology involves a combination of PA and LNA

design techniques

Maximum allowed voltage in a technology is critical in VCOs

VCOs can be algorithmically scaled in frequency and ported across

technology nodes

Colpitts topology exhibits lower noise and higher output power than

cross-coupled topology at mm-wave frequencies

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