NAME- NAVEEN

CHANDRA Mahi
ENR NO.-191B167 Tyagi
BASIC LOGIC GATES & COMBINATIONS
Experiment No. 1

Aim: Familiarization and Verification of logic functions of the TTL ICs.

Let inputs to a gate are A & B and Y is the output.
This experiment serves as an introduction to the ‘Bread-Boards’ used in the laboratory and to
understand the function of various TTL ICs.
Activity-1. Verification of Logic AND Gate (IC 7408)
Vcc
14 13 12 11 10 9 8

A
B Y

7408
Logic Diagram of AND gate

GND
Pin-out Diagram of IC 7408

Observations
(i) What is the number of AND gates in the IC 7408 = 4
(ii) Verification of Truth-Table
Inputs Outputs
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

(iii) Expression: Y=A.B

Activity-2. Verification of Logic OR Gate (IC 7432)

Vcc
14 12 11 10

A 7432
Y
B

GND
Logic Diagram of OR gate Pin-out Diagram of IC7432
 Observations
(i) What is the number of OR gates in the IC 7432 = 4
(ii) Verify of Truth-Table
Inputs Outputs
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

(iii) Expression: (A+B)

Activity-3. Verification of Logic NOT Gate (IC 7404)

Vcc
14 13 12 11 10 9 8

o o o

7404

a
y o o o

1 2 3 4 5 6 7
GND
Logic Diagram of NOT gate Pin-out Diagram of IC 7404

Observations
(i) What is the number of NOT gates in the IC 7404 = 6
(ii) Verification of Truth-Table
Inputs Outputs
a y
0 1
1 0

(iii) Expression: (y=ā)

Activity-4. Verification of Logic NAND Gate (IC 7400)

Vcc
14 13 12 11 10 9 8

A o o
Y
B

7400
Logic Diagram of NAND gate o o

1 2 3 4 5 6 7
GND
Pin-out Diagram of IC 7400

Observations
(i) What is the number of NOT gates in the IC 7404 = 4
 (ii) Verification of Truth-Table
Inputs Outputs
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

(iii) Expression: (y=A.B)

Activity-5. Verification of Logic NOR Gate (IC 7402)

o 14 13 12 11 10 9 8
A
o Y o o
B

7402

Logic Diagram of NOR gate o o

5 6

Pin-out Diagram of IC 7402

GND

Observations
(i) What is the number of NOR gates in the IC 7402 = 4
(ii) Verification of Truth-Table
Inputs Outputs
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

(iii) Expression: Y=(A+B)

Activity-6. Verification of Logic XOR Gate (IC 7486)

Vcc
14 13 12 11 10 9 8

A
Y
B
7486

Logic Diagram of XOR gate

5 6
GND
Pin-out Diagram of IC 7486

Observations
(i) What is the number of XOR gates in the IC 7486 = 4
(ii)Verification of Truth-Table
Inputs Outputs
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

(iii) Expression: (Y=A.B + A.B)

NAME-NAVEEN
CHANDRA
ENR NO.-191B167
COMBINATIONAL CIRCUITS

Experiment No. 2

Aim: Implementation of combinational circuits using MSI Logic.

Construct and identify the function performed by the ‘Block Diagram’ shown below.
Activity-1. Block Diagram-1
Q
NOT S
A AND

B OR U
AND
NOT AND Y
R T
C

Observations
(i) When C is at Logic ‘0’
Inputs Intermediate Outputs Outputs
A B C Q R S T U Y
0 0 0 1 1 0 0 0 0
0 1 0 1 0 1 0 1 0
1 0 0 0 1 0 1 1 0
1 1 0 0 0 0 0 0 0
(ii) When C is a Logic ‘1’
Inputs Intermediate Outputs Outputs
A B C Q R S T U Y
0 0 1 1 1 0 0 0 0
0 1 1 1 0 1 0 1 1
1 0 1 0 1 0 1 1 1
1 1 1 0 0 0 0 0 0

(iii) Name of operation (when c=1): XOR

Activity-2. Block Diagram-2

A Q Y
AND OR
B
U
AND

NOT R OR V

NOT AND T
S
 Department of Electronics and Communication Engineering

Observations
Inputs Intermediate Outputs Outputs
A B Q R S T U V Y
0 0 0 1 1 1 0 1 1
0 1 0 1 0 0 1 1 1
1 0 0 0 1 0 0 0 0
1 1 1 0 0 0 0 0 1

Name of operation: OR or XOR Gate

Activity-3. Block Diagram-3

A R
NOR
NOR NOR Y
Q
NOR
S
Observations B

Inputs Intermediate Outputs Outputs

A B Q R S Y
0 0 1 0 0 1
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

(i) Name of operation: NOR Gate

(ii) Suggest modification of circuit to get ‘Logic XOR’ function.

Jaypee University of Engineering & Technology, Guna (M.P.)

Department of Electronics and Communication Engineering

NAME-NAVEEN
CHANDRA
ENR NO.-191B167

ADDERS AND SUBTRACTORS

Experiment No. 03

Aim: Implementation of Binary Adders and Subtractors.

In this experiment you will construct and test various adders and subtractors circuits.

Half Adders: A half adder performs the arithmetic addition of two binary digits. It has two inputs (Augend
& Addend) and two outputs (Sum & Carry). The two inputs are the two 1-bit numbers X and Y, and the two
outputs are the sum(S) and carry (C).

Logic Symbol
X S
Inputs H.A. Outputs
Y C

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Department of Electronics and Communication Engineering

Full-Adders: A full-adder is a combinational circuit that performs the arithmetic sum of three input bits
namely Augend-bit(X), addend-bit(Y), and carry-bit from the lower significant position(Z).

Logic Symbol X S
Y F.A.
Z C

Half-Subtractor: The half-subtractor is and combinational circuit which is used to perform the subtraction
operation of two bits. It has two inputs, X(minuend) and Y(subtrahend) and two outputs D(difference) and
B(borrow).

Logic symbol

X D
H.S.
Y B

Full-Subtractor: And full subtractor is and combinational circuit that performs the subtraction operation of
three bits, namely, X (minuend), Y(subtrahend), and Z(borrow from the previous stage) and produces two
outputs D(difference) and B(borrow).

Logic Symbol

X D
Y F.S.
Z B
Activity.1. Half-Adder
Design, construct and test a half-adder circuit using one XOR gate and one AND gate, only.

X
Y

Design C

Observations
Truth-Table
Inputs Outputs
X Y S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Write: The switching expressions for Sum (S) =XY’+X’Y

and for Carry(C) = X.Y

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Department of Electronics and Communication Engineering

Exercise-1. Design, construct and test and half-adder circuit using five NAND gates, only and verify the
truth-table, you made above.

Activity.2. Full-Adder
Design, construct and test a full-adder circuit using two half-adders and one OR gate only.
Design

X X1 Σ1 X2 Σ2 S
HA1 HA2
Y
C

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 Department of Electronics and Communication Engineering

Observations
Truth-Table:
Inputs Outputs
X Y Z S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Write: The switching expressions for Sum (S) = X’Y’Z+X’YZ’+XYZ

and for Carry(C) = XY+YZ+ZX

Activity.3. Half-Subtractor
Design, construct and test and half-subtractor circuit using one XOR gate, one AND gate, and one NOT gate
only.
X
D
Y
o B
Observations
Truth-Table
Inputs Outputs
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Write: The switching expressions for Difference(D) =A XOR B

and for Borrow (B) = A’.B

Exercise-2.Design, construct and test half-subtractor circuit using five NAND gates, only and verify thetruth-table,
you made above.

Jaypee University of Engineering & Technology, Guna (M.P.)

 Department of Electronics and Communication Engineering

Activity.4. Full-Subtractor

Design, construct and test a full- subtractor circuit using two half- subtractor and one OR gate only.
Design

XY X1 D1 X2 D2 D
HS1 HS2
Y1 B2 Y2 B2
Y2 B
Z

Observations

Truth-Table:
Inputs Outputs
X Y Z D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Write: The switching expressions for Difference(D) =XY’Z’+X’Y’Z+XYZ+X’YZ’

and for Borrow (B) = X’Z+X’Y+YZ
Activity.5. Parallel-Adder

IC type 7483 is and ‘4-Bit Binary Parallel Adder’. Its internal construction is shown below:
A2 B2 A0 B0
A3 B3 A1 B1

Cin
Cout
C4 C3 C2
FA C1 C1 FA C0

FA C3
FA C2

S2
S3 S1 S0

Jaypee University of Engineering & Technology, Guna (M.P.)

Department of Electronics and Communication Engineering

16 Carry Output
B4 Vcc C4 14

1 A4 S4 15 Data output

4 B3
Pin-out Diagram
A3 S3 Data output

7 B2
IC7483
8 A2 S2 6
Data output
11 B1

10 A1 S1 Data output
13 C0 GND
12 GND

Jaypee University of Engineering & Technology, Guna (M.P.)

Department of Electronics and Communication Engineering

The two four-bit binary numbers are A1, A2, A3, A4, and B1, B2, B3, B4. The four-bit sum is obtained from
S1, S2, S3, S4. Here, C0 is the input carry and C4 is the output carry.

Observations
Table.1. When A(A4A3A2A1) = 1001 and C0=0
Inputs Outputs
B4 B3 B2 B1 C4 S4 S3 S2 S1
0 0 0 0 0 1 0 0 1
0 0 0 1 0 1 0 1 0
0 0 1 0 0 1 0 1 1
0 0 1 1 0 1 1 0 0
0 1 0 0 0 1 1 0 1
0 1 0 1 0 1 1 1 0
0 1 1 0 0 1 1 1 1
0 1 1 1 1 0 0 0 0
1 0 0 0 1 0 0 0 1
1 0 0 1 1 0 0 1 0
1 0 1 0 1 0 0 1 1
1 0 1 1 1 0 1 0 0
1 1 0 0 1 0 1 0 1
1 1 0 1 1 0 1 1 0
1 1 1 0 1 0 1 1 1
1 1 1 1 0 1 0 0 0

Table.2. When A(A4A3A2A1) = 1001 and C0=1

Inputs Outputs
B4 B3 B2 B1 C4 S4 S3 S2 S1
0 0 0 0 0 1 0 1 0
0 0 0 1 0 1 0 1 1
0 0 1 0 0 1 1 0 0
0 0 1 1 0 1 1 0 1
0 1 0 0 0 1 1 1 0
0 1 0 1 0 1 1 1 1
0 1 1 0 1 0 0 0 0
0 1 1 1 0 1 0 0 1
1 0 0 0 1 0 0 1 0
1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 0
1 0 1 1 1 0 1 0 1
1 1 0 0 1 0 1 1 0
1 1 0 1 1 0 1 1 1
1 1 1 0 1 1 0 0 0
1 1 1 1 1 1 0 0 1

Jaypee University of Engineering & Technology, Guna (M.P.)

 Department of Electronics and Communication Engineering

Write the output:

1. When A=1010 and B=1110.
For C0=0, S= 0011 & For C0=1, S= 1011
2. When A=1100 and B=1010
For C0=0, S= 0001 & For C0=1, S= 1001
3. When A=1011 and B=1111.
For C0=0, S= 0011 & For C0=1, S= 1011
4. When A=0011 and B=1100.
For C0=0, S= 1111 & For C0=1, S= 0000

Jaypee University of Engineering & Technology, Guna (M.P.)

 Department of Electronics and Communication Engineering

NAME-NAVEEN
CHANDRA
ENR NO.-191B167

K-MAP SIMPLIFICATION OF BOOLEAN FUNCTIONS

Experiment No. 04

This experiment demonstrates the relationship between a ‘Boolean Functions’ and their
corresponding ‘Logic Diagrams’. The Boolean functions are simplified using the ‘Karnaugh Map
Method’.

Activity-1. Logic Diagram

For three input variables, show that for each of the right possible input combinations, the two circuits
have the identical outputs. This part of the experiment starts with a given logic diagram from which we
proceed to apply simplification procedure to reduce the number of gates and possibly less hardware, i.e., less
number of TTL ICs.

y Y

Fig. Logic diagram

The above logic diagram requires two ICs, IC7400 and IC 7410. Note that the inverters for x, y, and z are
obtained from the remaining three gates in IC7400. If the inverter were taken from an IC7404, the circuit
would have required three ICs 7400, 7410, and 7404, instead of two ICs 7400 and 7410. It should be
avoided.
Procedure
Step1. Assign pin numbers to all inputs and outputs of the gates and connect the circuit with x, y, and z as
inputs going to three switches and the output F to an indicator lamp.
Step2. Construct and test the circuit by obtaining its truth-table.
Step.3. Obtain the Boolean Function of the above circuit and simplify it using the K-map.
F(x,y,z) = XY’+YZ

0 0 1 0

1 1 1 0

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 Department of Electronics and Communication Engineering

The simplified ‘Boolean Expression’ is, F(x,y,z)=XY’+YZ

Observations

Truth Table

Inputs Outputs
X Y Z Original Simplified
output output
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 0 0
1 1 1 1 1

Step.4. Construct the circuit using simplified ‘Boolean Expression’ without disconnecting the original
circuit.
Step.5. Test both the circuits by applying identical inputs to both the circuits simultaneously and observe the
separate outputs.
Step.6. Observe the 4th and 5th columns of the ‘Truth-Table’ you made, write your comments.

Activity-2. Boolean Function

Given the ‘Boolean Function’ in ‘Sum of Minterms’ form,

F1 (A, B, C, D) = m(0,1,4,5,8,9,10,12,13) and
F2 (A, B, C, D) = m(3,5,7,8,10,11,13,15)

Procedure

Step.1. Simplify the two functions by means of K-map.

Hence, F1=………c’+ab’d’…………………… F2=……bd+cd+ab’d’………………………

Step.2. Obtain a composite logic diagram with four inputs, A, B, C, and D, and two outputs F1 and F2. Implement the
two functions together with identical inputs using a minimum number of NAND gate ICs. Note: Don’t duplicate the same
gate if the corresponding term is needed for both functions. Use any extra gates in existing ICs for inverters when
possible.
Logic Diagram for

Step.3. Construct the circuit and take observations.

Jaypee University of Engineering & Technology, Guna (M.P.)

 Department of Electronics and Communication Engineering

Observations
Truth-Table: For Boolean Function F1
Inputs Outputs Given
Minterm
A B C D F1
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 0
Truth-Table: For Boolean Function F2
Inputs Outputs Given
Minterm
A B C D F2
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0

Jaypee University of Engineering & Technology, Guna (M.P.)

Department of Electronics and Communication Engineering

1 1 1 1 1

Step.4. The ‘Truth-Tables’ for F1 and F2 is obtained from the circuit you designed above should
conform with the minterms given.
Write: whether YES/NO. …………

Activity-3. Complement Function

Step.1. Plot the following Boolean function in the K-Map,
F=A’D+BD+B’C+AB’D

Step.2. Combine 1’s in the map to obtain the simplified function for F in ‘Sum of Product’ form.
F=………………D+B’C…………….

Step.3. Combine 0’s in the map to obtain the simplified function for F’ in ‘Product of Sum’ form.
F’=………………D’B+D’C’………………………………………

Step.4. Implement both the functions F and F’ using only NAND gates. Connect the two circuits to the same input
switches, but to separate output indicator lamps.

Step.5. Take observations to obtain the truth-table.

Observations

Truth-Table: For Boolean Function F

Input Outputs

A B C D F
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Jaypee University of Engineering & Technology, Guna (M.P.)

Department of Electronics and Communication Engineering

Truth-Table: For Boolean Function F’

Inputs Outputs

A B C D F’
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Step.7. By observing the truth-tables you made above , show that the functions are complement of each other. Write
your comments,

Jaypee University of Engineering & Technology, Guna (M.P.)

Department of Electronics and Communication Engineering
NAME-
NAVEEN
CHANDRA Code Converters
ENR. NO. -191B167 (Binary to Gray & Gray to Binary)

Experiment No. 05

Aim: Design a combinational circuit with four inputs and four outputs that converts
a four bit ‘Gray Code’ in to the equivalent four bit ‘Binary Number’. Implement the
circuit with XOR gates, only. Connect the circuit to four switches and four indicator
lamps, and test it for proper operation.
The conversion from one binary code to another is common in digital systems. In this
experiment, you will design and construct ‘Combinational Circuit Converters’.

Binary Numbers: The binary number system is a ‘Base-2 System’. It consists of only two
digits, e.g., 0 & 1. The position of 0 and 1 indicates the weight within the number. The
weight of each successively higher position to the left is an increasing power of two.
Gray Code:This non-weighted code belongs to a class of codes called ‘Minimum-Change
Code’ in which only one bit in the code group changes when moving from one step to the
next.

Activity-1. Binary to Gray Code Converter

The block diagram of a 4-bit binary-to-gray code converter is shown in fig. below.
It has four bit-binary inputs B(B3B2B1B0) and four-bit gray code outputs G(G3G2G1G0).

B G

4-Bit B G 4-Bit
Binary Inputs (Binary-to-Gray Code Converter) Gray-Code
B G
Outputs
B G

Fig. Block diagram of 4-bit binary-to-gray code converter

Design: To design and Binary-to-Gray code converter, follow the steps given below.

Step.1. Truth-Table

Step.2. Logical Expressions

From the truth-table, write the logical expressions for the gray code outputs.
G3=m ……… (8,…
9,…
10… ,1…
1,…
12…,1…3,…
14…,1…5)…….

G2=m ………
(4,…
5,…
6,…
7,… …,1…
8,9 0… …) ………….
,11

G1=m ………
(2,…
3,…
4,…
5,…
10…
,1…
1,…
12…
,1…
3)……….
(1,…
G0=m ……… 2,…
5,…
6,9,1
……0…,1…
3,1
…4…
) ……….

Jaypee Institute of Engineering &

Department of Electronics and Communication Engineering

Truth-Table
Binary Inputs Gray Code Outputs
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Step.3. Simplification of Logical Expressions

Simplify the logical expressions, using K-Map.

K-Map for G3 K-Map for G2

Hence, G3= ……B…

3……………….. Hence, G2= ……B…
3…⊕…B…
2 ………..

K-Map for G1 K-Map for G0

Hence, G1= ……B…

2⊕ B1…………..
…… Hence, G0= ……B…
1⊕ B0…………..
……

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Department of Electronics and Communication Engineering

Step.4. Logic Diagram

Implement the logical expressions you find (in step3) after simplifying the K-maps, using
only three XOR gates. Verify the truth-table for binary-to-gray code converter, you made in
step.1.
LSB LSB
Bo Go
⊕

B1 G1

B2 G2

G3
B3 MSB
MSB

Note: Do not disconnect this circuitry you implemented in the bread-board.

Write: How many ICs of XOR gate, you have used to implement this code
converter. ……
3 ….

Activity-2: Gray Code-to-Binary Converter

The block diagram of and 4-bit gray code-to-binary converter is shown below. It has four
bit-gray code inputs G(G3G2G1G0) and four-bit binary outputs B(B3B2B1B0).

G3 B3

G2 B2
4-Bit (Gray Code -to- Binary Converter) 4-Bit
Gray Code Inputs G1 B1 Binary
Outputs
G0 B0

Fig. Block diagram of 4-bit gray code-to-binary converter

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Department of Electronics and Communication Engineering

Design: To design a Gray code-to-Binary converter, follow the steps given below.
Step.1. Truth-Table
Gray Code Inputs Binary Outputs
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Step.2. Logical Expressions

From the truth-table, write the logical expressions for the binary outputs.
B3=m ……… (8…
,9…,1…
0,1…1…
,1… …3…
2,1 ,1…4,…
15… ) ….

(4…
B2=m ……… ,5…
,6…
,7,…
8,…
9,…
10…
,1…
1)………….

B1=m ………
(2…
,3…
,4…
,5,…
8,…
9,…
14…
,1…
5)………….

B0=m ………
(1…
,2…
,4…
,8,…
11…,1…
3,…
14…) ………….

Step.3. Simplification
of Logical Expressions
Using K-Map, simplify the above logical expressions.

K-Map for B3 K-Map for B2

Hence, B3= ………

G…3 …………….. Hence, B2= ………
G3…⊕
…G…
2………..

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Department of Electronics and Communication Engineering
K-Map for B1 K-Map for B0

G…
Hence, B1= ……… …G
1⊕ ⊕…
…2… G…
3 .. Hence, B0= …G ⊕…G…
…1… 2⊕…G ⊕…
…3… G.4.

Step.4. Logic Diagram

Implement the logical expressions you find (in step3) after simplifying the K-maps, using
only three XOR gates. Verify the truth-table for gray code-to-binary converter, you made in
step.1.
LSB
LSB
Go Bo

G1 B1

G2 B2

B3
G3
MSB
MSB

Note: Do not disconnect the circuitry you implemented in the bread-board.

Write: How3many ICs of XOR gate, you have used to implement this code
converter. ……….

Jaypee Institute of Engineering &

Department of Electronics and Communication Engineering

Activity-3 Verification of Code Converter

Procedure
Follow the steps given below.
Step.1. Short, corresponding G outputs and G inputs of the two circuitries, as shown in the
fig. below.

B0 B0

B1 Binary-to-Gray Gray Code-to- B1

Code Converter Binary
Converter B2
B2
B3 B3

Step.2. Apply, 4-bit binary input B(B3B2B1B0) to the Binary-to-Gray Code converter.
Step.3. Observe, the output displayed at the output of the Gray-to-Binary converter, whether
they both are same or not. If not, recheck or redesign (if necessary) the circuitry/circuitries.

Give Comments

T… …o…
he ut…pu… ts… sa…
is… m…e…as… in…
pu…
t b…ec…a…
us…eb…in…ar……e…
yg ts … nv…
co… er… …t…
ted o g…
ra…
y… de……
co…
…
an…
d…the. n to binary
…………………………………………………………………………………………
……….
T… …c…
he irc…ui…
t is…w…or…
ki…
ng…co…rr…
ec…
tly…fo… …
rall… …u…
inp ts ………………………………………
……….
…………………………………………………………………………………………
……….

Jaypee Institute of Engineering &

 NAME-NAVEEN
CHANDRA
Department of Electronics and Communication Engineering
ENR-191B167

Experiment No. 06 MULTIPLEXERS

Aim: Implementation of Multiplexers using gates and TTL ICs

Multiplexers: The term ‘multiplexer’ means “many in to one”. Multiplexing is the process of transmitting a
large number of information over a single line. The multiplexer (Data-Selector) has several Data-Input Lines
and a single Output line. The selection of a particular input line is controlled by a set of selection lines. The
block diagram of a multiplexer (MUX) with ‘n’ (Dn, Dn-1, …….., D1, D0) Input Lines, ‘m’ (Sm, Sm-1,….., S1,
S0) Select Lines, and one Output Line ‘Y’ is shown below.

D0
D1

‘n’ Data Input n-to-1

MUX Y Single Output
Signals
Signals

Dn-1
Dn

Sm Sm-1 S1 S0

‘m’ Select Input Signals

Fig.1. Block Diagram of n-to-1 MUX.

Activity 1: 2-to-1 Multiplexer

A 2-to-1 MUX ha two data input lines, one select line, and one output line. Its logic symbol is shown in
Fig.2, below.

D0

2-to-1
Data Inputs Y Data Output
MUX
D1
S

Fig.2. Block Diagram of 2-to-1 MUX

Select Input
Department of Electronics and Communication Engineering

Logic Diagram: S

D0

Y = D0S + D1S
D1

Fig.3. Logic Diagram of 2-to-1 MUX

Procedure
Step.1. Construct the circuit shown in the Fig.3.
Step.2. Apply the Data Inputs (D0 & D1) and Select Input (S) signal and record the Outputs.

Observations: Truth-Table
Data Select Data inputs Output Comment on Output
Inputs (Write D1 / D0)
S D1 D0 Y
0 0 0 0 Y=D0
0 0 1 1 Y=D0
0 1 0 0 Y=D0
0 1 1 1 Y=D0
1 0 0 0 Y=D1
1 0 1 0 Y=D1
1 1 0 1 Y=D1
1 1 1 1 Y=D1

Activity 2. Implementation of 2-to-1 line MUX with Enable / Disable input

Connect an extra Enable signal ‘E’ to the 2-to-1 MUX, as shown in Fig.4.
ES

D0

Y = (D0S + D1S)E
D1

Fig.4.
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Observation
Truth-Table
Enable Select Data inputs Output Comment on
Input Inputs Output
E’ S D1 D0 Y (Write D1 / D0)
1 0 0 0 0 Y=D0
1 0 0 1 1 Y=D0
1 0 1 0 0 Y=D0
1 0 1 1 1 Y=D0
1 1 0 0 0 Y=D1
1 1 0 1 0 Y=D1
1 1 1 0 1 Y=D1
1 1 1 1 1 Y=D1
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
Write:
1. When Enable Input is HIGH, the Output of the MUX is…En.…
ab…le..d.(Enabled / Disabled).

2. When Enable Input is LOW, the Output of the MUX is …

Di…
sa…
bl…
ed.. (Enabled/Disabled).

Activity 3. 2-to-1 MUX using IC 74157

The Logic Symbol of the IC 74157 (Quad 2-Input Multiplexer) is shown in Fig.5. below.
E’ (Enable Input)
15

Da0 2 MUX
3 (1)
Da1 4 Ya
Db0 5
MUX
Db1 6 7 Yb
(2)

Data-Inputs 14 IC 74157
MUX
12 Yc Data-Output
(3)
13
Dc0
11
MUX
Dc1 10 (4) 9

Dd0
Dd1 Vcc= PIN 16 1 Yd
GND=PIN 8
S (Select Input)

Fig.5.
Department of Electronics and Communication Engineering

Procedure
Step.1. Choose one multiplier (say MUX1) out of the four multipliers, as shown in the Fig.5.
Step.2. Make the proper connections of the Data Inputs, Enable Input, Select Input, and Output.
Step.3. Apply the Enable Signal and the Select Signal to the MUX and take observations.
Observations: Truth-Table
Enable Select Data Inputs Output Comment on
Input Input Outputs Ya
E’ S Da0 Da1 Ya (Da0 / Da1)
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

Activity4..Implementation of 4-to-1 Multiplexer Using IC 74153

The Logic Symbol for the IC 74153 (Dual 4-to-1 Multiplexer) is shown in Fig.8, below.

Da0 6
Da1 5 MUX(1)
7 Ya
Da2 4
Da3 3
E a’ 1
Da4 10 74153
Da5 11 MUX(2)
Da6 12 Yb
9
Da7 13
Eb ’ 2

Vcc= PIN 16
Fig.8. 2S
GND=PIN 8 1 S14
0
Department of Electronics and Communication Engineering

Procedure
Step.1. Choose either MUX1 or MUX2 to perform the experiment.
Step.2. Make the proper connections of the Data Inputs, Enable input, Select Input, and Output.
Step.3. Apply the Enable signal and Select Signal to the MUX.
Step.4. Take observations.
Observations: Truth-Table
Enable Select input Data Inputs Output Comment on
Acti
Input Outputs Ya
vity-
E’ S1 S0 Da0 Da1 Da2 Da3 Ya (Da0/Da1/Da2/Da3) 5.
1 X X X X X X 0 Don’t Care Impl
0 0 0 0 0 0 D 0 D0 eme
0 0 1 0 0 D 0 0 D1 ntati
0 1 0 0 D 0 0 0 D2 on
0 1 1 D 0 0 0 0 D3 of 8-

to-1 line of MUX using Dual 4-to-1 line MUX

Higher order (more number of inputs) multiplexers can be implemented using lower order (lesser number of
inputs) multiplexers. For example,
A 4-to-1 MUX can be implemented using two 2-to-1 MUX,
An 8-to-1 MUX can be implemented using four 4-to-1 or two 2-to-1 MUX,
A 16-to-1 MUX can be implemented using eight 2-to-1 or four 4-to-1 or two 8-to-1 MUX.
In this experiment we will consider the design of 8-to-1 MUX using two 4-to-1 MUX.

Da0

Da1

Da2
MUX1
Da3

S2

Y
Da4
Da5

Da6
MUX2
Da7

S1
Fig.9.
S0
Department of Electronics and Communication Engineering

Procedure
To select one of the 8 inputs, three select lines (S2, S1, S0) are required. Among the three select lines, the
Least Significant two select lines (S1, S0) are connected with the two select inputs of the multiplexers. The
Most Significant select line (S2) is directly connected to the Enable input of the MUX1 while the same is
connected to the Enable input of the MUX2, see Fig.8. Therefore,
1. When S2 = 0, MUX1 is selected as MUX2 is disabled and the data inputs D0 to D3 are multiplexed to the
output Y.
2. When S2 = 1, MUX2 is selected as MUX1 is disabled and the data inputs D4 to D7 are multiplexed to the
output Y.
Also, note that the outputs of the MUX1 and MUX2 are ORed using an OR gate to generate output Y.

Observations: Truth-Table
Enable Select Input Data Inputs Output Comments on
Input Outputs
E’ S2 S1 S0 Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Y

1 X X X X X X X X X X X 0 Don’t
Care
0 0 0 0 D 0 0 0 0 0 0 0 D D0
0 0 0 1 0 D 0 0 0 0 0 0 D D1
0 0 1 0 0 0 D 0 0 0 0 0 D D2
0 0 1 1 0 0 0 D 0 0 0 0 D D3
0 1 0 0 0 0 0 0 D 0 0 0 D D4
0 1 0 1 0 0 0 0 0 D 0 0 D D5
0 1 1 0 0 0 0 0 0 0 D 0 D D6
0 1 1 1 0 0 0 0 0 0 0 D D D7
Department of Electronics and Communication Engineering
NAME-NAVEEN
CHANDRA
ENR. NO.-191B167

Experiment No. 07 FLIP-FLOPS

_

Aim:To investigate the operation of various flip-flops, SR, JK, D and T using gates and flip-flop
ICs.
A Flip-Flop is a Bistable-Multivibrator, which is capable of storing one bit of information. It has two
outputs, one for normal value and one for the complement value. The input to the flip-flop can be fed
in a number of ways and this fact give rise to different types of flip-flop. There are two
characteristics shared by all flip-flops,
1. If input to the flip-flop causes it to go to ‘1’ state, it will remain there until some signal causes it
to go to ‘0’ state and vice-versa, i.e., a FF has two stable states.
2. The flip-flop has two output signals, one of which is the complement of the other.

In this experiment you will construct, test and investigate the operation of various flip-flop circuits;

RS, D, JK, T, and Master-Slave flip-flops.

Activity-1. SR Latch

The SR Latch is a basic flip-flop made with two cross-coupled NAND gates. It has two inputs
S(SET) and R(RESET), and it has two outputs Q and Q’.
Circuit Diagram:
Observations: Truth-Table
S Inputs Outputs Comments
Q S Qt+1
R Q’t+1
0 Qt
Same as before
0 Q't
0 0
Q’ Q=0 for reset
R 1 1
1 1
Q=1 for set
0 0
1 0 Forbbiden/ambiguous/
not used
1 0

Procedure:
Step.1. Construct the basic FF circuit and connect the two input switches and the two outputs to the
indicator lamps.
Step.2. Set the two switches to LOGIC-1, then momentarily turn each switch separately to the
LOGIC-0 position and back to the 1.
Step.3. Obtain the Truth-Table of the circuit.
Department of Electronics and Communication Engineering

Activity-2.Clocked RS Flip-Flop
Observations: Truth-Table
Inputs Outputs Comments
CLK S R Qt+1 Q’t+1
S o o 0 0 0 Qt Q't
Qt+1
0 0 1 Qt Q't
0 1 0 Qt Q't
0 1 1 Qt Q't
o Q’t+1 1 0 0 11 Invalid
R o
1 0 1 10 Set state
1 1 0 01 Reset state
1 1 1 Qt Q't Previous state

Procedure:
Step.1. Construct a clocked RS flip-flop with four NAND gates.
Step.2. Connect the S and R inputs to the two switches and the clock input to a pulsar.
Step.3. Obtain the ‘truth-Table’ of the circuit.

Activity-3. Implementation of Positive Edge-Triggered D Flip-Flops Using 7474 IC

IC 7474 consists of two D-Positive Edge-triggered FFs with preset and clear. Its PIN assignment is
shown in Fig. Below.

4 10

2 PR 12 D PR
D Q 5 Q 9

3 11 CK
CK

Q’ 6
Q’ Q’ 8
CLR CLR
Vcc(14) 13
1
GND(7)

Fig. Logic Symbol

Observations: Function Table

Inputs Outputs
Preset Clear Clock D Q Q’
0 1 X X 1 0
1 0 X X 0 1
0 0 X X 1 1
1 1 0 0 1
1 1 1 1 0
1 1 0 X No Change No Change
Department of Electronics and Communication Engineering

The Function Table specifies the preset and clear operations and the clock operation. The clock is
shown with an upward arrow to indicate that it is a positive edge-triggered FF.
Investigate the operation of one of the FF and verify its function table.
Activity-4. Implementaion of Clocked JK Flip-Flops Using IC 7476
IC type 7476 consists of two JK Master-Slave FFs with Preset and Clear. The pin assignment for
each FF is shown in the Fig. below.

Observations: Function Table

Inputs Outputs
Preset Clear Clock J K Q Q’
0 1 X X X 1 0
1 0 X X X 0 1
0 0 X X X 1 1
1 1 0 0 No Change No Change
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 Toggle Toggle

From the Function-Table, the first three entries in the table specify the operation of the
asynchronous preset and the clear inputs. These inputs behaves like a NAND SR Latch and are
independent of the clock or J and K inputs. The last four entries in the function table specify the
 Department of Electronics and Communication Engineering

clock operation with both the preset and clear inputs maintained at the Logic ‘1’. The clock value is
shown as a ‘Single Pulse’.
Operations:
Follow the following steps to verify the operation of the IC 7476,
Step.1. The positive transition of the pulse changes the Master FF, and the negative transition
changes the Slave FF as well as the output of the circuit.
Step.2. With J = K = 0, the output does not change.
Step.3. With J = K =1, the FF Toggles (or complements).

Activity-5. Master-Slave JK Flip-Flop

J
Q

CLK

Q’
K

Observations: Truth-Table

Inputs
CLK J K
1 1
1 1
1 1
1 1
Department of Electronics and Communication Engineering

1 1 1 nc
1 1 nc 1
Procedure:

Step.1. Construct the circuit.

Step.2. Connect the J and K inputs to the Logic ‘1’ and the clock input to a pulsar.
Step.3. Connect the normal output of the Master FF to one of the indicator lamp and the normal
output of the slave to another Slave FF.
Step.4. Press the push button in the pulsar and then release it to produce a single positive pulse.
Observe and record the outputs of the Master and the Slave FFs.
Step.5. Repeat step.4 for a single negative pulse and record the outputs.
Step.6. Explain the ‘Transfer Sequence” from input to Master and from Master to Slave.
………C …lo…c…k h…ig…
h-…
Ma…s…ter…J…
K …………………………………………………...
C loc k low-sla v e JK
……………………………………………………………………………………...
……………………………………………………………………………………...