Journal of Circuits, Systems, and Computers

Vol. 27, No. 10 (2018) 1850160 (14 pages)

.c World Scienti¯c Publishing Company
#
DOI: 10.1142/S0218126618501608

A Low Power CMOS-Based VCO Design with I-MOS

Varactor Tuning Control¤

Manoj Kumar and Dileep Dwivedi†

University School of Information, Communication and Technology,
by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.

Guru Gobind Singh Indraprastha University, Sector — 16C,

J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

Dwarka, New Delhi, India

†
dileep.dwivedi@ipu.ac.in

Received 17 June 2017

Accepted 27 November 2017
Published 9 January 2018

This paper presents a new design of low power voltage controlled oscillator (VCO) circuit using
three transistors NOR-gate and I-MOS (inversion mode) varactor tuning method. Variation in
the oscillation frequency has been obtained by varying the output load capacitance with the use
of I-MOS varactor tuning consisting of two PMOS transistors connected in parallel. Variable
capacitance across the I-MOS varactor has been achieved by varying the source/drain voltage
(Vtune Þ and back-gate voltage (Vb Þ. Variation of Vtune from 1 V to 2 V provides the frequency
deviation from 1.970 GHz to 1.379 GHz with I-MOS width of 8
m at power supply voltage
(Vdd Þ of 1.8 V. Power consumption of the circuit is 1.296 mW with Vdd of 1.8 V. The results have
been obtained for di®erent I-MOS varactor widths like 5
m, 8
m and 10
m. Further, varia-
tions in the frequency have been obtained from 0.650 GHz to 2.584 GHz with the Vdd variation
from 1 V to 3 V. In addition, by variations of Vb from 0 V to 1.8 V and Vdd from 1 V to 3 V, the
proposed oscillators operate in the frequency range from 0.556 GHz to 2.584 GHz for 8
m width
of I-MOS varactor. Proposed VCO circuit show a phase noise of
89:779 dBc/Hz at 1 MHz
o®set from the carrier frequency and the ¯gure of merit (FoM) for the VCO is 154.51 dB/Hz.
Proposed VCO shows an improved performance in terms of power consumption, output
frequency and FoM.

Keywords: Back-gate tuning; CMOS; delay cell; I-MOS; low power; NOR gate; phase noise.

1. Introduction
Voltage controlled oscillators (VCOs) are the major building blocks in most of the
existing and emerging RF wireless system and clock/data recovery systems.1–4 These
are the most critical blocks which probably needed more consideration at the design
time because the e®ective tuning range, phase noise, gain of VCO and ¯gure of merit
(FoM) show their direct impact on the overall system performance. In addition, these
*This paper was recommended by Regional Editor Piero Malcovati.
† Corresponding author.

1850160-1
 M. Kumar & D. Dwivedi

circuits are also one of the most power starving blocks in RF circuit design. Various
VCOs design implementations have been proposed in the literature such as LC-based
and CMOS-based ring oscillator.5–10 Integrated LC oscillators su®er from a low-
frequency tuning range due to large parasitic capacitance.11 This problem further
increases when the power supply voltage is reduced due to scaling. To maintain a
wide tuning range in VCO low-loss varactors are required. Varactors are charac-
terized by a variable capacitance and resistance.12 MOS varactors are becoming more
popular over diode varactors, due to their high-quality factor (Q). Quality factor of
MOS varactors can be improved by higher doping levels in silicon. Due to higher
doping level, resistive losses reduce with lower power consumption and less phase
noise.11,13–15 MOS varactor with variable capacitance can be realized by MOS
by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.

transistor with drain, source and bulk (D, S and B) connected together. Value of
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

MOS capacitance depends on the voltage Vbg between bulk (B) and gate (G) ter-
minal. Generally, varactor includes three modes of operation: inversion region, de-
letion region and accumulation region. All the three modes of operation mainly
depend on the value of Vbg and jVt j. For MOS transistor to work in inversion region,
voltage across the bulk and gate terminal Vbg should be greater than the threshold
voltage jVt j. For strong inversion region (Vbg >> jVt j), when carrier concentration is
excessive under the gate oxide and for moderate inversion region (Vbg > jVt j). When
the value of bulk to gate voltage (Vbg Þ is greater than °at band voltage (Vfb Þ but less
than the threshold voltage (Vfb < Vbg < jVt j) then the MOS transistor works in de-
pletion region, where the mobility of charge carrier is low. When the value of gate
voltage is greater than bulk voltage, the MOS transistor works in accumulation
region.16
In the literature, frequency tuning of VCO is reported with di®erent methods like
delay variation of inverter stages, output load variations and varactor tuning con-
trol.17–23 For the proposed VCO, two PMOS transistors connected in parallel are
used as an I-MOS varactor. Further improvement in tuning range has been obtained
with the back-gate tuning of the I-MOS varactor which varies the substrate resis-
tance of I-MOS. This paper is organized as follows: Section 2 describes the VCO
architecture and modeling of I-MOS varactor. Result and discussion are described in
Sec. 3. Finally, Conclusion is drawn in Sec. 4.

2. VCO Architecture and I-MOS Modeling

CMOS ring VCO circuit based on delay stages using three transistors (3T) NOR-
gates and I-MOS varactor is designed in this work. Proposed VCO is based on single-
ended delay stages as shown in Fig. 1. Output frequency of single-ended ring VCO
with `N' number of delay cell is given by Eq. (1) as
1
foutput ¼ ; ð1Þ
2Ntd

1850160-2
 A Low Power CMOS-Based VCO Design with I-MOS Varactor Tuning Control

C C
C

Vtune /Vb

Fig. 1. VCO topology based on single-ended delay cells.

by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

where `N' is the total numbers of delay cells, td is the delay time of each delay cell.
Delay time of each delay cell is dependent on the load capacitance (C).
In the proposed ring, VCO circuit inverter delay cell has been designed with 3T
NOR-gates and I-MOS varactor is utilized as a frequency tuning element. Width of
the transistors in the 3T NOR gate has been sized to achieve the adequate signal
swing. The voltage deterioration can be minimized by increasing W/L ratio of
transistors. Threshold voltage relation with channel length and width of the MOS
transistor is given in Eq. (2).24
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi t t t
VT ¼ VT 0 þ  VSB þ ’0
l ox ðVSB þ ’0 Þ
v ox Vds þ w ox ðVSB þ ’0 Þ: ð2Þ
L L W
Here, Vt0 is the zero bias threshold voltage,  is bulk threshold coe±cient, 0 is 2F
and F is Fermi potential, tox is the width of oxide and l , v and w are the process
parameters. From (2), it is clear that by increasing the width (W), it is possible to
compensate the voltage deterioration. Proposed delay cell is shown in Fig. 2. A 3T

N1

P2
P1

Vb

Vtune

N2
P3

Fig. 2. Proposed delay cell.

1850160-3
 M. Kumar & D. Dwivedi

Table 1. Transistor sizing for delay stage.

Name of the transistor Width

N1 0.5
m
P1 1
m
N2 1.25
m
P2 and P3 8
m

NOR gate works as an inverter element when one of its input is grounded. Output of
this inverting element is connected with the varying capacitance i.e., I-MOS var-
actor. Capacitance of I-MOS varactor has been varied with source/drain voltage
(Vtune Þ and back- gate voltage (Vb Þ. Supply voltage has been taken as 1.8 V and gate
by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.

lengths of all transistors used in the proposed design have been taken as 0.18
m.
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

Width of di®erent MOS transistors has been given in Table 1.

A three stages ring VCO has been designed with proposed delay cell as shown in
the Fig. 3. Output of ¯rst delay stage is connected with the input of second delay
stage and output of second delay stage is connected of input of third delay stage.
Finally, the output of last delay stage is connected as feedback to the input of ¯rst
delay stage that forms a closed loop. For single-ended VCO, the odd numbers of
delay stages are needed for oscillation occurrence.
In the proposed VCO, I-MOS varactor has been used as a frequency tuning
element. I-MOS has been implemented by connecting two PMOS transistors back to
back in parallel. I-MOS varactor has two terminals for controlling the capacitance
and hence the output frequency. One terminal is back-gate voltage (Vb Þ and other
is the source/drain voltage (Vtune Þ. These two voltages provide the capacitive
tuning in proposed ring VCO circuit. Equivalent capacitive model of I-MOS is shown
in Fig. 4.

N1 N1 N1

P1 P1 P1
P2
P2 P2

Vtune Vtune Vtune

Vb
Vb Vb
N2 N2 N2

P3
P3 P3

Fig. 3. Proposed three-stages ring VCO.

1850160-4
 A Low Power CMOS-Based VCO Design with I-MOS Varactor Tuning Control

Cgs Cgd
Cox

Cbs Cdep Cbd

Vb

Vtune
Cbs Cdep
Cbd
by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.

Cox
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

Cgs Cgd

Fig. 4. Equivalent capacitive model of I-MOS varactor.

Here, Cox denotes the oxide capacitance between gate and substrate, Cdep is the
channel capacitance, Cgs and Cgd represent the parasitic capacitance between gate
and source/drain terminals. Cbs and Cbd are the bulk to source and bulk to drain
capacitance. Equivalent capacitance between the gate and the substrate is a series
combination of Cox and Cdep capacitance given by \Eq. (3)".
Cox Cdep
Cequi ¼ : ð3Þ
Cox þ Cdep
In source/drain voltage tuning method, with increase in Vds depletion width at source
end will decrease which results in increase in bulk to source capacitance (Cbs Þ. So
overall capacitance between the gates terminals increase with increase in Vds . Since
the time delay of a delay cell is directly related with the capacitance that leads to the
increase in delay time, the output oscillation frequency of ring VCO decreases. In
back-gate tuning method as the voltage across the substrate increases, more number
of electrons are attracted towards the substrate terminal, leaving larger positive
charge near the surface region that leads to the increase in the depletion width. Due
to increase in the back-gate voltage (Vb Þ equivalent capacitance (Ceq ) across the gate
and substrate decreases. In addition, with the increase in back-gate voltage (Vb Þ
depletion width of source and drain end also increases. Increase in depletion width
results in decrease in depletion capacitance. Capacitance between bulk and source
terminal (Cbs Þ and capacitance between bulk and drain terminal (Cbd Þ as shown in
Fig. 4 also decreases with the increasing Vb . So, the overall capacitance of MOS
varactor decreases that leads to the decrease in the delay time of delay cell and
increase in the output oscillation frequency.

1850160-5
 M. Kumar & D. Dwivedi

3. Results and Discussions

Proposed ring VCO has been designed in TSMC 0.18
m CMOS technology with
supply voltage of 1.8 V. Variation in the output frequency has been obtained by
varying both source/drain voltage (Vtune Þ and back-gate voltage (Vb Þ of I-MOS
varactor. Table 2 shows the variation in output frequency with the variation in
source/drain tuning voltage (Vtune Þ of I-MOS with power supply (Vdd Þ and back-gate
voltage (Vb Þ of 1.8 V. With the rise in Vtune the net capacitance at the output node of
delay stage increases which further a®ects the time delay of a 3T-NOR-based in-
verter stage. Output frequency reduces with the increase in Vtune as depicted in
Table 3. Power consumption of the proposed VCO is 1.269 mW as the power supply
is ¯xed at 1.8 V for I-MOS source drain tuning method. Width of I-MOS varactor
by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

directly a®ects the output capacitance so the output frequency decreases with in-
creasing width as shown in Table 2.
Table 3 shows the variation in output oscillation frequency with power supply
(Vdd Þ tuning method for the I-MOS varactor width of 5
m, 8
m and 10
m. Source/
drain voltage (Vtune Þ for I-MOS has been ¯xed at 0 V for this case. Output frequency
is showing rising trend with increase in the power supply voltage as the more bias
current °ow in delay stage and subsequently the time delay of three transistor NOR
inverter stage decreases. With the increase in the I-MOS varactor width, the net
output node capacitance increases and subsequently, the output frequency decreases
as depicted in Table 3. Power consumption of the proposed VCO increases with rise
in the Vdd as the supply voltage directly a®ects the power consumption.
Table 4 shows the output frequency results for di®erent values of back-gate
voltage (Vb Þ with the variation in supply voltage (Vdd Þ. Width of varactor has been
taken as 8
m and back-gate voltage of I-MOS varactor has been varied from 0 V to
1.8 V. With the increase in the back-gate voltage (Vb Þ of I-MOS varactor the output
node capacitance of the delay stage decreases and subsequently the output frequency
increases as shown in Table 4.

Table 2. Source/drain tuning of 3-stages VCO with di®erent I-MOS widths.

Frequency (GHz)

I-MOS tune voltage (Vtune ) WI ¼ 5
m WI ¼ 8
m WI ¼ 10
m WI ¼ 15
m Power consumption (mW)

1.0 V 2.668 1.970 1.650 1.184 1.269

1.1 V 2.626 1.948 1.632 1.158 1.269
1.2 V 2.563 1.896 1.587 1.134 1.269
1.3 V 2.491 1.830 1.536 1.094 1.269
1.4 V 2.415 1.767 1.479 1.044 1.269
1.5 V 2.333 1.685 1.416 1.000 1.269
1.6 V 2.249 1.606 1.337 0.945 1.269
1.7 V 2.165 1.536 1.278 0.901 1.269
1.8 V 2.086 1.469 1.219 0.856 1.269
1.9 V 2.010 1.418 1.179 0.828 1.269
2.0 V 1.975 1.379 1.150 0.790 1.269

1850160-6
 A Low Power CMOS-Based VCO Design with I-MOS Varactor Tuning Control

Table 3. Power supply tuning of 3-stages ring VCO with di®erent I-MOS widths at Vb ¼ 1:8 V, Vtune ¼ 0 V.

Frequency (GHz)
Power supply tuning (Vdd Þ WI ¼ 5
m WI ¼ 8
m WI ¼ 10
m Power consumption (mW)
1.0 V 0.910 0.650 0.551 0.129
1.2 V 1.440 1.023 0.859 0.290
1.4 V 1.922 1.383 1.157 0.529
1.6 V 2.341 1.688 1.405 0.854
1.8 V 2.695 1.943 1.622 1.269
2.0 V 3.153 2.139 1.805 1.777
2.2 V 3.218 2.315 1.949 2.377
2.4 V 3.393 2.443 2.049 3.070
2.6 V 3.515 2.525 2.115 3.854
by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.

2.8 V 3.592 2.572 2.155 4.726

J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

3.0 V 3.621 2.584 2.172 5.685

Table 4. Output frequency versus power supply for di®erent back-gate voltages of I-MOS varactor
(WI ¼ 8
m).

Power Frequency (GHz), Frequency (GHz) Frequency (GHz) Frequency (GHz) Power
supply (Vdd Þ Vb ¼ 0 V Vb ¼ 0:5 V Vb ¼ 1:0 V Vb ¼ 1:8 V consumption (mW)

1.0 V 0.556 0.621 0.627 0.650 0.129

1.2 V 0.855 0.958 0.992 1.023 0.290
1.4 V 1.102 1.258 1.334 1.383 0.529
1.6 V 1.305 1.504 1.618 1.688 0.854
1.8 V 1.485 1.694 1.848 1.943 1.269
2.0 V 1.627 1.845 2.031 2.139 1.777
2.2 V 1.732 1.937 2.160 2.315 2.377
2.4 V 1.821 2.011 2.223 2.443 3.070
2.6 V 1.876 2.051 2.265 2.525 3.854
2.8 V 1.907 2.054 2.266 2.573 4.726
3.0 V 1.920 2.059 2.250 2.584 5.685

Figure 5 shows the frequency variation of VCO for di®erent I-MOS varactor
widths with source/drain (Vtune Þ controlling technique. Figure 6 shows the frequency
variations with change in the power supply for di®erent I-MOS varactor widths.
Power consumption variation trend with the change in power supply has been shown
in Fig. 7. Frequency variations with power supply tuning with di®erent value of
back-gate voltage (Vb Þ has been shown in Fig. 8. Output waveform for the proposed
VCO has been shown in Figs. 9(a)–9(c).
Phase noise is an essential parameter to study the noise performance of the ring
oscillator. Phase noise results with 1 MHz o®set from the carrier frequency have been
obtained and waveforms are shown in Figs. 10(a)–10(c) for di®erent value of I-MOS
tune voltage (Vtune Þ and back-gate voltage (Vb Þ. FoM is a widely used parameter for
evaluation of VCO performance and is de¯ned as25:
fc P
FoM ¼ 20 log
10 log DC mW
Lð
fÞ: ð4Þ

f 1

1850160-7
 M. Kumar & D. Dwivedi

3
Output Frequency (GHz)

2.5

2 WI=5µm
WI=8µm
1.5
WI=10µm
1 WI=15µm
0.5

0
0.9 1.1 1.3 1.5 1.7 1.9 2.1
Tuning Volttage (V)

Fig. 5. Output frequency variation versus Vtune .

by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

4
3.5
Output Frequency (GHz)

3
2.5 WI= 5µm
2 WI= 8µm
1.5 WI= 10µm
1
0.5
0
0.9 1.4 1.9 2.4 2.9
Power Supply (V)

Fig. 6. Frequency variation with power supply (Vdd Þ.

Lð
fÞ is the phase noise of the VCO in dBc/Hz at
f o®set from the carrier
frequency fc , and PDC is the power consumption in mW. FoM has been calculated as
per the equation (4). Table 5 shows the details regarding phase noise and FoM for
di®erent value of supply voltage and control voltages. FoM of the proposed VCO
varies from 150.48 dBc/Hz to 157.46 dBc/Hz for di®erent tuning conditions.

5
Power Consumption (mW)

0
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
Power Supply (V)

Fig. 7. Power consumption variation with Vdd .

1850160-8
 A Low Power CMOS-Based VCO Design with I-MOS Varactor Tuning Control

2.5
Output Freqqency (GHz)

2 Vb= 0V
Vb= 0.5V
1.5
Vb= 1.0V
1 Vb= 1.8V

0.5

0
0.9 1.4 1.9 2.4 2.9
Power Supply (V)

Fig. 8. Frequency versus Vdd variations for di®erent values of back-gate voltage (Vb Þ.
by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

(a)

(b)

Fig. 9. Waveforms of VCO for (a) Vtune ¼ 1 V, Vdd ¼ Vb ¼ 1:8 V (b) Vtune ¼ 2 V, Vdd ¼ Vb ¼ 1:8 V (c)
Vtune ¼ 0 V, Vdd ¼ Vb ¼ 1:8 V.

1850160-9
 M. Kumar & D. Dwivedi
by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

(c)

Fig. 9. (Continued )

Results of output frequency, power consumption, phase noise and FoM of pro-
posed VCO have been compared with earlier reported circuits. Table 6 summarizes
and compares the performance of proposed ring VCO with previous work. Proposed
VCO circuit provides the wide tuning range with low power consumption.

(a)

Fig. 10. Phase noise at (a) Vdd ¼ 3 V, Vb ¼ 1:8 V, Vtune ¼ 0 V. (b) Vdd ¼ 1:8 V, Vb ¼ 1:8 V, VTune ¼ 0 V.
(c) Vdd ¼ 1:8 V, Vb ¼ 1:8 V, Vtune ¼ 1:8 V.

1850160-10
 A Low Power CMOS-Based VCO Design with I-MOS Varactor Tuning Control
by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

(b)

(c)

Fig. 10. (Continued )

Table 5. Phase noise result of proposed VCO.

Power Back gate tuning Source/drain Phase noise of Output Power

supply voltage of bias voltage VCO@1MHz frequency consumption FoM
tuning (Vdd Þ I-MOS (Vb Þ of I-MOS (Vtune Þ (dBc/Hz) (GHz) (mW) (dBc/Hz)
3.0 V 1.8 V 0V
89.782 2.584 5.685 150.48
1.8 V 1.8 V 0V
89.779 1.943 1.269 154.51
1.8 V 1.8 V 1.0 V
89.782 1.921 1.269 154.41
1.8 V 1.8 V 1.8 V
89.779 1.436 1.269 151.88
1.8 V 1.0 V 1.8 V
89.777 1.372 1.570 150.55
1.8 V 0.5 V 1.8 V
89.777 1.375 2.507 148.55
1.0 V 1.0 V 1.0 V
93.676 0.557 0.129 157.46

1850160-11
 M. Kumar & D. Dwivedi

Table 6. Comparison of VCO performances.

Power
Frequency Technology Phase noise consumption FoM
References range (GHz) (
m) (dBc/Hz) (mW) (dBc/Hz)
2 1.8–2.4 0.18
98.24@1 MHz 6

3 0.020
0.807 0.18
108@1 MHz 22 150.6
4 0.090
0.152 0.18
99.35@1 MHz 9 —
7 1.77
1.92 0.18
102@1 MHz 13 156.3
8 0.770
5.287 0.18
97.93@1 MHz 15.1 160.6
14 5.16
5.93 0.18
99.5@1 MHz 80 155.72
17 8.1
10.5 0.18
92@1 MHz 68.4 153.2
20 0.5
1.2 0.18
90@1 MHz 0.71 151.48
by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.

87@1 MHz
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

21 0.059
2.96 0.18 3 143

22 4.2
5.9 0.18
99.1@1 MHz 58 156.28
23 7.3
7.86 0.13
103.4@1 MHz 60 163.3
Present 1.379
1.970 0.18
89.77@1 MHz 1.26 154.51
work (IMOS source/drain tuning)
0.556
2.584 (IMOS back
gate tuning) 0.650
2.584
(Power supply tuning)

4. Conclusions
In this paper, a new low power voltage controlled ring oscillator (VCO) with I-MOS
varactor frequency tuning control has been designed in 0.18
m CMOS technology.
The oscillator consists of three delay stages and each delay stage has one three-
transistor NOR gate and I-MOS varactor consisting of two PMOS transistor con-
nected in parallel. The proposed VCO operates in the frequency range from
1.970 GHz to 1.379 GHz with the variation in source/drain voltage (Vtune Þ from 1V to
2V and consumes the power of 1.269 mW with 1.8 V supply voltage. Further, var-
iations in the output frequency have been obtained from 0.650 GHz to 2.584 GHz
with the power supply voltage (Vdd Þ variations from 1V to 3V. Frequency deviations
from 0.556 GHz to 2.584 GHz has been obtained with back gate voltage (Vb Þ tuning
from 0 V to 1.8 V. The VCO power consumption varies from 0.129 mW to 5.685 mW
with power supply variation from 1 V to 3 V. E®ects of I-MOS varactor width have
also been considered and the results have been obtained with the di®erent varactor
width in this work. The phase noise for proposed VCO is
89.77 dBc/Hz at 1 MHz
o®set from carrier frequency and the corresponding FoM is 154.51 dBc/Hz. Com-
pared with previously reported circuits, the proposed VCO shows the advantages of
low power, wide tuning range and improved FoM. Therefore, the proposed VCO
circuit can be utilized as circuit component in PLL and low-power communication
systems.

1850160-12
 A Low Power CMOS-Based VCO Design with I-MOS Varactor Tuning Control

References
1. H. Thabet, S. Meillere, M. Masmoudi, J. L. Seguin, H. Barthelemy and K. Aguir, A low
power consumption CMOS di®erential-ring VCO for a wireless sensor, Analog Integr.
Circuits Signal Process. 73 (2012) 731–740.
2. J. Jin, Low power current-mode voltage controlled oscillator for 2.4 GHz wireless
applications, Comput. Electr. Eng. 40 (2014) 92–99.
3. J. Choi, K. Lim and J. Laskar, A ring VCO with wide and linear tuning characteristics for
a cognitive radio system, in Radio Frequency Integrated Circuits Symp. (RFIC 2008)
(Atlanta, GA), pp. 395–398.
4. W. H. Lee, B. J. Gu, Y. Nishida, H. Takao, K. Sawada and M. Ishida, Oscillation-
controlled CMOS ring oscillator for wireless sensor systems, Microelectron. J 41 (2010)
815–819.
by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.

5. M. Kumar, S. Arya and S. Pandey, Ring VCO design with variable capacitance XNOR
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

delay cell, J. Inst. Eng. 96 (2015) 371–379, doi: 10.1007/s40031-014-0154-4.

6. J. K. Panigrahi and D. P. Acharya, Performance analysis and design of wideband CMOS
voltage controlled ring oscillator, 5th IEEE Int. Conf. Industrial and Information Systems
(IEEE, Mangalore, India, 2010), pp. 234–238.
7. Z. Z. Chen and T. C. Lee, The design and analysis of dual-delay-path ring oscillators,
IEEE Trans. Circuits. Syst. I. Regul. Pap. 58 (2011) 470–478.
8. L. Xuemei, W. Zhigong and S. Lianfeng, Design and analysis of a three-stage voltage-
controlled ring oscillator, J. Semicond. 34 (2013) 115003.
9. Y. Luo, C. Ma, Y. Gan, M. Qian and T. Ye, A dual-band CMOS LC-VCO with highly
linear frequency tuning characteristics, Microelectron. J. 46 (2015) 1420–1425.
10. S. Y. Lee and J. Y. Hsieh, Analysis and implementation of a 0.9-V voltage-controlled
oscillator with low phase noise and low power dissipation, IEEE Trans. Circuits. Syst. II.
Express Briefs 55 (2008) 624–627.
11. C. Y. Wu and C. Y. Yu. A 0.8 V 5.9 GHz wide tuning range CMOS VCO using inversion-
mode bandswitching varactors, IEEE Int. Symp. Circuits and Systems (ISCAS 2005),
(IEEE, Krobe, Japan), pp. 5079–5082.
12. F. Svelto, P. Erratico, S. Manzini and R. Castello, A metal-oxide-semiconductor varactor,
IEEE Electron Device Lett. 20 (1999) 164–166.
13. V. R. Gonzalez-Diaz, L. A. Sanchez-Gaspariano, C. Muñiz-Montero and J. J. Alvarado-
Pulido, Improving linearity in MOS varactor based VCOs by means of the output
quiescent bias point, Integr. VLSI J. 55 (2016) 274–280.
14. Y. A. Eken and J. P. Uyemura, A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl
mu/m CMOS, IEEE J. Solid-State Circuits 39 (2004) 230–233.
15. J. Maget, M. Tiebout and R. Kraus, In°uence of novel MOS varactors on the performance
of a fully integrated UMTS VCO in standard 0.25-
m CMOS technology, IEEE J. Solid-
State Circuits 37 (2002) 953–958.
16. P. Andreani and S. Mattisson, On the use of MOS varactors in RF VCOs, IEEE J. Solid-
State Circuits 35 (2000) 905–910.
17. H. Q. Liu, W. L. Goh and L. Siek, 1.8-V 10-GHz ring VCO design using 0.18-
m CMOS
technology, Proceedings 2005 IEEE International SOC Conference, Herndon, VA, 2005,
pp. 77–78, doi: 10.1109/SOCC.2005.1554459.
18. M. Li, R. E. Amaya, R. G. Harrison and N. G. Tarr, Investigation of CMOS varactors
for high-GHz-range applications, J. Electr. Comput. Eng. 25 (2009) Article ID 535809,
4 pages, doi: 10.1155/2009/535809.

1850160-13
 M. Kumar & D. Dwivedi

19. S. Ikeda, S. Y. Lee, H. Ito, N. Ishihara and K. Masu, 0.5 V 5.8 GHz highly linear current-
reuse voltage-controlled oscillator with back-gate tuning technique, Jpn. J. Appl. Phys.
54 (2015) 04DE06, doi: 10.7567/JJAP.54.04DE06.
20. T. Yoshida, N. Ishida, M. Sasaki and A. Iwata, Low-voltage, low-phase-noise ring volt-
age-controlled oscillator using 1/f-noise reduction techniques, Jpn. J. Appl. Phys. 46
(2007) 2257.
21. W. T. Lee, J. Shim and J. Jeong, Design of a three-stage ring-type voltage controlled
oscillator with a wide tuning range by controlling the current level in an embedded delay
cell, Microelectron. J. 44 (2013) 1328–1335.
22. C. Danfeng, R. Junyan, D. Jingjing, L. Wei and L. Ning, A multiple-pass ring oscillator
based dual-loop phase-locked loop, J. Semicond. 30 (2009) 105014.
23. H. Q. Liu, W. L. Goh, L. Siek, W. M. Lim and Y. P. Zhang, A low-noise multi-GHz
CMOS multiloop ring oscillator with coarse and ¯ne frequency tuning, IEEE Trans. Very
by UNIVERSITY OF NEW ENGLAND on 01/10/18. For personal use only.

Large Scale Integr. (VLSI) Syst. 17 (2009) 571–577.

J CIRCUIT SYST COMP Downloaded from www.worldscientific.com

24. Y. Tsividis, Mixed Analog-Digital VLSI Devices and Technology (McGraw Hill,
Singapore, 1996).
25. P. Andreani, A. Bonfanti, L. Romano and C. Samori, Analysis and design of a 1.8-GHz
CMOS LC quadrature VCO, IEEE J. Solid-State Circuits 37 (2002) 1737–1747.

1850160-14