RISC CISC

1. Multiple register set often consisting of more than 1. Single resistor set typically 6 to 16 registers in total
256 registers.
2. three register operands allowed per instruction 2. One or two register allowed per instruction.
e.g. Add R1, R2, R3 e.g. Add R1, R2
3. Hardware control 3. micro programmed control
4. Highly pipelined 4. less pipelined
5. Simple in instructions that are few in number 5. many complex instructions
6. Fixed length instruction 6. variable length instructions
7. complexity in compiler 7. complexity in micro-code
8. Few address modes 8. Many addressing modes
9. only load and stored instruction can access memory 9. Many instruction can access memory
10. single cycle instructions 10. Multiple cycle instruction
(except for load and store)
11. parameter passing through efficient on chip register 11. parameter passing through inefficient chip memory
windows
12. reduced instruction set computer 12. complex instruction set computer

Big Endian and little endian:

Big Endian: machine that stores the most significant byte first (Left to right)

A B C D

Little Endian: machine that stores the most significant byte first (Right to left)

A B C D

Instruction Characteristics
Elements of a Machine Instruction: Each instruction must contain the information required by the CPU for
execution. Elements of a Machine Instruction are:
 Operation Code: Specifies the operation to be performed. The operation is specified by a binary
code, known as the operation code, or opcode.
 Source operand reference: The operation may involve one or more source operands; that is,
operands that are the inputs for the operation.
 Result operand reference: The operation may produce a result.
 Next instruction reference: This tells the CPU where to fetch the next instruction after the
execution of this instruction is complete.

The next instruction to be fetched is located in main memory or in case of virtual memory system it can be
either in main memory or secondary memory. In most cases, the next instruction to be fetched
immediately follows the current instruction. In those cases, there is no explicit reference to the next
instruction. But when explicit reference is needed, then the main memory or virtual memory address must
be supplied. The form in which the address is supplied is discussed in this section. Source and Result
operands can be in one of the three areas:
 Main (or virtual) memory: The memory address must be supplied.
 CPU register: CPU contains one or more registers that may be referenced by machine instructions.
If only one register exists, reference to it may be implicit. If more than one register exists, then each
register is assigned a unique number, and the instruction must contain the number of the desired
register.
  I/O device: The instruction must specify the I/O module or device for the operation. If memory-
mapped I/O is used, this is just another memory address.

Instruction Representation
Each instruction is represented by a sequence of bits. The instruction is divided into fields, corresponding
to the constituent elements of the instruction. This layout of the instruction is called instruction format.
With most instruction sets, more than one format is used. It is difficult for a programmer and the reader to
deal with binary representations of machine instructions. Hence usually the instructions are written in
symbolic representations of machine code using English like language called mnemonics.

Thus operation codes in short Opcodes are represented using mnemonics. The format for this instruction is
given in figure

Opcode Op. Ref Operand Reference

A simple instruction format

In most modern CPU's, the first byte contains the opcode, sometimes including the register reference in
some of the instructions. The operand references are in the following bytes (byte 2, 3, etc...).
Examples of few mnemonics:

Mnemonics Description
ADD add
SUB subtract
MUL Multiply
LOAD Load data from memory
MOV A, B Move contents of B register to A register,
where A & B are user visible registers of CPU
An instruction with a register and memory address operands.

8 bits 8 bits 16/32 bits

Opcode Operand Ref. Operand Reference
register reference memory address
An instruction may span to the second byte

12 bits 4 bits
Opcode Operand Ref.
register reference
2 byte instruction
For example consider an instruction ADD R, Y
Assuming that it means that add the contents of data location Y of the memory to the contents of register
R. The operation is performed on the data present in location Y and not on its address i.e., Y itself.
Previous to the execution of add instruction he gives a list of specifications like X= 153, Y=154
And R=20. And the contents of memory at location 153 is 10 and at 154 it is 20.
After the execution of the given ADD R, Y
The result will be in R and will be equal to {R=20+[Y=154] =20} =40.
Instruction Types
Example: High level language statement: X = X + Y
If we assume a simple set of machine instructions, this operation could be accomplished with three
instructions: (assume X is stored in memory location 624, and Y in memory loc. 625.)
1. Load a register with the contents of memory location 624.
2. Add the contents of memory location 625 to the register,
3. Store the contents of the register in memory location 624.

As we have seen before, the instructions fall into one the following four categories:
• Data processing: Arithmetic and logic instructions.
• Data storage: Memory instructions.
• Data movement: I/O instructions.
• Control: Test and branch instructions.

What is the maximum number of addresses one might need in an instruction?

Virtually all arithmetic and logic operations are either unary (one operand) or binary (two operands). The
result of an operation must be stored, suggesting a third address. Finally, after the completion of an
instruction, the next instruction must be fetched, and its address is needed.
This line of reasoning suggests that an instruction could be required to contain 4 address references: two
operands, one result, and the address of the next instruction. In practice, the address of the next
instruction is handled by the program counter; therefore most instructions have one, two or three
operand addresses. Three-address instruction formats are not common, because they require a relatively
long instruction format to hold three address references.

Utilization of Instruction Addresses (Non-branching Instructions):

No. Number of Addresses Symbolic Interpretation
Representation
a 3 Address Inst. OP A, B, C A <- B OP C
b 2 Address Inst. OP A, B A <- A OP B
c 1 Address Inst. OP A AC <- AC OP A, (AC is Aaccumulator)
d 0 Address Inst. OP T <- T OP (T-1)

3 address Instruction Format 2 address Instruction Format

 3 addresses needed  One address doubles as

 Operand 1, Operand 2, Result operand and result

 a = b + c;  a=a+b

 May be a forth - next instruction  Reduces length of instruction

(usually implicit)  Requires some extra work

 Not common  Temporary storage to hold

 Needs very long words to hold some results

everything
 1 address Instruction Format 0(zero ) address Instruction Format
 1addresses needed  No address needed

 Implicit second address  All addresses implicit

 Usually a register (accumulator)  Uses a stack

 Common on early machines  Dis adv: possibility of

underflow and overflow

 e.g. push a

push b

add

pop c

c=a+b

Q. Define Stack. Explain how arithmetic operation (A-B)/(C+A*D +B/C) is

calculated by implementing.

Three address Comment

SUB Y, A, B; YM[A]-M[B]
MPY T, D, E; TM[D]-M[E]
ADD T, T, C; TT+M[C]
DIV Y, Y, T; YY/T
Two address Comment
MOVE Y, A YA
SUB Y, B YY-B
MOV T, D TD
MPY T, E TT*E
ADD T, C TT+C
DIV Y, T YY/T

One address Comment

LOAD D ACD
MPY E ACAC*E
ADD C ACAC+C
STOR Y YAC
LOAD A ACA
SUB B ACAC-B
DIV Y ACAC/Y
STOR Y YAC
Zero address Comment
PUSH D TOSD
PUSH E TOSE
MPY TOSD*E
PUSH C TOSC
ADD TOSD*E+C
POP Y YTOS
PUSH A TOS A
PUSH B TOS TOSB
SUB TOS A-B
DIV TOS(A-B)/Y
POP Y YTOS

Program to execute Y = ( A – B ) / ( C + D x E) ?

Solution: With One-Address Instructions:(requires an accumulator AC)

Solution to example
LOAD D AC <- D
MUL E AC <- AC x E
ADD C AC <- AC + C
STOR Y Y <- AC
LOAD A AC <- A
SUB B AC <- AC – B
DIV Y AC <- AC / Y
STOR Y Y <- AC

A) With of Two-Address Instructions:

Solution to example
MOVE Y, A Y <- A
SUB Y, B Y <- Y – B
MOVE T, D T <- D
MUL T, E T <- T x E
ADD T, C T <- T + C
DIV Y, T Y <- Y / T
B) With of Three-Address Instructions:
Solution to example
SUB Y, A, D Y <- A – B
MUL T, D, E T <- D x E
ADD T, T, C T <- T + C
DIV Y, Y, T Y <- Y / T

Q. Consider a system which supports both 1 address and 2- address instruction the fixed length 16 bit inst.
It stored in 128 word memory. If there exists “2” two address inst. What will be the no. of one address
inst. Supported by the above system?

Instruction Set Design

The design of an instruction set is very complex, since it affects many different aspects of the computer
system. The instruction set defines many of the functions performed by CPU. The instruction set is a
programmer’s means of implementation of the CPU.
The fundamental design issues in designing an instruction set are:
 Operation Repertoire: How many and which operations to provide, and how complex operations
should be.
 Data Types: The various types of data upon which operations are performed.
 Instruction Format: Instruction length (in bits), number of addresses, size of various fields, and so on.
 Registers: Number of CPU registers that can be referenced by instructions and their use.
 Addressing modes: The mode or modes by which the address of an operand is specified.
These issues are highly interrelated and must be considered together in designing an instruction set.

Types of Operands
The most important general categories of data are:
 Addresses
 Numbers
 Characters
 Logical data
Characters
International Reference Alphabet (IRA) which is referred to as ASCII in the USA. Each character in this code is
represented by a unique 7-bit pattern, thus 128 different charcters can be represented. Some of the patterns
represent control characters. ASCII – encoded characters are usually stored and transfered as 8-bits per character.
The eight bit may be set to 1 or 0 for even parity. EBCDIC character set used in IBM 370 machines. İt is an 8-bit code.
Logical Data
With logical data memory can be used most efficiently for this storage. Boolean data. 1 = true, 0 = false.
A set of general types of operations is as follows:
Types of Operations
A set of general types of operations is as follows:
Data transfer
İs the most fundamental type of machine instruction. The data transfer must specify
1) the location of the source and destination each location can be memory, register or top of stack
2) the length of the data to be transferred
3) The mode of addressing for each operand

If both the operands are CPU registers, then the CPU simply causes data to be transfered from one register
to another. This operation is internal to the CPU. If one or both operands are in memory, then the CPU
must perform some or all of the following actions:

1. Calculate the memory address, based on the address mode.

2.if the address refers to virtual memory, translate from virtual to actual memory address.
3. Determine whether addressed item is in cache.
4. If not issue command to memory module.

For example: Move, Store, Load (Fetch), Exchange, Clear (Reset), set, Push, Pop

Arithmetic
Most machines provide basic arithmetic functions like Add, Subtract, Multiply, Divide. They are invariably
provided for signed integer numbers. Often they are also provided for floating point and packed decimal
numbers. Also some operations include only a single operand like Absolute that takes only absolute value
of the operand, Negate that takes the compliment of the operands, Increment that increments the value of
operand by 1, Decrement that decrements the value of operand by 1.
Logical
Machines also provide a variety of operations for manipulating individual bits of a word often referred to
as bit twiddling. They are based on Boolean operations like AND, OR, NOT, XOR, Test, Compare, Shift,
Rotate, Set control variables.
Conversion
These instructions are the one that change the format or operate on the format of the data. Examples are
Translate, Convert.
I/O, System control
There are variety of approaches like isolated programmed I/O, memory mapped I/O, DMA and so on.
Examples: Output (Write), Start I/O, Test I/O.
Transfer of Control
The instruction specifies the operation. In the normal course of events the next instruction to be
performed is the one immediately follows the current instruction in memory. But when the transfer of
control type instruction occurs they specify the location of the next instruction that is to be executed. For
example : Jump (Branch), Jump Conditional, Jump to Subroutine, Return, Execute, Skip, Skip Conditional,
Halt, Wait (Hold), No Operation.
System Control
These instructions are reserved for the use of Operating system. Instructions that can only be executed
while the processor is in a privileged state, or is executing a program in a special privileged area of
memory.

Addressing Modes
In general, a program operates on data that reside in the computer’s memory. These data can be
organized in a variety of ways. If we want to keep track of students’ names, we can write them in a list. If
we want to associate information with each name, for example to record telephone numbers or marks in
various courses, we may organize this information in the form of a table. Programmers use organizations
called data structures to represent the data used in computations. These include lists, linked lists, arrays,
queues, and so on.

Programs are normally written in a high-level language, which enables the programmer to use constants,
local and global variables, pointers, and arrays. When translating a high-level language program into
assembly language, the compiler must be able to implement these constructs using the facilities provided
in the instruction set of the computer in which the program will be run. The different ways in which the
location of an operand is specified in an instruction are referred to as addressing modes.

There are the following addressing modes:

• Immediate Addressing
• Direct Addressing
• Indirect Addressing
• Register Addressing
• Register Indirect Addressing
• Displacement Addressing
• Stack Addressing (auto addressing mode)
Notation:
A = contents of an address field in the instruction
R = contents of an address field in the instruction that refers to a register
EA = effective (actual) address of the location containing the referenced operand
(X) = contents of location X
Basic Addressing Modes

Mode Algorithm Principal Advantage Principal

Disadvantage
Immediate Operand = A No memory reference Limited operand
magnitude
Direct EA = A Simple Limited address
space
Indirect EA = (A) Large address space Multiple memory
references
Register EA = R No memory reference Limited address
space
Register EA = (R) Large address space Extra memory
Indirect reference
Displacement EA = A + (R) Flexibility Complexity
Stack EA = top of No memory reference Limited capability
stack

1. immediate addressing mode

The operand is actually present ın the instruction.
Operand = A
Can be used to define and use constants, or set initial values.
 Operand is part of instruction
 Operand = address field
E.g. ADD 5
— Add 5 to contents of accumulator
— 5 is operand
Points:
 No memory reference to fetch data
 Fast
 Limited range
Instruction

Opcode Operand

For example, the instruction Move 200 immediate, R0 places the value 200 in register R0. Clearly, the
immediate mode is only used to specify the value of a source operand. Using a subscript to denote the
immediate mode is not appropriate in assembly languages. A common convention is to use the sharp sign
(#) in front of the value to indicate that this value is to be used as an immediate operand.
Hence, we write the instruction above in the form Move # 200, R0 Constant values are used frequently in
high-level language programs.
For example, the statement, A = B + 6 contains the constant 6. Assuming that A and B have been declared
earlier as variables and may be accessed using the Absolute mode, this statement may be compiled as
follows:
Move B, R1 ; Add #6, R1 ; Move R1, A

Constants are also used in assembly language to increment a counter, test for some bit pattern, and so on.
2. Direct Addressing mode

• Address field contains address of operand

• Effective address (EA) = address field (A)
E.g. ADD A
— add contents of cell A to accumulator
— Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space
Instruction
Opcode Address

Operand

The operand is in a memory location; the address of this location is given explicitly in the instruction. (In
some assembly languages, this mode is called Direct.)

The instruction Move LOC, R2 uses these two modes the data in a register are accessed using the Register
mode. The Absolute mode can represent global variables in a program.
A declaration such as Integer A, B; in a high- level language program will cause the compiler to allocate a
memory location to each of the variables A and B. Whenever they are referenced later in the program, the
compiler can generate assembly language instructions that use the Absolute mode to access these
variables.

Next, let us consider the representation of constants. Address and data constants can be represented in
assembly language using the immediate mode.

3. Indirect Addressing mode

Opcode

pointer to
operand
o

Operand

 Memory cell pointed to by address field contains the

Address of (pointer to) the operand
• EA = (A)
— Look in A, find address (A) and look there for operand
• e.g. ADD (A)
— Add contents of cell pointed to by contents of A to accumulator
• Multiple memory accesses to find operand
• Hence slower
Indirect mode — The effective address of the operand is the contents of a register or memory location
whose address appears in the instruction.
We denote indirection by placing the name of the register or the memory address given in the instruction
in parentheses as illustrated in Figure and Table.

4. Register Addressing mode

Registers
Opcode Register Address R


 Operand




 Operand is held in register named in address filed
 EA = R
 Limited number of registers
 Very small address field needed
 Shorter instructions
 Faster instruction fetch
 No memory access
 Very fast execution
 Very limited address space
 Multiple registers helps performance
 Requires good assembly programming or compiler writing
 N.B. C programming
 register int a;

5. Register Indirect Addressing mode

• EA = (R)
• Operand is in memory cell pointed to by contents of register R
• Large address space (2n)
• One fewer memory access than indirect addressing
6. Displacement Addressing mode
• EA = A + (R)
• Address field hold two values
— A = base value
— R = register that holds displacement
— or vice versa
Relative addressing
• A version of displacement addressing
• R = Program counter, PC
• EA = A + (PC)
Base- register addressing
• A holds displacement
• R holds pointer to base address
• R may be explicit or implicit
7. Stack Addressing mode (auto addressing mode)
 Operand is (implicitly) on top of stack
 e.g. ADD Pop top two items from stack and add
• A = base
• R = displacement
• EA = A + R
• Good for accessing arrays
— EA = A + R
— R++
8. Other additional addressing modes
The two modes described next are useful for accessing data items in successive locations in the
memory.
Auto increment mode — The effective address of the operand is the contents of a register specified in
the instruction. After accessing the operand, the contents of this register are automatically
incremented to point to the next item in a list.
We denote the Auto increment mode by putting the specified register in parentheses, to show that the
contents of the register are used as the effective address, followed by a plus sign to indicate that these
contents are to be incremented after the operand is accessed. Thus, the Auto increment mode is
written as (Ri )+.
Subroutines
In a given program, it is often necessary to perform a particular subtask many times on different data
values. Such a subtask is usually called a subroutine. For example, a subroutine may evaluate the sine
function or sort a list of values into increasing or decreasing order. It is possible to include the block of
instructions that constitute a subroutine at every place where it is needed in the program. However, to
save space, only one copy of the instructions that constitute the subroutine is placed in the memory, and
any program that requires the use of the subroutine simply branches to its starting location. When a
program branches to a subroutine we say that it is calling the subroutine. The instruction that performs
this branch operation is named a Call instruction.

After a subroutine has been executed, the calling program must resume execution, continuing immediately
after the instruction that called the subroutine. The subroutine is said to return to the program that called
it by executing a Return instruction. Since the subroutine may be called from different places in a calling
program, provision must be made for returning to the appropriate location. The location where the calling
program resumes execution is the location pointed to by the updated PC while the Call instruction is being
executed. Hence, the contents of the PC must be saved by the Call instruction to enable correct return to
the calling program.
The way in which a computer makes it possible to call and return from subroutines is referred to as its
subroutine linkage method. The simplest subroutine linkage method is to save the return address in a
specific location, which may be a register dedicated to this function. Such a register is called the link
register. When the subroutine completes its task, the Return instruction returns to the calling program by
branching indirectly through the link register.
The Call instruction is just a special branch instruction that performs the following operations:
• Store the contents of the PC in the link register
• Branch to the target address specified by the instruction

The Return instruction is a special branch instruction that performs the operation:
Branch to the address contained in the link register.

Q. A cpu , which address the data through its 6 registers in one of the 12 different modes , is to be
designed to support 10 athematic inst. 15 logic inst. ,24 data moving inst. , 6 branch inst. And 5 control
type inst. Of these inst. Respectively 20% ,60%,50%,&60% are wither single operand or no- operand inst.
And rest are of double operand inst. Word?
8086 Processor: