Chapter Five

Basic Computer Organization and Design

Computer Organization & Architecture

(SEng 3022)
Outline
Instructional Code
Computer Registers
Computer Instructions
Timing and Control
Memory Reference Instructions
Design of Basic Computer
Design of accumulator Logic

2
 Introduction
Levels of Programming Languages
1) Machine Language
Consists of individual instructions that will be executed by the CPU
one at a time
2) Assembly Language (Low Level Language)
Designed for a specific family of processors (different processor
groups/family has different Assembly Language)
Consists of symbolic instructions directly related to machine
language instructions one-for-one and are assembled into machine
language.
3) High Level Languages
e.g. : C, C++ and V.basic
 Designed to eliminate the technicalities of a particular computer.
Statements compiled in a high level language typically generate
many low-level instructions.
3
 What is control Unit?
A Control Unit or CU is circuitry that directs operations within a
computer's processor.
 It lets the computer's logic unit, memory, as well as
both input and output devices know how to respond to instructions
received from a program.
Examples of devices that utilize control units
include CPUs and GPUs.
A control unit works by receiving input information that it converts
into control signals, which are then sent to the central processor.
The computer's processor then tells the attached hardware what
operations to carry out.
The functions that a control unit performs are dependent on the
type of CPU, due to the variance of architecture between different
4 manufacturers.
 Cont.…
The following diagram illustrates how instructions from a
program are processed

5
Instructional Code

 A program is a set of instructions that specify the operations, operand,

and the sequence (control).
 An instruction is a binary code that specifies a sequence of
microoperations.
 Instruction codes together with data are stored in memory (=Stored
Program Concept)
 The computer reads each instruction from memory and places it in a
control register.
 The control then interprets the binary code of the instruction and
proceeds to execute it by issuing a sequence of micro-operations.
 Each instruction has multiple stages (fetch, decode, ..., interrupts).
• Each one of these involves one or more µ-operations;

6
Instructional Code
 An instruction code is a group of bits that instruct the
computer to perform a specific operation.
15 12 1 0
1
 It usually divided into two parts Opcode Address

Instruction Format

Operation code:
 It is the most basic part of the Instruction code.
 The operation code of an instruction is a group of bits that
define such operations as add, subtract, multiply, shift and
complement.
 The number of bits required for the op code of an instruction
depends on the total number of operations available in the
computer.
 The operation code must consist of at least n bits for a givers 2 n

7
(or less) distinct operations.
Cont.…
 The simplest way to organize a computer is to have one processor
register and an instruction code format with two parts.
 The first part specifies the operation to be performed and the
second specifies an address.
 Instruction code format with two parts : Op. Code + Address
 Op. Code: specify 16 possible operations (4 bit)
 Address: specify the address of an operand (12 bit)
 Store each instruction code(program) and operand (data) in 16-
bit memory word
Accumulator register: Computers that have a single-processor
register usually assign to it the name accumulator and label it AC.
The operation is performed with the memory operand and the
content of AC.

8
Instructional Code

 It’s an
ADD
Memory operation

Op code
Control
110010?????????? Unit

Fig 3.1 Read instruction

from memory

9
Instructional Code

15 12 1 0 Memory
Opcode
1
Address 15
4096x16 0

Instruction Format
Instructions
15 0
(program)
Binary Operand

Operands
(data)

15 0

Processor register
(Accumulator AC)

10 Fig 3.2 Read operands from memory

 Addressing mode
how are the bits of an instruction organized to define the operand addresses and
operation of that instruction.
The most common addressing techniques are:
❍ Immediate
❍ Direct
❍ Indirect
❍ Register
❍ Register Indirect
❍ Displacement
❍ Stack
 To explain the addressing modes, we use the following notation:

A = contents of an address field in the instruction that refers to a memory

 Effective address: Address of the operand in a computation-type instruction or the
R = contents of an address field in the instruction that refers to a registertarget address in a
branch-type instruction is called effective address
EA = actual (effective) address of the location containing the referenced operand
(X) = contents of location X

11
 Immediate addressing
The simplest form of addressing is immediate addressing, in
which the operand is actually present in the instruction:
OPERAND = A
This mode can be used to define and use constants or set initial
values of variables.
The advantage of immediate addressing is that no memory
reference other than the instruction fetch is required to obtain
the operand.
The disadvantage is that the size of the number is restricted to
the size of the address field, which, in most instruction sets, is
small compared with the world length.

12 Fig 3.3 immediate addressing

 Direct addressing
A very simple form of addressing is direct addressing, in which
the address field contains the effective address of the operand:
EA = A
It requires only one memory reference and no special
calculation

Fig 3.4 direct addressing

13
 Indirect addressing
With direct addressing, the length of the address field is
usually less than the word length, thus limiting the address
range.
One solution is to have the address field refer to the address
of a word in memory, which in turn contains a full-length
address of the operand. This is know as indirect addressing:

EA = (A)

14 Fig 3.5 Indirect addressing

 Register addressing
 Register addressing is similar to direct addressing. The only
difference is that the address field refers to a register rather than a
main memory address:
EA = R
 The advantages of register addressing are that only a small address
field is needed in the instruction and no memory reference is
required.
 The disadvantage of register addressing is that the address space is
very limited.

15 Fig 3.6 Register addressing

 Register indirect addressing
Register indirect addressing is similar to indirect addressing,
except that the address field refers to a register instead of a
memory location.
It requires only one memory reference and no special calculation.
EA = (R)
Register indirect addressing uses one less memory reference than
indirect addressing.
Because, the first information is available in a register which is
nothing but a memory address.
From that memory location, we use to get the data or information.
In general, register access is much more faster than the memory
access.

16
 Contd..

Fig 3.7 Register indirect addressing

Reading assignment
Displacement Addressing:
Stack Addressing:
17
Instructional Code

Instruction Format  Effective

15 14 12 11 0
I Opcode Address address
Direct Address Indirect address

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand
1350 Operand

+ +

AC AC

18
Fig 3.8 different addressing mode
COMPUTER REGISTERS
Computer instructions are normally stored in consecutive

memory locations and executed sequentially one at a time

The control reads an instruction from a specific address in

memory and executes it, and so on

This type of sequencing needs a counter to calculate the

address of the next instruction after execution of the current

instruction is completed.
The computer needs processor registers for manipulating

data and a register for holding a memory address.

19
COMPUTER REGISTERS
11 0
Register PC
11 0
AR Memory

15 0 4096 x 16
IR
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character

20
COMPUTER REGISTERS
Program Counter(PC) :
 hold the address of the next instruction to be read from
memory after the current instruction is executed
 Instruction words are read and executed in sequence unless
a branch instruction is encountered
 A branch instruction calls for a transfer to a nonconsecutive
instruction in the program
 The address part of a branch instruction is transferred to PC
to become the address of the next instruction
 To read instruction, memory read cycle is initiated, and PC
is incremented by one(next instruction fetch)

21
Cont.…
.

Fig 3.9
22
Cont.…
Common Bus System:
The basic computer has eight registers, a memory unit, and
a control unit. Paths must be provided to transfer information
from one register to another and between memory and
registers.
A more efficient scheme for transferring information in a
system with many registers is to use a common bus.
The outputs of seven registers and memory are connected
to the common bus.
The specific output that is selected for the bus lines at any
given time is determined from the binary value of the
selection variables S1, S2 and S3.
23
Cont.…
Common Bus System:
The particular register whose LD (load) input is enabled
receives the data from the bus during the next clock pulse
transition.
 The memory receives the contents of the bus when its write
Input is activated.
When the contents of AR of PC are applied to the 16-bit
common bus the four most significant bits are set to 0’s
When AR or PC receives information from the bus, only the
12 least significant bits are transferred into the registers.
OUTR can only receive information from the bus.
It receives a character from AC and delivers it to an output
device.
24
COMPUTER REGISTERS
Common Bus System:
The increment operation is achieved by enabling the count
input of the counter.
By using a single register for the address, we eliminate the
need for an address bus that would have been needed otherwise.
The 16 inputs of AC come from an adder and logic circuit.
This circuit has three sets of inputs.
The content of any register can be applied onto the bus and an
operation can be performed in the adder and logic circuit during
the same clock cycle.
 The clock transition at the end of the cycle transfers the
content of the bus into the designated destination register and
the output of the adder and logic circuit into AC.
25
COMPUTER REGISTERS
Common Bus System:
By using a single register for the address, we eliminate the
need for an address bus that would have been needed
otherwise.

The 16 inputs of AC come from an adder and logic circuit.

This circuit has three sets of inputs.

The content of any register can be applied onto the bus and
an operation can be performed in the adder and logic circuit
during the same clock cycle.

26
Computer Instructions
The Basic Computer has three instruction code formats
each format has 16 bits.
The type of instruction is recognized by the computer
control from the four bits in positions 12 through 15 of the
instruction

27
Computer Instructions
Note that the bit in position 15 of the instruction code
designated by the symbol I but is not used as a mode bit when
the operation code is equal to 111.
Register-reference instructions use 16 bits to specify an
operation.
The leftmost, four bits are always 0111, which is equivalent
to hexadecimal 7.
The other three hexadecimal digits give the binary equivalent
of the remaining 12 bits.
The input-output instructions also use all 16 bits to specify an
operation.
The last four bits are always 1111, equivalent to hexadecimal
F.
28
Computer Instructions

Instruction Set Completeness: If the computer includes a

sufficient number of instructions in each of the following
categories.
Arithmetic, Logical, and shift instructions: CMA, INC,

Moving information to and from memory and processor

register AC : STA, LDA

Program control instructions together with instructions that

check status condition: BUN, BSA, ISZ

Input/output instructions: INP, OUT
29
Computer Instructions

Fig 3.10 computer instructions

30
 BASIC COMPUTER
INSTRUCTIONS Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
31 IOF F040 Interrupt off
 Instruction Fetch Execute Cycle
Once a computer has been powered on it performs a
continuous cycle of the following:
a. Fetch: gets an instruction from memory
b. Decode: decides what the instruction
means
c. Execute: performs the instruction

Figure 3.11: Basic Instruction

Fetch Execute Cycle

32
 Fetch Cycle
The fetch cycle begins with retrieving the address stored in the
Program Counter (PC).
The address stored in the PC is some valid address in the
memory holding the instruction to be executed.
 (In case this address does not exist we would end up causing
an interrupt or exception).
The Central Processing Unit completes this step by fetching
the instruction stored at this address from the memory and
transferring this instruction to a special register – Instruction
Register (IR) to hold the instruction to be executed.
The program counter is incremented to point to the next
address from which the new instruction is to be fetched.

33
 Step before execution of an instruction
• Fetch the instruction – directly from memory or through a
cache
• An instruction fetch using memory address register (MAR) and
the content of the instructions in memory transfer to instruction
register (IR)

34 Fig 3.12 Fetch the instruction

 Contd..
Assume instruction at a memory address M[I], where I is the
address of the instruction I
• Step 1 in Fetch process─
MAR←PC
Address_Bus←MAR
• Step 2 in Fetch process─
RD: Data_Bus← M[I]
IR← Data_Bus

35
 Decode Cycle
The decode cycle is used for interpreting the instruction that was fetched in the
Fetch Cycle.
The operands are retrieved from the addresses if it is needed.

Execute Cycle
• This cycle as the name suggests , simply executes the instruction that was fetched
and decoded.
Interrupt Cycle
• An interrupt can occur any time during the program execution.
• Whenever it is caused, a series of events take place so that the instruction fetch
execute cycle can again resume after the OS calls the routine to handle the
interrupt.

36
 Instruction Formats
• Format = Layout of bits in an instruction
• Includes opcode and address.
• Usually more than one instruction format in an instruction set
The operation of CPU is determined by the instructions it executes
(machine or computer instructions)
CPU’s instruction set – the collection of different instructions that
CPU can execute.
Each instruction must contain the information required by CPU for
execution :-
1. Operation code (opcode) -- specifies the operation to be performed
(e.g.: ADD, I/O) do this
2. Source operand reference -- the operation may involve one or more
source operands (input for the operation)  to this
3. Result operand reference -- the operation may produce a result  put
the answer here
4. Next instruction reference -- to tell the CPU where to fetch the next
instruction after the execution of this instruction is complete  do this
when you have done that
37
 Contd...

Operands (source & result) can be in one of the 3 areas:-

Main or Virtual Memory
CPU register
I/O device
It is not efficient to put all the information required by CPU in a machine
instruction
Each instruction is represented by sequence of bits & is divided into 2 fields;
opcode & address

Processing become faster if all information required by CPU in one instruction or one
instruction format

38
 Contd…
Opcodes are represented by abbreviations, called mnemonics,
that indicate the operation. Common examples:
ADD Add
SUB Subtract
DIV Divide
LOAD Load data from memory
STOR Store data to memory

39
 Instruction format

40
 Contd..

41
TIMING AND CONTROL
A master clock generator controls the timing for all
registers in the basic computer.
The clock pulses do not change the state of a register unless
the register is enabled by a control signal.
 The control signals are generated in the control unit and
provide control inputs for the multiplexers in the common
bus, control inputs in processor registers, and micro-
operations for the accumulator.
There are two major types of control organization:
hardwired control and micro programmed control.

42
TIMING AND CONTROL
hardwired organization:
the control logic is implemented with gates, flip-flops,
decoders, and other digital circuits.
 advantage: it can be optimized to produce a fast mode of
operation.
requires changes in the wiring among the various
components if the design has to be modified or changed.
micro programmed organization:
the control information is stored in a control memory. The
control memory is programmed to initiate the required
sequence of micro operations.
any required changes or modifications can be done by
updating the micro-program in control memory.
43
TIMING AND CONTROL
Instruction register (IR)
15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I
D7 Control
logic
gates
T15
T0

15 14 . . . . 2 1 0
4 x 16
Sequence decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

Fig.3.13 timing and control

44
MEMORY REFERENCE INSTRUCTIONS
The actual execution of the instruction in the bus system
will require a sequence of microoperations.
This is because data stored in memory cannot be processed
directly.
The data must be read from memory to a register where
they can be operated on with logic circuits.

45
MEMORY REFERENCE INSTRUCTIONS
1. AND to AC:
performs the AND logic operation on pairs of bits in AC
and the memory word specified by the effective address. The
result of the operation is transferred to AC.
The micro operations that execute this instruction are:
D0T4 : DR ← M[AR]
D0T5: AC ← AC Λ DR, SC ← 0
this instruction uses the operation decoder D0 since this
output of the decoder is active when the instruction has an
AND operation whose binary code value is 000

46
MEMORY REFERENCE INSTRUCTIONS
2. ADD to AC:
The instruction adds the content of the memory word
specified by the effective address to the value of AC.
The sum is transferred into AC and the output carry Cout is
transferred to the E (extended accumulator) flip-flop.
The micro operations needed to execute this instruction are
D1T4: DR ← M[AR]
D1T5: AC ← AC + DR, E ← Cout, SC ← 0

47
MEMORY REFERENCE INSTRUCTIONS
3. LDA : Load to AC:
This instruction transfers the memory word specified by the
effective address to AC.
 The microoperations needed to execute this instruction are
D2T4: DR ← M[AR]
D2T5: AC ← DR, SC ← 0

it is necessary to read the memory word into DR first and

then transfer the content of DR into AC.
The reason for not connecting the bus to the inputs of AC is
the delay encountered in the adder and logic circuit.

48
MEMORY REFERENCE INSTRUCTIONS
4. STA : Store AC:
This instruction stores the content of AC into the memory
word specified by the effective address.
Since the output of AC is applied to the bus and the data
input of memory is connected to the bus, we can execute this
instruction with one microoperation:
D3T4: M[AR] ← AC, SC ← 0

49
MEMORY REFERENCE INSTRUCTIONS
5. BUN : Branch Unconditionally:
This instruction transfers the program to the instruction
specified by the effective address.
PC is incremented at time T1 to prepare it for the address
of the next instruction in the program sequence.
The BUN instruction allows the programmer to specify an
instruction out of sequence and we say that the program
branches (or jumps) unconditionally.
The instruction is executed with one microoperation:
D4T4: PC ← AR, SC ← 0

50
MEMORY REFERENCE INSTRUCTIONS
6.BSA : Branch and Save Return Address:
This instruction is useful for branching to a portion of the
program called a subroutine or procedure.
The BSA instruction performs the function usually referred
to as a subroutine call.
To use the memory and the bus properly, the BSA
instruction must be executed with a sequence of two
microoperations:
D5T4: M[AR] ← PC, PC ← AR +1
D5T5: PC ← AR, SC ← 0

51
MEMORY REFERENCE INSTRUCTIONS
7.ISZ : Increment and Skip if Zero:
This instruction increments the word specified by the
effective address, and if the incremented value is equal to 0, PC
is incremented by 1.
Since it is not possible to increment a word inside the
memory, it is necessary to read the word into DR, increment
DR, and store the word back into memory.
This is done with the following sequence of microoperations:
D6T4: DR ← M[AR]
D6T5: DR ← DR + 1
D6T6 : M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC
←0

52
DESIGN OF BASIC COMPUTER
 a basic computer have the following
1. A memory unit: 4096 x 16.
2. Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR,
and SC
3. Flip-Flops (Status): I, S, E, R, IEN, FGI, and
FGO
4. Decoders:
1. a 3x8 Opcode decoder
2. a 4x16 timing decoder
5. Common bus: 16 bits
6. Control logic gates
7. Adder and Logic circuit: Connected to AC

53
DESIGN OF BASIC COMPUTER
Input-Output Instructions

D7IT3 = p
IR(i) = Bi, i = 6, …, 11

INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC

OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off

54 Computer Organization
DESIGN OF BASIC COMPUTER

55
DESIGN OF BASIC COMPUTER
start
SC  0, IEN  0, R  0

(Instruction Cycle) =0 =1 (Interrupt Cycle)

R
R’T0 RT0
AR  PC AR  0, TR  PC
R’T1 RT1
IR  M[AR], PC  PC + 1 M[AR]  TR, PC  0
R’T2 RT2
AR  IR(0~11), I  IR(15) PC  PC + 1, IEN  0
D0...D7  Decode IR(12 ~ 14) R  0, SC  0

(Register or I/O) =1 =0 (Memory Ref)

D7

(I/O) =1 =0 (Register) (Indir) =1 =0 (Dir)

I I

D7IT3 D 7I’T3 D7’IT3 D 7’I’T3

Execute Execute AR  M[AR] Idle
I/O RR
Instruction Instruction
Execute MR D7’T4
Instruction

56
DESIGN OF BASIC COMPUTER
CONTROL LOGIC GATES:
 The output of the control logic circuits are:

Control of register and Memory:

The registers of the computers connected to a common bus
system.
The control inputs of the registers are LD (Load), INR
(increment), and CLR (clear).
Control inputs of Memory are: Read, Write.
57
DESIGN OF ACCUMULATOR LOGIC
The adder and logic circuit has three sets of inputs. One set
of 16 inputs comes from the outputs of AC.
Another set of 16 inputs comes from the data register DR.
A third set of eight inputs comes from the input register
INPR.
The outputs of the adder and logic circuit provide the data
inputs for the register.
In addition it is necessary to include logic gates for
controlling the LD, INR, and CLR in the register and for
controlling the operation of the adder and logic circuit.

58
 LOGIC
Circuits associated with AC 16
Adder and
16 16 16
From DR logic AC

8 circuit To bus
From INPR

LD INR CLR Clock

Control
gates

All the statements that change the content of AC

D0T5: AC  AC  DR AND with DR
D1T5: AC  AC + DR Add with DR
D2T5: AC  DR Transfer from DR
pB11: AC(0-7)  INPR Transfer from INPR
rB9: AC  AC’ Complement
rB7 : AC  shr AC, AC(15)  E Shift right
rB6 : AC  shl AC, AC(0)  E Shift left
rB11 : AC  0 Clear
59 cpe
rB5252:
: Computer
AC  ACOrganization
+1 Increment
DESIGN OF ACCUMULATOR LOGIC
Control of AC register: The gate structure that controls the
LD,INR, and CLR inputs of AC is shown below figure.

60
DESIGN OF ACCUMULATOR LOGIC
Adder and Logic circuit:
 The adder and logic circuit can be subdivided into 16
stages, with each stage corresponding to one bit of AC.

61
 I/O and interrupts
Baic I/O are:

62
 Accessing I/O Devices

63
 Contd..
 Most modern computers use single bus arrangement for connecting I/O

devices to CPU & Memory

 The bus enables all the devices connected to it to exchange information

 Bus consists of 3 set of lines: Address, Data, Control

 Processor places a particular address (unique for an I/O Dev.) on address lines

 Device which recognizes this address responds to the commands issued on

the Control lines

 Processor requests for either Read / Write

• The data will be placed on Data lines

64
 Contd..

65