2016 International Siberian Conference on Control and Communications (SIBCON)
A behavioral model of integer-N PLL frequency
synthesizer for reference spur level simulation
Denis I. Sotskov, Vadim V. Elesin
National Research Nuclear University MEPhI (Moscow Engineering Physics Institute)
Moscow, Russia
disot@spels.ru
Abstract—The major effects defining reference spurs level of
the integer-N phase-locked loop (PLL) frequency synthesizer are
described. The behavioral model of the PLL for evaluating
reference spurs level has been developed in CAD Keysight ADS.
The model takes into account time delay between output signals
of the phase-frequency detector (PFD) and delay in the PFD reset
path; charge pump current mismatch; charge pump current
leakage; charge pump switching time mismatch. The design
issues of SOI CMOS PLL functional blocks (FB) based on the
proposed behavioral model, have been provided.
Keywords—behavioral model, frequency synthesizer, PLL,
reference spur, phase-frequency detector, charge pump
I. INTRODUCTION
Phase-locked loop frequency synthesizers (PLL-FS) are
used to generate a stable signal of a given frequency. PLL is a
key functional block of transceiver modules; it functions as an
local oscillator that generates the carrier [1]. Today, monolithic
PLL are manufactured with < 0.35 μm CMOS and BiCMOS
process and used in a variety of applications including
integrated transceivers for telecommunications, navigation,
RFID, etc. [2-5].
The main characteristics of PLL-FS include phase noise
(which determines the carrier frequency stability), the
minimum frequency step, lock time, phase margin, and spurs
level in the output spectrum. PLL-FS is a complex analog-
digital system combining both radio-frequency analog FBs,
low-frequency analog units and digital elements, which makes
optimizing of its parameters at the stage of schematic design
using time domain methods of analysis a resource-intensive
process [6]. Modern advances in end-to-end CAD technology
has made it possible to resolve this problem using integrated
behavioral models (BM) allowing to verify the PLL-FS
architecture and establish requirements for the parameters of
individual FBs at the initial design phase. This approach has
helped to significantly reduce the time and number of iterations
of the transistor-level simulation [6].
Behavioral models for PLL-FS described in the modern
scientific and technical literature [7, 8] mostly apply to
evaluation of such integral parameters as phase margin, lock
time and phase noise at a fixed offset frequency. Meanwhile,
today's systems for telecommunications, broadband data
transmission, RFID, etc., have intensified their requirements
This work was partially supported in accordance with agreement
between Ministry of Education and Science of the Russian Federation and
National Research Nuclear University MEPhI as of November 24, 2014 ʋ
14.578.21.0075 (unique identifier of applied research: RFMEFI57814X0075).
978-1-4673-8383-7/16/$31.00 ©2016 IEEE
for the output spectrum, which demands control of spurs in the
PLL-FS output spectrum at the design stage. The existing
behavioral models used to calculate the spurs have been
developed for general-purpose mathematical modeling
packages (such as MATLAB/Simulink); however, those
methods offer insufficient accuracy and low time efficiency
[9]; the authors are unaware of whether the behavioral models
have already been developed for end-to-end CAD.
This circumstance makes it a crucial task to develop a
behavioral model to estimate spurs in the PLL-FS output for
end-to-end CAD for IC design.
II. ANALYSIS OF THE EFFECTS DETERMINING SPURS IN THE
PLL-FS OUTPUT SPECTRUM
Pre-assessment of spurs for PLL-FS is quite a complex
process due to several effects involved in FBs of the phase
frequency detector (PFD) and charge pump, including [10]:
- time delay between the PFD output signals;
- delay in the PFD reset path;
- charge pump current mismatch;
- charge pump current leakage;
- charge pump switching time mismatch, see a simplified
block diagram in Fig. 1.
A. Phase Frequency Detector
Time delay between the UP and DN PFD signals (tdel) is
due to a delay in the inverter (INV) connected to the output Q
of the PFD's D-trigger. The time delay in the PFD's reset path
(RST) (tR) is determined by the total delay in the NOR gate and
in the delay element (IJ), compensating the "dead zone" effect.
[11].
B. Charge Pump
The mismatch (įI) between charge pump source current
(Isource) and sink current (Isink) is due to several reasons. First of
all, it results from the channel length modulation due to the
output voltage (UOUT) and process variations [12].
įI is usually a percentage value calculated from the
expression (1) [13]:
Isource  Isink
EI  ¸100 % (1)
ICP ,
 2016 International Siberian Conference on Control and Communications (SIBCON)

where ICP is the average value of charge pump output current, 30 ps, tR = 3 ns, įI = 3 %, ICP = 350 μA, Ileak = 2 nA, trIsource =
defined as an arithmetic average of |Isource| and |Isink|. 15 ps, trIsink = 10 ps, tfIsource = 30 ps, tfIsink = 20 ps, is shown in
Fig. 3.
Leakage current (Ileak) depends on the charge pump output
current at simultaneously open transistor switches MP and MN.
In modern PLL-FS ICs, the value of Ileak is several nA or less
[14].
Charge pump switching time mismatch is determined by
the time of rise (trIsource, trIsink)/fall (tfIsource, tfIsink) of the current
impulses |Isource| and |Isink| at the charge pump output when the
MP and MN transistor switches are closed/open, respectively.
The following inequalities are commonly true (2):
Fig. 2. High-level design for the behavioral model for integer-N PLL-FS to
estimate the spurs level in the output spectrum.
|trIsource - trIsink|  0, |tfIsource - tfIsink|  0. (2)

Fig. 3. PLL-FS output spectrum.

Numerical simulation has shown that, for the given

Fig. 1. Simplified block diagram of PFD with a charge pump. example the greatest contribution to the spurs level in the
output is from Ileak of the charge pump, which is due to a
III. BEHAVIORAL MODEL OF PLL-FS relatively low comparison frequency of the PFD. The other
effects in this case are insignificant.
To assess the spurs level in the integer-N PLL-FS output, a
behavioral model for the Advanced Design System (ADS) A common method to suppress the spur is to use a higher-
CAD based on a standard library for the model of a voltage order low-pass filter [14]. Dependence of the level of the spur
controlled oscillator (VCO) with a built-in N-frequency divider PS(ƒS) at the offset frequency ƒS = ƒPFD = 200 kHz on the value
in the feedback loop, has been built. PFD and charge pump of charge pump's Ileak for a LPF of the 2nd and 3rd order with
taking into account all the above-mentioned effects, have been the loop bandwidth of 10 kHz is shown in Fig. 4. As seen from
implemented as a program code written in Verilog-A. The the calculated dependences, the LPF of the 3rd order allows to
high-level design of the developed behavioral model for PLL- decrease the spur level to 5 dB compared to an LPF of the 2nd
FS to analysis in time domain is shown in Fig. 2. order.
A downside of the integer-N PLL-FS is lengthy hopping to
a new frequency, which may take a fraction of a millisecond or
more [15] and hence demand measures to expedite modeling at
the behavioral level.
Reduced lock time for the VCO's output frequency has
been achieved by inclusion of a library-based switch model
(S1) into the PLL-FS behavioral model. PFD input signals are
sawtooth pulses with a linear voltage growth, which increases
the accuracy of estimating frequency or phase mismatch for the
PFD input.
The output spectrum has been calculated using a built-in
Fourier transform (fs) and the Blackman-Harris window
function. An example of the integer-N PLL-FS output obtained
using the developed model for a 2nd order low-pass filter
Fig. 4. Dependence of the spur level PS (ƒS) on the charge pump leakage
(LPF), comparison frequency ƒPFD = 200 kHz, loop bandwidth
FC = 10 kHz, VCO's tuning sensitivity KVCO = 50 MHz/V, tdel = current Ileak.
 2016 International Siberian Conference on Control and Communications (SIBCON)

IV. AN INTEGER-N PLL-FS DESIGN IN 0.18 μM SOI CMOS

TECHNOLOGY
PLL-FS behavioral model has been successfully tested in
establishing of requirements for the parameters of FBs of an
integer-N PLL-FS with a range of input frequencies of up to
3 GHz designed in 0.18 μm SOI CMOS process [16-18].
As a result, schematics and layouts have been designed for
the following FBs of integer-N PLL-FS:
- differential cross-coupled LC VCO;
- dual-modulus (divide-by-16/18) prescaler based on the
current mode logic;
- 8-bit counters with a fixed (R = 50) and variable (N =
240... 250) frequency division ratios;
- PFD based on NAND gates;
- analog lock detect requiring an external filtering circuit;
- charge pump based on a multi-stage current mirror [19]
and an output stage based on current steering switch; Fig. 6. Simulation and testing results for the developed VCO: dependencies of
- serial interface based on a 4-bit shift register and 4-bit the output frequency (Fout) on the tuning voltage (Vtune).
storage register.
The photomicrograph of the PLL chip layout is provided in
Test results for VCO chips (see the photomicrograph in Fig. 7. The PLL contains PFD, counters with fixed and variable
Fig. 5) have confirmed frequency tuning in the range of division ratios, analog lock detect, charge pump and buffer
1.58...2.02 GHz at a tuning voltage of 0...1.8 V, output power amplifiers. The size of the chip is 1.4×1.4 mm2. Estimated time
of 0 dBm, phase noise of -90 dBc/Hz at 100 kHz frequency diagrams of the PLL in “closed-loop” mode shown in Fig. 8.
offset and power consumption of 41 mW. According to the numerical simulation, the PFD and charge
pump FBs of the PLL has the following parameters in charge
pump output voltage range from 0.7 V to 2.5 V: tR = 4 nsec, ICP
= 360 uA, |δI| < 1.2 %, |Ileak| < 5 nA.

Fig. 5. The photomicrograph of a test chip 0.18 μm SOI CMOS VCO, chip size
1.00×0.95 mm2.

Comparing the oscillation frequency of the VCO samples

on tuning voltage obtained from experiments and CAD-based
calculations are shown in Fig. 6.
A test chip of a dual-modulus (divide-by-16/18) prescaler,
has the input frequency range of 0.1...4.0 GHz, sensitivity of no Fig. 7. The photomicrograph of the 0.18 μm SOI CMOS PLL layout.
worse than -15 dBm at a power consumption of 60 mW; chip
size with contact pads is 1.35×0.85 mm2.
 2016 International Siberian Conference on Control and Communications (SIBCON)

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The behavioral model of PLL-FS has been successfully
tested in establishing requirements for the parameters of a set
of functional blocks of an integer-N PLL-FS with a range of
input frequencies of up to 3 GHz designed in 0.18 μm SOI
CMOS process. The PLL-FS functional blocks have been
designed to develop a variety of radiation tolerant RF and MW
frequency synthesizers and transceivers ICs.
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