IEEE INDICON 2015 1570178631

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Design of FinFET based Frequency Synthesizer
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6   Sobhana Tayenjam, S. R. Sriram, B. Bindu
7   School of Electronics Engineering
8   VIT University, Chennai Campus
9   Chennai, India
10   Email: sobhanatayenjam009@gmail.com, sriram.sr2014phd1149@vit.ac.in, bindu.boby@vit.ac.in
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12   Abstract— Miniaturization in the geometry of CMOS applied to reduce the VCO swing to improve the phase noise
13   technology improves IC performance but beyond certain limit, [5]. Frequency presetting technique is used to reduce the
14   scaling of CMOS may be quite challenging due to various short locking time in [6]. A multichannel based frequency
channel effects. To overcome such issues double gate (DG) synthesizer is developed for the ultra low power consumption
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CMOS or FinFET are used because of its ability to minimize
16   of 204 μW using CMOS 180 nm technology [7]. A frequency
short channel effects. This paper presents the designing of
17   frequency synthesizer using phase locked loop (PLL) based on synthesizer with low power consumption has been developed
18   FinFET technology. Here we have used shorted gate FinFET for using 130 nm CMOS technology node is developed in [8]. To
19   designing the circuits. A frequency synthesizer capable of improve the phase noise performance of the PLL, a hybrid
20   synthesizing an input clock frequency of 500 MHz to an output phase/current-mode phase interpolator using 65 nm CMOS
21   frequency of 1 GHz is implemented using FinFET with a lock in technology is presented in [9]. A direct-digital frequency
time of 254 ns. The circuits are implemented on Cadence synthesizer has been developed [10] using 55 nm CMOS
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®Virtuoso using 32nm FinFET technology and 1V power supply. technology with reduced power consumption and hardware
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24   complexity. Also PLL based frequency synthesizer employing
Keywords—FinFET, frequency synthesizer, phase frequency CMOS transistors and single-electron devices (SEDs) are
25   detector(PFD), phase locked loop (PLL) , voltage control oscillator
26   (VCO).
reported [11]. There is no reported work on the design of PLL
27   based frequency synthesizer using FinFET in literature so far.
28   I. INTRODUCTION In this paper, a PLL based frequency synthesizer is
29   implemented using FinFET technology.
30   With the ever growing need for low power, high speed and
31   more packing density of integrated chips (ICs), the scaling of II. FINFET BASED FREQUENCY SYNTHESIZER
32   devices became inevitable. However, the scaling of CMOS
33   technology reaches its limit due to the short channel effects The frequency synthesizer proposed in this paper is
34   [1]. Multi-gate MOSFET or FinFET happens to be better designed with FinFET technology. The BSIM-CMG FET
35   substitutes for CMOS for scaling beyond sub-micron regime Verilog-A model [12] is integrated with Cadence Virtuoso
because of their high immunity to short channel effects. Some EDA tool [13] for FinFET transistors with gate length of 30
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of the main advantages of FinFET include higher Ion/Ioff ratio nm. The device used in this simulation is FinFET –on-SOI
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and low value of intrinsic gate capacitances [2]. All the type with tri-gate structure and all the gates are connected to
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circuits designed in this paper are implemented using shorted the same bias. The designed fin thickness and fin height are
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gate mode of FinFET where in the gates are shorted or tied 15 nm and 30 nm respectively. Fin pitch is 80 nm;
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41   together [3]. source/drain doping is 2  1020 / cm3 and channel (body)
42   doping is 1016 / cm3 .
The main function of a frequency synthesizer is the ability
43   to generate a new synthesized frequency using a single input
44   frequency which is stable in nature. It is very common for a
45   frequency synthesizer to use the PLL because of its
46   advantages like minimum power consumption, reduction in
47   the architectural complexity. Thus, many communication
48   systems require the use frequency synthesizer for the
49   generation of different range of frequencies. Some of these
50   applications includes radios, mobile phones other wireless
51   devices [4].
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53   Many authors have focused on various techniques for the
54   efficient design of frequency synthesizer. The variety of low
55   power PLL based frequency synthesizer using CMOS has
56   been developed for the low power consumption and low phase
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noise [5-10]. The current reusing technique is used to reduce Fig. 1. Block diagram of PLL as frequency synthesizer
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the power consumption and forward body bias technique is
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978-1-4673-6540-6/15/$31.00 ©2015 IEEE

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 The block diagram of a PLL based frequency synthesizer
shown in Fig. 1. A PLL circuit comprises of a phase frequency
detector (PFD), a charge pump, a loop filter and a VCO. The
basic purpose of a PLL is to generate a clock signal which is
in phase with respect to the reference clock signal [4]. The
frequency divider is placed in between the output and the
feedback input to generate multiple frequencies.
A. Phase Frequency Detector
The basic functionality of PFD is the detection of phase or
frequency differences between the reference clock and output
clock. Here, PFD [4] is used to detect the phase error between
the input reference clock and output clock from the frequency
divider circuit. The PFD of the proposed frequency
synthesizer is shown in Fig. 2.
Fig. 2. Schematic of PFD using modified D flip-flop
Fig. 3. PFD simulation waveform
The PFD is a modified form of the conventional PFD using
two D flip-flop and an AND gate. The circuits for generating
the UP and DOWN signal is same and the way how the
reference and output clock is given will determine the PFD UP
and DOWN circuit. The place where the reference and output
clock given in PFD UP circuit is interchanged and given in the
PFD DOWN circuit. If the output clock lags the reference
2
clock, then UP pulses are generated and if the output clock
leads the reference clock the DOWN pulses are generated. The
UP and DOWN pulses are fed to the Charge pump for the
generation of error signal. The generation of UP signal from
the lagging output clock is shown in Fig. 3 where pulse width
of the UP signal is same as the amount of phase error between
the reference clock and output clock.
B. Charge Pump
The PFD is followed by a charge pump circuit which is
used to integrate the two output signals of the PFD i.e. UP and
DOWN into a single current signal to drive the loop filter [4].
Fig. 4. Charge Pump
The simple charge pump circuit used in this work is shown
in Fig. 4. The simple current source circuit containing either P-
FinFET or N-FinFET is used in the charge pump. When there
is occurrence of pulses in the UP signal, FinFET F1 is turned
ON which connects the supply voltage VDD to the loop filter
for charging the capacitors and if there is occurrence of pulses
in the DOWN signal, then FinFET F2 is turned ON which
connects the loop filter to ground to discharge the capacitor in
the loop filter.
C. Loop Filter
The bandwidth selection of a PLL mainly depends upon the
design of the loop filter used. A PLL loop filter can either be a
first order system or a second order system. The second order
loop filter is employed mostly because of its efficiency
compared to a first order system in terms of noise suppression
[4]. The main function a charge pump is to generate a control
voltage from the phase error generated by the PFD. This
controlled voltage signal is used to tune the VCO. In this paper
second order system loop filter is used in the PLL based
frequency synthesizer.
D. Voltage Controlled Oscillator
The frequency of VCO depends on the error signal
generated by the PFD. The VCO employed here is a current
starved VCO with 5 inverter stages. Fig. 5 shows the circuit
diagram of a current starved VCO using FinFET. The UP
signal drives the loop filter and increases the control voltage
of the VCO. The increase of control voltage increases the
frequency of oscillation. The DOWN signal decreases the
control voltage consequently decreasing the frequency of equal to1V. CT is the total capacitances on the drain of the two
oscillation. The occurrence of pulses in the UP and DOWN FinFETs of the 1st inverter stage and is given by
signal from the PFD depends on the lagging and leading of
output clock with the reference clock respectively. The 1 1 1 1
   (2)
frequency of oscillation with respect to control voltage CT CSi C gate Coxide
VinVCO is shown in Fig. 6.
where CSi is the capacitance to the carriers in the channel, Cgate
is the depletion capacitance of the gate electrode and Coxide is
the oxide capacitance.

E. Frequency Divider

The addition of frequency divider circuit in a PLL

completes a frequency synthesizer circuit. The main function
of a frequency divider is to scale down the frequency of output
clock from the VCO. Here a divide by two circuits based on
true single phase clocking has been employed [15]. This
circuit divides the VCO output by two which is then fed to
PFD as input and so the frequency of the final output of the
VCO will get multiplied by two after locking. The Fig. 7 is the
frequency divider circuit and the output of the frequency
divider is shown in Fig. 8, where the clock period of the
output signal is twice that of the reference clock i.e., half of
the frequency of reference clock.
Fig. 5. FinFET based current starved VCO

Fig. 6 Oscillating frequency vs control voltage of VCO

Fig. 7. Divide by 2 circuit

The frequency increases with the control voltage and so

the occurrence of UP pulses induces oscillation of the VCO at
the required frequency. The FinFET p_F4 and n_F3 forms a
buffer stage and p_F3 & n_F4 are used to limit the amount of
current flow in the buffer. The input stage of the inverter
consists of FinFETs p_F2 and n_F2. The control voltage
Vinvco sets the drain currents of FinFETs p_F2 and n_F2. The
drain current of these two devices are same and are mirrored
over each inverter stage that follows. When VinVCO= Vdd/2, the
current starved VCO possesses an oscillation frequency given
by the following expression [14]:
Id
VCO freq  (1)
(n  CT  Vdd )
where Id is the drain current, n is the number of inverter stages Fig. 8. The output of divider circuit
employed, for this case n=5. Vdd is the supply voltage which is

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 III. FREQUENCY SYNTHESIZER frequency of output clock is twice as that of the reference
clock. The pulse width of the UP signal is reduced with time as
The main function of a frequency synthesizer is to generate locking is achieved at consequently. This represents the
a new range of frequencies from a single stable reference clock reduction of phase error between the reference clock and
frequency. The frequency synthesizer circuit designed to output clock. The comparison of FinFET and various CMOS
generate a frequency of 1GHz from a stable reference clock technology based design of frequency synthesizer are
frequency of 500MHz. The frequency divider which is added summarized in the Table I.
between the VCO output and PFD used to divide frequency by
2. The phase errors between the reference clock and frequency TABLE I. COMPARISON OF FREQUENCY SYNTHESIZER PERFORMANCE WITH
PREVIOUS WORKS
divider is generated by the PFD which drives the VCO and this
design is the key to synthesize the frequency twice the Ref This
reference clock. The frequency of reference clock is 500MHz Ref [16] Ref [9]
[17] Work
and that of the output from the frequency divider is 250MHz. CMOS CMOS CMOS FinFET
As this increases phase errors consequently increasing the Technology
control voltage and double the frequency of the VCO. The 180-nm 130-nm 90-nm 30-nm
acquisition curve of frequency synthesizer is shown in Fig. 9 Settling
200 μs 500 μs 400 μs 254 ns
where the locking time is 254ns. Time
VCO
100 770
tuning N/A 1 GHz
MHz MHz
range
Supply
1.2 V 1.2 V 1.2 V 1V
Voltage

IV. CONCLUSION
A FinFET based frequency synthesizer circuit capable of
synthesizing a reference clock frequency into twice the
frequency was designed. The functionality of the designed
circuit is verified by synthesizing a 1GHz frequency from a
reference frequency of 500MHz. The lock-in time observed is
254 ns.

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Fig. 9 Acquisition curve of PLL frequency synthesizer
Fig. 10. Simulation waveform of FinFET based frequency synthesizer.
(Output clock is shown as a line with the symbol and the reference clock is
the line without symbol)
Fig. 10 shown above is the output of the frequency
synthesizer where the frequency doubling is achieved. The
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