Manual - PMAC-LITE Hardware Reference Manual

Hardware Reference
MANUAL
“UNIVERSAL”
PMAC-LITE
P/N 400-602402-10x
Manual P/N 400-602402-363
September 1999
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MAIN INDEX
PMAC-Lite Hardware Reference
TABLE OF CONTENTS
INTRODUCTION .............................................................................................................1
Overview ...................................................................................................................................................................... 1
Board Configuration................................................................................................................................................... 1
Hardware Updates ...................................................................................................................................................... 4
Compatibility Issues.................................................................................................................................................... 5
E-POINT DESCRIPTIONS ..............................................................................................7
E1 - E2: Machine Output Supply Voltage Configure .............................................................................................. 7
E3 - E6: Servo Clock Frequency Control................................................................................................................. 8
E7: Machine Input Source/Sink Control.................................................................................................................. 9
E9, E10, E13, E14: Serial Interface Direction Control ........................................................................................... 9
E17A-D: Amplifier Enable/Direction Polarity Control ......................................................................................... 10
E22 - E23: Control Panel Handwheel Enable........................................................................................................ 10
E24 - E27: Encoder Single-Ended/Differential Control........................................................................................ 11
E28: Following Error/Watchdog Timer Signal Control....................................................................................... 11
E29 - E33: Phase Clock Frequency Control .......................................................................................................... 12
E34 - E38: Encoder Sampling Clock Frequency Control ..................................................................................... 12
E39: Reset-From-Bus Enable.................................................................................................................................. 13
E40 - E43: Servo and Phase Clock Direction Control .......................................................................................... 13
E44 - E47: Serial Baud Rate Control ..................................................................................................................... 14
E48: CPU Clock Frequency Control ...................................................................................................................... 15
E49: Serial Communications Parity Control ......................................................................................................... 15
E50: Non-Volatile Memory Save Control .............................................................................................................. 16
E51: Normal/Re-initializing Power-Up .................................................................................................................. 16
E54 - E65: Host Interrupt Signal Select ................................................................................................................. 17
E66 - E71: Bus Base Hardware Address (Low Bits) ............................................................................................. 18
Table of Contents i
E72 - E73: Panel Analog Time Base Signal Enable............................................................................................... 18
E74 - E75: Clock Output Control for Ext. Interpolation...................................................................................... 19
E76 - E84: Host Interrupt Signal Select ................................................................................................................. 20
E85: Host-Supplied Analog Power Source Enable................................................................................................ 21
E86: Host Interrupt Signal Select ........................................................................................................................... 21
E87 - E88: Host-Supplied Analog Power Source Enable...................................................................................... 22
E89: Amplifier-Supplied Switch Pull-Up Enable .................................................................................................. 22
E90: Host-Supplied Switch Pull-Up Enable........................................................................................................... 23
E91 - E92: Bus Base Address Select (High Bits).................................................................................................... 23
E93 - E94: Reset from Bus by Software Enable ..................................................................................................... 24
E98: DAC/ADC Clock Frequency Control ............................................................................................................ 25
E100: Output Flag Supply Select............................................................................................................................. 25
E101 – E102: Output Flag Supply Voltage Configure........................................................................................... 26
E103: Watchdog Disable Jumper ............................................................................................................................ 27
E106: Firmware Reload Enable............................................................................................................................... 27
E110: Expansion Port Configuration ...................................................................................................................... 27
HOST PC-AT I/O ADDRESS MAP................................................................................29
BUS ADDRESS JUMPER SETUP................................................................................31
MATING CONNECTORS ..............................................................................................33
CONNECTOR PINOUTS ..............................................................................................37
J1 (JDISP): Display Port Connector ....................................................................................................................... 37
J2 (JPAN): Control Panel Port Connector ............................................................................................................. 38
J3 (JTHW): Multiplexer Port Connector ............................................................................................................... 40
J4 (JRS232) Serial Port Connector ......................................................................................................................... 42
J4A (JRS422): Serial Port Connector ..................................................................................................................... 43
J5 (JOPTO): I/O Port Connector ............................................................................................................................ 44
ii Table of Contents
J6 (JXIO): Auxiliary I/O Port Connector...............................................................................................................................45
J7 (JS1): A/D Port Connector ..................................................................................................................................................46
J8 (JEQU): Position-Compare Connector...............................................................................................................................47
J11 (JMACH1): Machine Port Connector.............................................................................................................................48
TB1 (JPWR): Power Supply......................................................................................................................................................51
SCHEMATICS
Sheet 2 of 5
Sheet 3
Sheet 4
Sheet 5
Table of Contents iii

iv Table of Contents
INTRODUCTION
Overview
The PMAC-Lite is a member of the PMAC(1) family of boards optimized for interface to traditional
servo drives with single analog inputs representing velocity or torque commands. Its software is capable
of 8 axes of control. It has 4 channels of on-board axis interface circuitry. It can also support up to 8
channels of off-board axis interface circuitry through its expansion port, connected to an ACC-24P
board.
The PMAC-Lite is a full-sized ISA-bus expansion board. While the PMAC-Lite is capable of ISA bus
communications, with or without the optional dual-ported RAM, it does not need to be inserted into an
ISA expansion slot. Communications can be done through an RS-232 or RS-422 serial port; standalone
operation is possible.
The new “Universal” PMAC-Lite board replaces the previous PMAC-Lite board with battery-backed
RAM and the PMAC1.5-Lite board with flash-backed RAM. The Universal PMAC-Lite can be built to
use either type of memory.
Board Configuration
Base Version
The base version of the PMAC-Lite provides a 1-slot board with:
• 20 MHz DSP56002
• 128k x 24 SRAM active memory
• Battery-backup circuitry for SRAM (PMAC-Lite)
• 128k x 8 EPROM for firmware (PMAC-Lite)
• 512k x 8 flash memory for SRAM backup & firmware (PMAC1.5-Lite)
• Latest released firmware version
• RS-232/422 serial interface, ISA (PC) bus interface
• 4 channels axis interface circuitry, each including:
• 16-bit +/-10V analog output
• 3-channel differential/single-ended encoder input
• 4 input flags, 2 output flags
• Interface to external 16-bit serial ADC
• Display, control panel, muxed I/O, direct I/O interface ports
• PID/notch/feedforward servo algorithms
Introduction 1
The unit has a 1-year limited warranty from date of shipment, and includes one manual per set of 1 to 4
PMACs in shipment.
Cables, mounting plates, and mating connectors are not included.
If the PMAC(1)-Lite version (battery-backed memory) of the board is ordered, the standard configuration
will have SRAM ICs in U6, U9, and U15, filling the full footprint, and a battery in BT1. There will be
no SRAM ICs in U7, U10, and U16. There will be an EPROM IC in the U5 socket.
If the PMAC1.5-Lite version (flash-backed memory) of the board is ordered, the standard configuration
will have SRAM ICs in U7, U10, and U16. There will be a flash-memory IC in the U5 socket. There
will be no SRAM ICs in U6, U9, and U15, and no battery in BT1, unless Option 16 is ordered.
Option 2: Dual Ported RAM

Dual-ported RAM provides a very high speed communications path for bus communications with the
host computer through a bank of shared memory. DPRAM is advised if more than about 100 data items
per second are to be passed between the controller and the host computer in either direction.
Option 2 provides an on-board 8k x 16 bank of dual-ported RAM. The key component on the board is
U46. (Note that for previous versions of the PMAC-Lite, this was a separate board.)
Option 5: CPU & Memory Configurations

The standard PMAC-Lite has a 20-MHz CPU. Options 5A, 5B and 5C are available for applications
requiring more computing power. These options provide faster CPU ICs in U13 and faster SRAM ICs in
U7, U10, and U16. They are only available with flash-memory backup of the SRAM.
Option 5A provides a 40 MHz CPU with zero-wait-state SRAM active memory and flash backup.
Option 5B provides a 60 MHz CPU with zero-wait-state SRAM active memory and flash backup.
Option 5C provides an 80 MHz CPU with zero-wait-state SRAM active memory and flash backup.
Option 6: Extended Servo Algorithm

The standard PID servo algorithm with feedforward and notch filter is suitable for most applications.
Systems with difficult dynamics, especially with significant flexibility, may require a more powerful
servo algorithm, such as the Extended Servo Algorithm (ESA).
Option 6 provides firmware in the PMAC-Lite that replaces the standard PID servo algorithm with the
Extended Servo Algorithm. This option provides different firmware in the U5 flash-memory/EPROM
IC. If loaded at the factory, this IC will have a “1” suffix on the labeled and reported version number
(e.g. V1.16D1).
Option 7: Plate Mounting

If the PMAC-Lite is used as an ISA bus expansion board, the standard hardware provides for proper
mounting of the board in the bus. However, if it is not installed in an ISA expansion slot, other
provisions must be made for mounting.
Option 7 provides a mounting plate connected to the PMAC-Lite with standoffs. It is used to install the
PMAC-Lite in standalone applications.
2 Introduction
Option 8: High-Accuracy Clock Crystal

The PMAC-Lite has a clock crystal (component Y1) of nominal frequency 19.6608 MHz (~20 MHz).
The standard crystal’s accuracy specification is +/-100 ppm. Long-term velocity accuracy is limited by
the accuracy of the crystal, unless an external time base is used.
Option 8A provides a nominal 19.6608 MHz crystal with a +/-15 ppm accuracy specification.
Option 9: RS-422 Interface (now standard)

The RS-422 interface now comes standard with the PMAC-Lite in addition to the RS-232 interface.
There is no need to order Option 9L as before.
Option 10: Firmware Version Specification

Normally the PMAC-Lite is provided with the newest released firmware version. A label on the U5
flash-memory/EPROM IC shows the firmware version loaded at the factory.
Option 10 provides for a user-specified firmware version.
Option 14: Replacement of flag Opto-Isolators with Socketed Shunts

Normally, the flag inputs on all servo channels have opto-isolator circuits that require 12 to 24V inputs to
turn on. When the ACC-8D Option 8 Analog Encoder Interpolator is used on a pair of channels, it uses
the flag inputs on the second (even-numbered) channel to provide “sub-count” information at 5V levels
referenced to digital ground.
Option 14 replaces the opto-isolators on the even-numbered channels of PMAC-Lite with socketed
shunts that permit the input of 5V non-isolated signals from the ACC-8D Option 8 board.
Option 15: V-to-F Converter for Analog Input

The JPAN control panel port on the PMAC-Lite has an optional analog input called WIPER (because it is
often tied to a potentiometer’s wiper pin). PMAC-Lite can digitize this signal by passing it through an
optional voltage-to-frequency converter, using E-point jumpers to feed this into the Encoder 4 circuitry
(no other use is then permitted), and executing frequency calculations using the “time base” feature of
the encoder conversion table.
Option 15 provides a voltage-to-frequency converter that permits the use of the WIPER input on the
control panel port.
Option 16: Battery-Backed Parameter Memory

The contents of the main flash-backed memory (components U7, U10, and U16) of the PMAC1.5-Lite
are not retained through a power-down or reset unless they have been saved to flash memory first.
Option 16 provides supplemental battery-backed RAM for real-time parameter storage that is ideal for
holding machine-state parameters in case of an unexpected power-down. It can only be used when the
main memory is flash-backed.
Option 16 provides a 16k x 24 bank of battery-backed parameter RAM in components U6, U9, U15
(smaller than the full footprint), with the battery in BT1.
Introduction 3
Hardware Updates
Significant upgrades were made to the PMAC-Lite board in the 602402-102 version. This new version
replaces earlier versions of the 602402 board (PMAC1.5-Lite – flash-backed memory) , and the 602399
board (PMAC(1)-Lite – battery-backed memory). The ability to configure 602402-102 (and newer) in
either battery-backed or flash-backed memory configurations leads to it being called the “Universal”
PMAC-Lite.
Improvements on the Universal PMAC-Lite include:
• Universality. Formerly different board designs were used for battery-backed (602399-10x) and
flash-backed (PMAC1.5-Lite: 602402-101) versions of the PMAC-Lite. Now both configurations
can be built on the same board, for cost savings that are passed on to you.
• 80-MHz CPU. The new PMAC-Lite supports the Option 5C 80 MHz CPU for high-end operations.
• Supplemental Battery-Backed Parameter Memory. The new PMAC-Lite supports the Option 16
supplemental battery-backed parameter memory when the main memory is flash-backed.
• On-board Dual-Ported RAM. The new PMAC-Lite has optional on-board dual-ported RAM,
whereas the old PMAC-Lite required a separate board. On-board DPRAM saves an expansion slot
and is less expensive.
• Raised Bottom Edge. The bottom edge of the board has been raised so that it can clear high-profile
parts on the PC mother board – up to 25mm (1 inch) high.
• Standard RS-422 Serial Port. An RS-422 serial interface, which formerly required the Option 9L
piggyback board, now is standard. Jumpers E107 and E108 select between the RS-232 port and the
RS-422 port.
• 24V Amplifier-Enable Capability. New Jumper E100 permits use of up to 24V supply for the
amplifier-enable signal, compared to a maximum of 15V on the older version.
• Sinking or Sourcing Input Flags. The new ACC-24P permits the use of either sinking or sourcing
input flags (home, limits, fault); the old ACC-24P permitted only sinking input flags.
• Voltage Interlock Circuit. The new ACC-24P has an interlock circuit that shuts down the analog
outputs if it detects anything wrong with the power supply, preventing runaway on partial supply
loss.
• Surface-Mount Technology. Most components are surface mounted for higher reliability and
greater long-term part availability.
• In-System-Programmable Logic. Interface logic ICs now can be programmed when installed in the
PMAC-Lite, permitting elimination of sockets for higher reliability, and easier manufacturing and
upgradability.
4 Introduction
Compatibility Issues
The new PMAC-Lite can be operated in a manner that is 100% compatible with the old PMAC-Lite. The
board is shipped from the factory with settings for 100% compatible operation. To ensure your operation
is compatible, double-check the following settings:
• Raised Bottom Edge. The higher bottom edge moves the lower left mounting hole for standoffs up
12.7 mm (0.5 in). If you are using standoff mounting, and cannot move the matching mounting hole,
contact Delta Tau for free offset standoffs.
• Serial Port Choice. Because both RS-232 and RS-422 ports are always provided, jumpers must be
set correctly to use the port of your choice. Jumpers E107 and E108 must connect pins 1 and 2 to use
the RS-232 port on the J4 connector; they must connect pins 2 and 3 to use the RS-422 port on the
J4A connector.
• On-Board Dual-Ported RAM. If you wish to use dual-ported RAM with your new PMAC-Lite,
you must order Option 2 at the time you order the board. The new PMAC-Lite is not compatible
with the off-board DPRAM, and the on-board DPRAM option cannot be installed in the field.
• 24V Amplifier Enable Capability. In order for the amplifier enable outputs to use the +12V to
+15V analog supply voltage for a high-side clamping supply, jumper E100 must connect pins 1 and
2.
• Sinking/Sourcing Input Flags. To use sinking input flags, connect the flags as you have done
before.
• Firmware Reload. Putting jumper E51 ON is now for re-initialization to factory default values
only. Firmware reload is set up by jumping pins 2 and 3 of E106.
Introduction 5
6 Introduction
E-POINT DESCRIPTIONS
E1 - E2: Machine Output Supply Voltage Configure

E Point & Physical Location Description Default
Layout
E1 D1 CAUTION 1-2 Jumper
The jumper setting must match the type installed
of driver IC, or damage to the IC will
result.
Jump pin 1 to 2 to apply +V (+5V to

24V) to pin 11 of “U26” (should be
ULN2803A for sink output
configuration) JOPTO “MACHINE”
outputs M01-M08
Jump pin 2 to 3 to apply GND to pin

11 of U26 (should be UDN2981A for
source output configuration)

The jumper setting must match the type installed
result.
Jump pin 1 to 2 to apply GND to pin
10 of “U26” (should be ULN2803A for
sink output configuration).
Jump pin 2 to 3 to apply +V (+5V to

24V) to pin 10 of “U26” (should be
UDN2981A for source output
configuration).
E-Point Descriptions 7
E3 - E6: Servo Clock Frequency Control

The servo clock (which determines how often the servo loop is closed) is derived from the phase clock
(see E98, E29 - E33) through a “divide-by-N” counter. Jumpers E3 through E6 control this dividing
function.
Default & Physical Layout
E3 E4 E5 E6
E3 E4 E5 E6 Servo Clock = Phase
Clock Divided by N
LOC.: E4 E4 E4 E4
ON ON ON ON N = Divided by 1
OFF ON ON ON N = Divided by 2
ON OFF ON ON N = Divided by 3
OFF OFF ON ON N = Divided by 4 ONLY E5 and E6 ON
ON OFF ON ON N = Divided by 5
OFF ON OFF ON N = Divided by 6
ON OFF OFF ON N = Divided by 7
OFF OFF OFF ON N = Divided by 8
ON ON ON OFF N = Divided by 9
OFF ON ON OFF N = Divided by 10
ON OFF ON OFF N = Divided by 11
OFF OFF ON OFF N = Divided by 12
ON ON OFF OFF N = Divided by 13
OFF ON OFF OFF N = Divided by 14
ON OFF OFF OFF N = Divided by 15
OFF OFF OFF OFF N = Divided by 16
Adjust the setting of I-variable I10 to match the servo interrupt cycle time set by E98, E29 -- E33, and E3 -
- E6. I10 holds the length of a servo interrupt cycle, scaled so that 8,388,608 equals one millisecond.
Since I10 has a maximum value of 8,388,607, the servo interrupt cycle time should always be less than a
millisecond (unless you want to make your basic unit of time on PMAC something other than a
millisecond). If you wish a servo sample time greater than one millisecond, the sampling may be slowed
in software with variable Ixx60.
Frequency can be checked on J4 pins 21 & 22. It can also be checked from software by typing RX:0 in
the PMAC terminal at 10-second intervals and dividing the difference of successive responses by 10000.
The resulting number is the approximate Servo Clock frequency kHz.
If E40-E43 are not all ON, the phase clock is received from an external source through the J4 serial-port
connector, and the settings of E3 – E6 are not relevant.
8 E-Point Descriptions
E7: Machine Input Source/Sink Control

Layout
E7 C1 Jump pin 1 to 2 to apply +5V to input 1-2 Jumper
reference resistor sip pack; this will installed
bias MI1 to MI8 inputs to +5V for
“OFF” state; input must then be
grounded for “ON” state.
Jump pin 2 to 3 to apply GND to input
reference resistor sip pack; this will
bias MI1 to MI8 inputs to GND for
“OFF” state; input must then be pulled
up for “ON” state (+5V to +24V).
E9, E10, E13, E14: Serial Interface Direction Control

The E9, E10, E13, and E14 jumpers control whether the RS-232 serial port will be in DCE or DTE
format. The default configuration permits straight-across connection to a PC DB-9 serial port.
Layout
E9 E10 E1 Jump E9-1 to E9-2 to allow RXD/ 1-2 Jumpers
to be input on J4-3. Jump E10-1 to installed
E10-2 to allow TXD/ to be output
on J4-5.
Jump E9-1 to E10-1 to allow TXD/
to be output on J4-3. Jump E9-2 to
E10-2 to allow RXD/ to be input on
J4-5.
E13 E14 E1 Jump E13-1 to E13-2 to allow RTS 1-2 Jumpers
to be input on J4-7. Jump E14-1 to installed
E14-2 to allow CTS to be output on
J4-9.
Jump E13-1 to E14-1 to allow CTS
to be output on J4-7. Jump E13-2
to E14-2 to allow ‘RTS’ to be input
on J4-9.
E17A-D: Amplifier Enable/Direction Polarity Control

Layout
E17A F1 Jump 1-2 for high-true AENA1 No jumper installed
Remove jumper for low-true AENA1
E17B F1 Jump 1-2 for high-true AENA2 No jumper installed

E17C F1 Jump 1-2 for high-true AENA3 No jumper installed

E17D F1 Jump 1-2 for high-true AENA4 No jumper installed

Note: Low-true enable is the fail-safe option with the default sinking ULN2803A output driver IC. High-
true enable is the fail-safe option with the alternate sourcing UN2981A.
E22 - E23: Control Panel Handwheel Enable

E-Point & Physical Location Description Default
Layout
E22 E2 Jump pin 1 to 2 to obtain handwheel No jumper
encoder signal from front panel at J2-
16 for CHB2 (ENC2-B).
E23 E2 Jump pin 1 to 2 to obtain handwheel No jumper

encoder signal from front panel at J2-
22 for CHA2 (ENC2-A).
Note: With these jumpers ON, no encoder should be wired into ENC2 on JMACH1. Jumper E26 must
connect pins 1-2, because these are single-ended inputs. This function is unrelated to the encoder brought
in through ACC-39 on J2.
E24 - E27: Encoder Single-Ended/Differential Control

Layout
E24 F2 ENC 4 through 1: 1-2 Jumper
installed for
Jump pin 1 to 2 to tie complementary E24 - E27
encoder inputs to 2.5V
E25 F2 Jump pin 2 to 3 to tie E24: ENC 4

complementary encoder inputs to 5V E25: ENC 3
E26: ENC 2
For no encoder connection: Jump pin E27: ENC 1
1 to 2
E26 F3
For single-ended encoders: Jump pin 1
to 2
For differential line-driver encoders:

Don’t care
E27 F3
For complementary open-collector
encoders: Jump pin 2 to 3
E28: Following Error/Watchdog Timer Signal Control

Layout
E28 C2 Jump pin 1 to 2 to allow warning 2-3 Jumper
following error (Ix12) for the selected installed
coordinate system to control FEFCO/
on J8-57
Jump pin 2 to 3 to cause WATCHDOG

timer output to control FEFCO/.
Low TRUE output in either case
E29 - E33: Phase Clock Frequency Control

Jumpers E29 through E33 control the speed of the phase clock, and, indirectly, the servo clock, which is
divided down from the phase clock (see E3 - E6). No more than 1 of these 5 jumpers may be on at a
time.
PHASE CLOCK
FREQUENCY DEFAULT &
E29 E30 E31 E32 E33 E98 Connects E98 Connects PHYSICAL LOC
Pins 1 and 2 Pins 2 and 3 LAYOUT
ON OFF OFF OFF OFF 2.26 kHz 1.13 kHz B2
E29
OFF ON OFF OFF OFF 4.52 kHz 2.26 kHz B2
E30
OFF OFF ON OFF OFF 9.04 kHz 4.52 kHz B2
E31
OFF OFF OFF ON OFF 18.07 kHz 9.04 kHz B2
E32
OFF OFF OFF OFF ON 36.14 kHz 18.07 kHz B2
E33
Note: If E40-E43 are not all ON, the phase clock is received from an external source through the J4
serial-port connector, and the settings of E29 – E33 are not relevant.
E34 - E38: Encoder Sampling Clock Frequency Control

Jumpers E34 - E38 control the encoder sampling clock (SCLK) used by the gate array ICs. No more than
1 of these 6 jumpers may be on at a time.
SCLK CLOCK DEFAULT & PHYSICAL
LAYOUT
FREQUENCY
E34A E34 E35 E36 E37 E38
E34A E34 E35 E36 E37 E38
LOCATION; ALL AT D4
ON OFF OFF OFF OFF OFF 19.6608 MHz

OFF ON OFF ON OFF OFF 9.8304 MHz E34 ON
OFF OFF ON OFF OFF OFF 4.9152 MHz
OFF OFF OFF ON OFF OFF 2.4576 MHz
OFF OFF OFF OFF ON OFF 1.2288 MHz
OFF OFF OFF OFF OFF ON External Clock 1 TO 30
MHz max. input on
CHC4 & CHC4/
E39: Reset-From-Bus Enable

Layout
E39 C4 Jump pin 1 to 2 to allow PMAC to No jumper
derive its reset from the PC backplane.
Remove jumper to allow PMAC to
power up in normal way; PCbus
hardware reset will not reset PMAC; it
must be removed for standalone
operation.
Only one of E39, E93, and E94 should
be on at once. See also E93 & E94
E40 - E43: Servo and Phase Clock Direction Control

E40 E41 E42 E43 Card Address Servo & Phase Default & Physical
Clock Direction Layout
E40 E41 E42 E43
C3 C3 C3 C3
ON ON ON ON @0 OUTPUT (ALL ON)
OFF ON ON ON @1 INPUT
ON OFF ON ON @2 INPUT
OFF OFF ON ON @3 INPUT
ON ON OFF ON @4 INPUT
OFF ON OFF ON @5 INPUT
ON OFF OFF ON @6 INPUT
OFF OFF OFF ON @7 INPUT
ON ON ON OFF @8 INPUT
OFF ON ON OFF @9 INPUT
ON OFF ON OFF @A INPUT
OFF OFF ON OFF @B INPUT
ON ON OFF OFF @C INPUT
OFF ON OFF OFF @D INPUT
ON OFF OFF OFF @E INPUT
OFF OFF OFF OFF @F INPUT
Note: If any jumper E40 – E43 is removed and the servo and phase clocks are not brought in on the J4A
serial port, the watchdog timer will trip immediately.
E44 - E47: Serial Baud Rate Control

Jumpers E44 - E47 control what baud rate to use for serial communications. Any character received over
the bus causes PMAC to use the bus for its standard communications. The serial port is disabled when
E44-E47 are all on.
Baud Rate Control Baud Rate Default &
“E” Points Physical Layout
E44 E45 E46 E47 20 MHz Battery 60 MHz 80 E44 E45 E46 E47
Flash CPU, 40 Flash MHz
CPU MHz CPU Flash
(OPT Flash (Opt 5B) CPU
4A) CPU (Opt C3 C3 C3 C3
(Opt 5A) 5C)
ON ON ON ON DISABLE DISABLE DISABLE DISABL
D D D ED
OFF ON ON ON 300 600 900 1200
ON OFF ON ON 400* 800* 1200 1600*
OFF OFF ON ON 600 1200 1800 2400
ON ON OFF ON 800* 1600* 2400 3200*
OFF ON OFF ON 1200 2400 3600 4800
ON OFF OFF ON 1600* 3200* 4800 6400*
OFF OFF OFF ON 2400 4800 7200 9600 Opt 5C
ON ON ON OFF 3200* 6400* 9600 12800* Opt 5B
OFF ON ON OFF 4800 9600 14400 19200 Standard, Opt 5A
ON OFF ON OFF 6400* 12800* 19200 25600*
OFF OFF ON OFF 9600 19200 28800 38400 Opt 4A (1.5-Lite)
ON ON OFF OFF 12800* 25600* 38400 51200*
OFF ON OFF OFF 19200 38400 57600 76800
ON OFF OFF OFF 25600* 51200* 76800 102400*
OFF OFF OFF OFF 38400 76800 115200 153600
*Non-standard baud rate
Note: These jumpers are only read at power-up/reset to set the baud rate at that time.
E48: CPU Clock Frequency Control

E Point & Location Description Default
Physical Layout
E48 C2 Jump pins 1 and 2 to multiply crystal No jumper installed
frequency by 3 inside CPU for 60 MHz (20, 40 & 80 MHz
operation versions)
Remove jumper to multiply crystal Jumper installed

frequency by 2 inside CPU for 40 MHz (60 MHz version)
operation
Don’t care for 20 MHz CPU versions
For 80 MHz operation, set jumper for

40 MHz, then increase speed in
software (WX$FFFD,$750003)
Note: It may be possible to operate a board at a frequency higher than that for which its components are
are rated. However, this uses the components outside of their specified operating range, and proper
execution of the PMAC under these conditions is not guaranteed. PMAC software failure is possible, even
probable, under these conditions, and this can lead to very dangerous machine failure. Operation in this
mode is done completely at the user’s own risk; Delta Tau can accept no responsibility for the operation of
the PMAC or the machine under these conditions.
E49: Serial Communications Parity Control

Physical Layout
E49 C2 Jump pin 1 to 2 for NO serial parity; Jumper installed
remove jumper for ODD serial parity
E50: Non-Volatile Memory Save Control

Physical Layout
E50 C2 Jump pin 1 to 2 to enable save to Jumper installed
EAROM or flash memory
Remove jumper to disable save to

EAROM or flash memory
E51: Normal/Re-initializing Power-Up

Physical Layout
E51 C2 Jump pin 1 to 2 to re-initialize on No jumper installed
power-up/reset, loading factory default
parameters
Remove jumper for normal power-

up/reset, loading last saved parameters
Note: On the Universal PMAC-Lite, the board is put in “bootstrap mode” for the loading of new firmware
by connecting pins 2 and 3 of E106. E51 is for re-initialization of parameters only.
E54 - E65: Host Interrupt Signal Select

Physical Layout
E55 B4 Jump pin 1 to 2 to allow EQU4 to No jumper installed
interrupt host-PC at PMAC interrupt
level IR7
E57 C4 Jump pin 1 to 2 to allow EQU3 to No jumper installed

level IR7
E58 C4 Jump pin 1 to 2 to allow MI2 to No jumper installed

level IR6
E59 C4 Jump pin 1 to 2 to allow AXIS No jumper installed

EXPANSION INT-0 to interrupt host-
PC at PMAC interrupt level IR6
E61 C4 Jump pin 1 to 2 to allow EQU2 to No jumper installed

level IR6
E62 C4 Jump pin 1 to 2 to allow MI1 to No jumper installed

level IR5
E63 C4 Jump pin 1 to 2 to allow AXIS No jumper installed

EXPANSION INT-1 to interrupt host-
PC at PMAC interrupt level IR5
E65 C4 Jump pin 1 to 2 to allow “EQU1” to No jumper installed

level “IR5”.
E66 - E71: Bus Base Hardware Address (Low Bits)

These jumpers work with E91 & E92 to set the base address of PMAC-Lite on the PC bus. See PMAC-
Lite Bus Addressing below for details on how to set these jumpers.
Physical Layout
E66 E67 E68 E69 E70 E71 C4/D4 E66 - Bit 9 PC bus base E67-E70
address installed
E67 - Bit 8 PC bus base
address
address
address
address
address
ON = 0; OFF = 1 for
calculating bus address
E72 - E73: Panel Analog Time Base Signal Enable

Physical Layout
E72 D2 Jump pin 1 to 2 to allow V to F No jumper installed
converter FOUT derived from WIPER
input on J2 to connect to CHA4
E73 D2 Jump pin 1 to 2 to allow V to F No jumper installed

converter SIGNOUT derived from
WIPER input on J2 to connect to CHB4
Note: With these jumpers ON, no encoder should be wired into ENC4 on JMACH1. E27 must
connect pins 1 to 2 because these are single-ended inputs. Variable I915 should be set to 4 to
create a positive voltage (frequency) number in PMAC.
E74 - E75: Clock Output Control for Ext. Interpolation

Physical Layout
E74 D2 Jump pin 1 to 2 to allow SCLK/ to No jumper installed
output on CHC4/
E75 D2 Jump pin 1 to 2 to allow SCLK to No jumper installed

output on CHC4
Note: SCLK out permits synchronous latching of analog encoder interpolators such as ACC-8D Opt 8.
E76 - E84: Host Interrupt Signal Select

Physical Layout
E76 D4 jump pin 1 to 2 to allow PMAC- No jumper installed
INTERRUPT to host-PC on IRQ14
E77 D4 Jump pin 1 to 2 to allow PMAC- No jumper installed




E81 E4 Jump pin 1 to 2 to allow PMAC- No jumper installed




Note: Only one of the jumpers from E76 to E84, and E86, should be ON at one time.
E85: Host-Supplied Analog Power Source Enable

Physical Layout
E85 F4 Jump pin 1 to pin 2 to allow A+14V to No jumper
come from PC bus (ties amplifier and
PMAC-Lite power supply together.
Defeats OPTO coupling)
Note that if E85 is changed, E88 and

E87 must also be changed
Also see E90
E86: Host Interrupt Signal Select

Physical Layout
E86 E4 Jump pin 1 to 2 to allow PMAC- No jumper
E87 - E88: Host-Supplied Analog Power Source Enable

Physical Layout
E87 F4 Jump pin 1 to pin 2 to allow AGND to No jumper
PMAC-Lite GND together. Defeats
OPTO coupling)

E88 also must be changed
Also see E90

E88 F4 Jump pin 1 to pin 2 to allow A-14V to No jumper
PMAC-Lite power supply together.
Defeats OPTO coupling)

E85 must also be changed.
Also see E90.
E89: Amplifier-Supplied Switch Pull-Up Enable

Physical Layout
E89 F3 Jump pin 1 to 2 to use A+15V on J8 Jumper installed
(JMACH1) pin 59 as supply for input
flags
Remove jumper to use A+15V/OPT+V

from J7 pin 59 as supply for input flags
Note: This jumper setting is only

relevant if E90 connects pin 1 to 2
E90: Host-Supplied Switch Pull-Up Enable

Physical Layout
E90 F3 Jump pin 1 to 2 to use A+15V from J8 1-2 Jumper
pin 59 as supply for input flags (E89 installed
ON) {flags should be tied to AGND}
or A+15V/OPT+V from J8 pin 11 as
supply for input flags (E89 OFF) {flags
should be tied to separate 0V
reference}
Jump pin 2 to 3 to use +12V from PC
bus connector P1-pin B09 as supply
for input flags {flags should be tied to
GND}
See also E85, E87, E88 and PMAC
Opto-isolation diagram
E91 - E92: Bus Base Address Select (High Bits)

Physical Layout
E91 E92 A4 E91 - Bit 11 PC bus base address Jumper installed
E92 - Bit 10 PC bus base address
ON = 0 OFF = 1
These jumpers work with E66 - E71 to set the base address of PMAC-Lite on the PC bus. See PMAC-Lite
PC Bus Addressing below for details on how to set these jumpers.
E93 - E94: Reset from Bus by Software Enable

Physical Layout
E93 C4 Jump 1-2 to provide a hardware No jumper
RESET of PMAC-Lite under the
software control of the host-PC.
PMAC-Lite will power up and stay in
the RESET state until PC software
writes 40 HEX to BASE+12. PMAC-
Lite can be put in RESET state by PC
writing 40 HEX to BASE+10
Remove jumper to disable this function
Only one of E39, E93, E94 should be
ON at the same time
E94 C4 Jump 1-2 to provide a hardware No jumper

RESET of PMAC-Lite under the
software control of the host-PC.
PMAC-Lite will power up in
NORMAL mode. PMAC-Lite can be
put in RESET state by PC writing 40
HEX to BASE+12. PMAC-Lite can be
released from RESET state by PC
writing 40 HEX to BASE+10
Remove jumper to disable this function
Only one of E39, E93, E94 should be
ON at the same time
E98: DAC/ADC Clock Frequency Control

Physical Layout
E98 D4 Jump 1-2 to provide a 2.45 MHz 1-2 Jumper
DCLK signal to DACs and ADCs installed
Jump 2-3 to provide a 1.22 MHz
DCLK signal to DACs and ADCs.
Important for high accuracy A/D
conversion on ACC-28
Note: This also divides the phase and servo clock frequencies in half.
See E29-E33, E3-E6, I10
E100: Output Flag Supply Select

Physical Layout
E100 Jump pin 1 to 2 to apply analog supply 1-2 Jumper
voltage A+15V to U54 flag output installed
driver IC
Jump pin 2 to 3 to apply flag supply
voltage OPT+V to U54 flag output
driver IC
E101 – E102: Output Flag Supply Voltage Configure

Physical Layout
E101 CAUTION 1-2 Jumper
installed
The jumper setting must match the type
result.
Jump pin 1 to 2 to apply +V (12V to
24V) to pin 10 of U54 (should be
ULN2803A for sink output
configuration) for AENA1-4 and
EQU1-4 flag outputs
Jump pin 2 to 3 to apply AGND to pin
10 of U54 (should be UDN2981A for
source output configuration) for
AENA1-4 and EQU1-4 flag outputs

installed
The jumper setting must match the type
result.
Jump pin 1 to 2 to AGND to pin 9 of
U54 (should be ULN2803A for sink
output configuration) for AENA1-4
and EQU1-4 flag outputs
Jump pin 2 to 3 to apply apply +V
(12V to 24V) to pin 9 of U54 (should
be UDN2981A for source output
configuration) for AENA1-4 and
EQU1-4 flag outputs
E103: Watchdog Disable Jumper

Physical Layout
E103 Jump pin 1 to 2 to disable No jumper installed
WATCHDOG timer (for test purposes
only!!)
Remove jumper to enable
WATCHDOG timer
E106: Firmware Reload Enable

Physical Layout
E106 Remove jumper for normal operation No jumper installed
Jump pin 1 to 2 to lock card in reset
state for programming of on-board
logic (for factory use only)
Jump pin 2 to 3 to reload firmware
through serial or bus port on power-
up/reset
E110: Expansion Port Configuration

Physical Layout
E110 Jump pin 1 to 2 to bring address line 1-2 jumper
BA04 to JEXP pin 31 to support installed
interface to ACC-24P2 board
Jumper pin 2 to 3 to bring chip select
line CS02/ to JEXP pin 31
HOST PC-AT I/O ADDRESS MAP
Hex Range Dec Range Usage

000-01F 0-31 DMA Controller 1 8237A-5
020-03F 32-63 Interrupt Controller 1 8259A
040-05F 64-67 Timer 8254-2
060-06F 96-111 8042 (Keyboard)
070-07F 112-127 Real-time clock, NMI mask
080-09F 128-159 DMA Page Registers
0A0-0BF 160-191 Interrupt Controller 2 8259A
0C0-0DF 192-223 DMA Controller 2 8237A-5
0F0-0FF 240-255 Math CO processor
1F0-1F8 496-504 Fixed Disk
200-20F 512-527 Game Control
210-217 528-535 Expansion Unit (usually open)
278-27F 632-639 Parallel Printer: LPT2
2B0-2DF 688-735 Alternate EGA
2F8-2FF 760-767 Asynchronous Common: COM2
300-31F 768-799 Prototype Card (usually open)
360-36F 864-879 PC Network
378-37F 888-895 Parallel Printer: LPT1
380-38F 896-911 SDLC Communications 2
390-393 912-915 Cluster
3A0-3A9 928-937 SDLC Communications 1
3B0-3BF 944-959 IBM Monochrome Display/Printer
3C0-3CF 960-975 Enhanced Graphics Adapter
3D0-3DF 976-991 Color/Graphics
3F0-3F7 1000-1015 Diskette Controller
3F8-3FF 1016-1023 Asynchronous Common.: COM1
x2E1 GPIB Adapter
x390-x393 Cluster Adapter
Contention is exhibited by:
1) Total Malfunction.
2) Partial Function, Input O.K., Output bad or vice versa.
3) Intermittent operation.
Host PC-AT I/O Address Map 29

30 Host PC-AT I/O Address Map

BUS ADDRESS JUMPER SETUP
Jumpers E91, E92, E66, E67, E68, E69, E70, and E71 on the PMAC-Lite determine the base address of
the card in the I/O space of the host PC’s expansion bus. Together, they form a binary number that
specifies the 16 consecutive addresses on the bus where the card can be found.
The jumpers form the base address in the following fashion:
Jumper E91 E92 E66 E67 E68 E69 E70 E71
Bit # 11 10 9 8 7 6 5 4
Dec Value 2048 1024 512 256 128 64 32 16
Hex Value 800 400 200 100 80 40 20 10
If a jumper is ON, the value it contributes to the base address is ZERO.

If a jumper is OFF, the value it contributes to the base address is given in the table above.
On the PMAC-Lite, the jumpers are physically arranged in the same order they are presented in the above
table.
From Jumper Configuration To Address

To determine the address specified by a given jumper configuration, use the following formula:
(Decimal)
Address = 2048*E91 + 1024*E92 + 512*E66 + 256*E67 + 128*E68 + 64*E69 + 32*E70 + 16*E71
(Hexadecimal)
Address = $800*E91 + $400*E92 + $200*E66 + $100*E67 + $80*E68 + $40*E69 + $20*E70 +
$10*E71
In each case, Exx = 1 if the jumper is OFF; Exx = 0 if the jumper is ON.
Example: On a PMAC card, the jumpers are in the following configuration:
E91 E92 E66 E67 E68 E69 E70 E71
ON ON OFF OFF ON ON ON ON
The address can be computed as:

Decimal Address = 0 + 0 + 512 + 256 + 0 + 0 + 0 + 0 = 768
Hex Address = 0 + 0 + $200 + $100 + 0 + 0 + 0 + 0 = $300
Bus Address Jumper Setup 31

From Address To Jumper Configuration

Once an I/O address on the PC expansion port has been selected, the following procedure can be used for
setting the address jumpers.
1. Convert the address to a 3-digital hexadecimal value ($000 to $FFF, representing 0 to 4095). If the
value does not fit in this range, you will not be able to set PMAC for this address. Make sure the last
digit is 0; only addresses divisible by 16 are permitted as PMAC base addresses.
2. Take the first hex digit and convert it to binary. The binary digits represent bits 11 through 8 of the
base address. Assign each binary digit to jumpers as follows:
Bit # 11(MSB) 10 9 8(LSB)
Jumper E91 E92 E66 E67
Digit Value 8 4 2 1
Setting for 1 OFF OFF OFF OFF
Setting for 0 ON ON ON ON
3. Take the second hex digit and convert it to binary. The binary digits represent bits 7 through 4 of the
base address. Assign each binary digit to jumpers as follows:
Bit # 7(MSB) 6 5 4(LSB)
Jumper E68 E69 E70 E71
Digit Value 8 4 2 1
Setting for 1 OFF OFF OFF OFF
Setting for 0 ON ON ON ON
Example 1: You wish to set up the card to be at base address 992 decimal on the PC expansion bus.
1. 992 decimal is equal to 3E0 hexadecimal.
2. The first digit of 3 is binary 0011. This sets E91 ON, E92 ON, E66 OFF, E67 OFF.
3. The second digit of E is binary 1110. This sets E68 OFF, E69 OFF, E70 OFF, E71 ON.
1. 528 decimal is equal to 210 hexadecimal.
2. The first digit of 2 is binary 0010. This sets E91 ON, E92 ON, E66 OFF, E67 ON.
3. The second digit of E is binary 0001. This sets E68 ON, E69 ON, E70 ON, E71 OFF.
1. 544 decimal is equal to 220 hexadecimal.
2. The first digit of 2 is binary 0010. This sets E91 ON, E92 ON, E66 OFF, E67 ON.
3. The second digit of E is binary 0010. This sets E68 ON, E69 ON, E70 OFF, E71 ON.
32 Bus Address Jumper Setup

MATING CONNECTORS
This section lists several options for each connector. Choose an appropriate one for your
application.
J1 (JDISP)/DISPLAY PORT
1. 14-pin female flat cable connector Delta Tau P/N 014-R00F14-0K0
Qty. 2 - T&B Ansley P/N 609-1441
2. 171-14 T&B Ansley stan. flat cable stranded 14-wire
3. Phoenix varioface modules type FLKM14 (male pins) P/N 22 81 02 1
J2 (JPAN)/CONTROL PANEL PORT

1. 26-pin female flat cable connector Delta Tau P/N 014-R00F26-0K0 qty. 2 - T&B Ansley
P/N 609-2641
2. 171.26.T&B Ansley stan. flat cable stranded 26-wire
3. Phoenix varioface module type FLKM 26 (male pins) P/N 22 81 05 0
J3 (JTHW)/MULTIPLEXER PORT
P/N 609-2641
J4 (JRS232)/RS232 SERIAL COMMUNICATIONS

P/N 609-1041
J4A (JRS422)/RS422 SERIAL COMMUNICATIONS

P/N 609-2641
J5 (JOPT)/GENERAL-PURPOSE I/O
1. 34-pin female flat cable connector Delta Tau P/N 014-R00F34-0k0 qty. 2 - T&B Ansley
P/N 609-3441
Mating Connectors 33
J6 (JXIO)/AUXILIARY PORT
P/N 609-1041
J7 (JS1)/A-D INPUTS
P/N 609-1641
3. PHOENIX varioface module type FLKM 16 (male pins) P/N 22 81 03 4
J8 (JEQU)/POSITION COMPARE
P/N 609-1041
J9 (JEXP)/EXPANSION PORT
P/N 609-5041
3. Phoenix varioface module type FLKM 50 (male pins) P/N 22 81 08 9 used for daisy
chaining acc-14 I/0, -23 A and D connectors -24 expansion
J11 (JMACH1)/1st MACHINE CONNECTOR

P/N 609-6041 available as ACC 8P or 8D
Note
Normally, J11 is used with accessory 8P or 8D with Option P, which provides
complete terminal strip fan-out of all connections.
34 Mating Connectors
P1 (PC BUS)
62-pin card edge connector with solder pierced eyelets Delta Tau P/N 014-000F62-SCO qty. 1
Viking P/N 3KH 31/9 JN12 card edge conn. pierced solder eyelets.
P2 (AT BUS)
36-pin card edge connector with solder pierced eyelets Delta Tau P/N 014-000 F36-SCO qty.1
Viking P/N 3KH 18/9 JN12 card edge conn. pierced solder eyelets.
Mating Connectors 35
36 Mating Connectors
CONNECTOR PINOUTS
J1 (JDISP): Display Port Connector
J1 JDISP (14-PIN CONNECTOR)

Front View
Pin # Symbol Function Description Notes

1 Vdd Output +5V Power Power Supply Out
2 Vss Common PMAC Common
3 Rs Output Read Strobe TTL Signal Out
4 Vee Output Contrast Adjust Vee 0 TO +5 VDC *
5 E Output Display Enable High is Enable
6 R/W Output Read or Write TTL Signal Out
7 DB1 Output Display Data1
The JDISP connector is used to drive the 2 line x 24 character (Acc-12), 2 x 40 (Acc-12A) LCD, or the 2
x 40 vacuum fluorescent (Acc 12C) display unit. The DISPLAY command may be used to send messages
and values to the display.
* Note; Controlled by potentiometer R1
See Also:
Program Commands: DISPLAY
Accessories; ACC-12, 12A, 12C, ACC16D
Memory Map: Y:$0780 - $07D1
Connector Pinouts 37
J2 (JPAN): Control Panel Port Connector
J2 JPAN (26-PIN CONNECTOR)
Front View

1 +5V Output +5V Power For remote panel
2 GND Common PMAC Common
3 FPD0/ Input Motor/C.S. Select Bit 0 Low is TRUE
4 JOG-/ Input JOG IN - DIR. Low is”JOG -“
5 FPD1/ Input Motor/C.S. Select Bit 1 Low isTRUE
6 JOG+/ Input Jog In + Dir. Low is”JOG +”
7 PREJ/ Input Return to Prejog Position Low is”RETURN”
equiv to “J=” CMD
8 STRT/ Input Start Program Run Low is “START”
Equiv to “R” CMD
9 STEP/ Input Step through Program Low is”STEP”
Equiv to “S” OR “Q”
10 STOP/ Input Stop Program Run Low is “STOP”
Equiv to “A”
11 HOME/ Input Home Search Command Low is “GO HOME”
Equiv to “HM”
12 HOLD/ Input Hold Motion Low is “HOLD”
Equiv to “H”
13 FPD2/ Input Motor/C.S. Select Bit 2 Low isTRUE
14 FPD3/ Input Motor/C.S. Select Bit 3 Low is TRUE
15 INIT/ Input Reset PMAC Low is “RESET”
Equiv to “$$$”
16 HWCA Input Handwheel Enc. A Channel 5V TTL SQ. pulse
must use E23 (CHA2)
17 IPLD/ Output In Position Ind. (C.S.) Low Lights LED
18 BRLD/ Output Buffer Request Ind. Low Lights LED
19 ERLD/ Output Fatal Follow Err (C.S.) Low Lights LED
20 WIPER Input Feed Pot Wiper 0 TO +10V input
must use E72, E73
(CHA4)
21 (SPARE) N.C.
22 HWCB Input Handwheel Enc. B Channel 5V TTL SQ. pulse
must use E22 (CHB2)
23 F1LD/ Output Warn Follow Err (C.S.) Low Lights LED
24 F2LD/ Output Watchdog Timer Low Lights LED
25 +5V Output +5V Power For remote panel
38 Connector Pinouts
The JPAN connector can be used to connect the Accessory 16 (Control Panel), or customer-provided I/O,
to the PMAC, providing manual control of PMAC functions via simple toggle switches. If the automatic
control panel input functions are disabled (I2=1), the inputs become general-purpose TTL inputs, and the
coordinate system (C.S.) specific outputs pertain to the host-addressed coordinate system.
See Also:
Control panel inputs, Accessories: ACC-16, ACC-39
I-variables: I2, Ixx06
J3 (JTHW): Multiplexer Port Connector
J3 JTHW (26-PIN
CONNECTOR)
Front View

3 DAT0 Input Data-0 Input Data input from multiplexed
accessory
4 SEL0 Output Select-0 Output Multiplexer select output
accessory
accessory
accessory
accessory
accessory
accessory
accessory
19 N.C. N.C. No Connection
21 BRLD/ Output Buffer Request Low is “BUFFER REQ.”
23 IPLD/ Output In Position Low is “IN POSITION”
25 +5V Output +5VDC Supply Power supply out
26 INIT/ Input PMAC Reset Low is “RESET”
The JTHW multiplexer port provides 8 inputs and 8 outputs at TTL levels. While these I/O can be used in
unmultiplexed form for 16 discrete I/O points, most users will utilize PMAC software and accessories to
use this port in multiplexed form to greatly multiply the number of I/O that can be accessed on this port.
In multiplexed form, some of the SELn outputs are used to select which of the multiplexed I/O are to be
accessed.
See also:
I/O and Memory Map Y:$FFC1
Suggested M-variables M40 - M58
M-variable formats TWB, TWD, TWR, TWS
ACC-8D Opt 7, ACC-8D Opt 9, ACC-18, ACC-34x, NC Control Panel
J4 (JRS232) Serial Port Connector
J4 JRS232 (10-PIN CONNECTOR)
Front View

1 PHASE Output Phasing Clock
2 DTR Bidirect Data Term Rdy Tied to “DSR”
3 TXD/ Input Receive Data Host transmit data
4 CTS Input Clear to Send Host ready bit
5 RXD/ Output Send Data Host receive data
6 RTS Output Req. to Send PMAC ready bit
7 DSR Bidirect Data Set Ready Tied to “DTR”
8 SERVO Output Servo Clock
The JRS232 connector provides the PMAC2-PC with the ability to communicate serially with an RS232
port. E107 and E108 must connect pins 1 and 2 to use this connector. This connector cannot be used for
daisychain interconnection of multiple PMACs – the J4A RS422 connector must be used for
daisychaining.
J4A (JRS422): Serial Port Connector
J4A JRS422 (26-PIN CONNECTOR)
Front View

1 CHASSI Common PMAC Common
2 S+5V Output +5VDC Supply Deactivated by “E8”
3 RD- Input Receive Data Diff. I/O LOW TRUE= **
4 RD+ Input Receive Data Diff. I/O HIGH TRUE *
5 SD- Output Send Data Diff. I/O LOW TRUE **
6 SD+ Output Send Data Diff. I/O HIGH TRUE *
7 CS+ Input Clear to Send Diff. I/O HIGH TRUE **
8 CS- Input CLEAR TO Send Diff. I/O LOW TRUE *
9 RS+ Output Req. to Send Diff. I/O HIGH TRUE **
10 RS- Output Req. to Send Diff. I/O LOW TRUE *
11 DTR Bidirect Data Term Read Tied to “DSR”
12 INIT/ Input PMAC Reset Low is “RESET”
13 GND Common PMAC Common **
14 DSR Bidirect Data Set Ready Tied to “DTR”
15 SDIO- Bidirect Special Data Diff. I/O LOW TRUE
16 SDIO+ Bidirect Special Data Diff. I/O HIGH TRUE
17 SCIO- Bidirect Special CTRL. Diff. I/O LOW TRUE
18 SCIO+ Bidirect Special CTRL. Diff. I/O HIGH TRUE
19 SCK- Bidirect Special Clock Diff. I/O LOW TRUE
20 SCK+ Bidirect Special Clock Diff. I/O HIGH TRUE
21 SERVO- Bidirect Servo Clock Diff. I/O LOW TRUE ***
22 SERVO+ Bidirect Servo Clock Diff. I/O HIGH TRUE ***
23 PHASE- Bidirect Phase Clock Diff. I/O LOW TRUE ***
24 PHASE+ Bidirect Phase Clock Diff. I/O HIGH TRUE ***
The JRS422 connector provides the PMAC with the ability to communicate both in RS422 and RS232. In
addition, this connector is used to daisychain interconnect multiple PMACs for synchronized operation.
Jumpers E107 and E108 must connect pins 2 and 3 to use this port.
* Note: Required for communications to an RS-422 host port
** Note: Required for communications to an RS-422 or RS-232 host port
*** Note: Output on card @0; input on other cards. These pins are for synchronizing multiple PMACs
together by sharing their phasing and servo clocks. The PMAC designated as card 0 (@0) by its jumpers
E40-E43 outputs its clock signals. Other PMACs designated as cards 1-15 (@1-@F) by their jumpers
E40-E43 take these signals as inputs. If synchronization is desired, these lines should be connected even if
serial communications is not used.
See Also:
Serial Communications
Synchronizing PMAC to other PMACs
J5 (JOPTO): I/O Port Connector
J5 JOPTO (34-PIN CONNECTOR)
Front View

1 MI8 Input Machine Input 8 Low is TRUE
17 MO8 Output Machine Output 8 Low-TRUE (SINKING);
High-TRUE (SOURCING)
19 MO7 Output Machine Output 7 “ “
33 +V Input/ +V Power I/O +V = +5V TO +24V
Output +5V out from PMAC, +5 TO
+24V in from external source,
diode isolation from PMAC
This connector provides means for 8 general purpose inputs and 8 general purpose outputs. Inputs and
outputs may be configured to accept or provide either +5 volt or +24 volt signals. Outputs can be made
sourcing with an IC (U11 to UDN2981) and jumper (E1 & E2) change. E7 controls whether the inputs are
pulled up or down internally. Outputs are rated at 100mA per channel.
J6 (JXIO): Auxiliary I/O Port Connector
J6 JXIO (10-PIN CONNECTOR)
Front View

1 CHA1 Input Enc. A CH. Pos. From ACC-14 board
2 CHB1 Input Enc. B CH. Pos. From ACC-14 board
3 CHC1 Input Enc. C CH. Pos. From ACC-14 board
4 CHA3 Input Enc. A CH. Pos. From ACC-14 board
5 CHB3 Input Enc. B CH. Pos. From ACC-14 board
6 CHC3 Input Enc. C CH. Pos. From ACC-14 board
7 E63 Input Interrupt IR4 From ACC-14 board
8 E59 Input Interrupt IR5 From ACC-14 board
9 SCLK Output Encoder Clock To ACC-24, ACC-8D OPT 8 boards
10 DCLK Output D to A, A to D Clock To ACC-24 board
This connector is used for miscellaneous I/O functions related to expansion cards which are used with
PMAC.
J7 (JS1): A/D Port Connector
J7 JS1 (16-PIN HEADER)
Front View

1 DCLK Output D to A, A to D Clock DAC and ADC clock for
Chan. 1, 2, 3, 4
2 BDATA1 Output D to A Data DAC data for Chan. 1, 2, 3, 4
3 ASEL0/ Output Chan. Select Bit 0 Select for Chan. 1, 2, 3, 4
4 ASEL1/ Output Chan. Select Bit 1 Select for Chan. 1, 2, 3, 4
5 CNVRT01 Output A to D Convert ADC convert sig. Chan. 1, 2,
3, 4
6 ADCIN1 Input A to D Data ADC data for Chan. 1, 2, 3, 4
7 OUT1/ Output Amp. Enable/Dir Amp. Enable/Dir for Chan. 1
11 HF41 Input Amp. Fault Amp Fault Input for Chan. 1
15 +5V Output +5V Supply Power supply out
ACC-28A/B connection; digital amplifier connection.
J8 (JEQU): Position-Compare Connector
J8 JEQU (10-PIN CONNECTOR)
Front View

1 EQU1/ Output Enc. 1 Comp-EQ Low is TRUE
2 EQU2/ Output Enc. 2 Comp.-EQ Low is TRUE
5 AENA1/ Output Amp. Enable 1 Low is TRUE
9 A+V Supply Power Supply +5V to +24V
10 AGND Common Analog Ground
This connector provides the position-compare outputs and the amplifier enable outputs for the four servo
interface channels. The board is shipped by default with a ULN2803A or equivalent open-collector driver
IC. It may be replaced with UDN2891A or equivalent open-emitter driver (E101 and E102 must be
changed; see E-Point Descriptions for details), or a 74ACT563 or equivalent 5V CMOS driver.
J11 (JMACH1): Machine Port Connector
J11 JMACH1 (60-

PIN HEADER)

1 +5V Output +5V Power For encoders, 1
2 +5V Output +5V Power For encoders, 1
3 GND Common Digital Common
4 GND Common Digital Common
5 CHC3 Input Encoder C CH. POS 2
7 CHC3/ Input Encoder C CH. NEG 2,3
9 CHB3 Input Encoder B CH. POS 2
11 CHB3/ Input Encoder B CH. NEG 2,3
13 CHA3 Input Encoder A CH. POS 2
15 CHA3/ Input Encoder A CH. NEG 2,3
29 DAC3 Output Analog out Pos. 3 4
30 DAC4 Output Analog out Pos. 4 4
31 DAC3/ Output Analog out Neg. 3 4,5
32 DAC4/ Output Analog out Neg. 4 4,5
33 AENA3/DIR3 Output Amp-Ena/Dir. 3 6
35 FAULT3 Input Amp-Fault 3 7
37 +LIM3 Input Neg. End Limit 3 8,9
39 -LIM3 Input Pos. End Limit 3 8,9
J11 JMACH1 (60-

PIN HEADER)
(Continued)

41 HMFL3 Input Home-Flag 3 10
43 DAC1 Output Analog Out Pos. 1 4
44 DAC2 Output Analog Out Pos. 2 4
45 DAC1/ Output Analog Out Neg. 1 4,5
46 DAC2/ Output Analog Out Neg. 2 4,5
57 FEFCO/ Output Fe/Watchdog Out Indicator/Driver
58 AGND Input Analog Common
59 A+15V/OPT+V Input Analog +15V Supply
60 A-15V Input Analog -15V Supply
J11 JMACH1 (60-

PIN HEADER)
(Continued)
The J8 connector is used to connect PMAC to the first 4 channels (Channels 1, 2, 3, and 4) of servo amps,
flags, and encoders.
Note 1: In standalone applications, these lines can be used as +5V power supply inputs to power PMAC’s
digital circuitry. However, if a terminal block is available on your version of PMAC, it is preferable to
bring the +5V power in through the terminal block.
Note 2: Referenced to digital common (GND). Maximum of + 12V permitted between this signal and its
complement.
Note 3: Leave this input floating if not used (i.e. digital single-ended encoders). In this case, jumper (E18
- 21, E24 - 27) for channel should hold input at 2.5V.
Note 4: + 10V, 10mA max, referenced to analog common (AGND).
Note 5: Leave floating if not used; do not tie to AGND. In this case AGND is the return line.
Note 6: Functional polarity controlled by jumper(s) E17. Choice between AENA and DIR use controlled
by Ix02 and Ix25.
Note 7: Functional polarity controlled by variable Ix25. Must be conducting to 0V (usually AGND) to
produce a ‘0’ in PMAC software. Automatic fault function can be disabled with Ix25.
Note 8: Pins marked -LIMn should be connected to switches at the positive end of travel. Pins marked
+LIMn should be connected to switches at the negative end of travel.
Note 9: Must be conducting to 0V (usually AGND) for PMAC to consider itself not into this limit.
Automatic limit function can be disabled with Ix25.
Note 10: Functional polarity for homing or other trigger use of HMFLn controlled by Encoder/Flag
Variable 2 (I902, I907, etc.) HMFLn selected for trigger by Encoder/Flag Variable 3 (I903, I908, etc.).
Must be conducting to 0V (usually AGND) to produce a ‘0’ in PMAC software.
TB1 (JPWR): Power Supply

1 GND Common Reference Voltage
2 +5V Input Positive Supply Voltage Supplies all PMAC digital
circuits
3 +12V Input Positive Supply Voltage Ref to digital GND
4 -12V Input Negative Supply Voltage Ref to digital GND
This terminal block can be used to provide the input for the power supply for the circuits on the PMAC
board when it is not in a bus configuration. When the PMAC2 is in a bus configuration, these supplies
automatically come through the bus connector from the bus power supply; in this case, this terminal block
should not be used.
If you desire to keep the optical isolation between the digital and analog circuits on PMAC, you must
provide analog power (+/-12V to +/-15V & AGND) through the JMACH connector, instead of the bus
connector or this terminal block.
1 2 3 4 5 6 7 8
C64
+5V
1
U27
.1UF
8
RP39 0ohmSIP8I
2
4
1
3
J3 J3 (JTHW)
NOTE: THIS PART MUST BE `MAX202ECWE' A0 VCC GND
2 7 6 5
TO PROVIDE ÈSD' PROTECTION +5V A1 TEST 10KSIP10C 1 GND
10
10
3 6 8 7
A2 SCL 2
1
OF THE `RS232' INPUT SECTION. 4 5 RP24 DAT0 DAT0
VSS SDA R9 5K POT 3
C54 X24C16 (DIP8)
(IN SOCKET) 4.7KSIP10C
RP38 0ohmSIP8I
2
4
1
3 RP25
CW J1 J1 (JDISP)
SEL0
DAT1
SEL1
4
5
SEL0
DAT1
SEL1
Vdd DAT2 6 DAT2
6 5
GND 1 Vss SEL2 7 SEL2
.1UF 8 7
BRS 2 RS DAT3 8 DAT3
9
8
7
6
5
4
3
2
9
8
7
6
5
4
3
2
16
C58 C55 U28
U20 BD00 DISP1 3 Vee SEL3 9 SEL3
38 5 18 2
+5V BD00 BD01 D0 PA0 DISP0 - - BE 4 E DAT4 10 DAT4
37 4 17 3
VCC
BD01 BD02 D1 PA1 DISP3 - - BR/W 5 R/W SEL4 11 SEL4
RP20A .1UF 2 6 .1UF 36 3 16 4
+V V- BD02 D2 PA2 - - 6 12
1
3.3KSIP8I
2 PHASE+ C57
1
C1+ C2+
4
C56
J4 J4 (JRS232)
BD03
BD04
BD03
BD04
BD05
35
33
32
D3
D4
PA3
PA4
2
44
43
DISP2
DISP5
DISP4
15
14
13
- ( U32 ) -
- (SOL20) -
5
6
7
7
8
DB1
DB0
DB3
DAT5
SEL5
DAT6
13
14
DAT5
SEL5
DAT6
N.C. BD05 BD06 D5 PA5 DISP7 - - 9 DB2 SEL6 15 SEL6
RP20B .1UF 3 5 .1UF 31 42 12 8
C1- C2- 1 DTR BD06 BD07 D6 PA6 DISP6 - SEE NOTE 1 - 10 DB5 DAT7 16 DAT7
3 4 30 41 11 9
2 TXD- BD07 D7 PA7 - - 11 DB4 SEL7 17 SEL7
11 14 E09 1 2
3.3KSIP8I TXD TXD 3 CTS BRD- DATA_0 RESET 12 DB7 18 N.C.
6 20 C45 20 19
A
RP20C E107 1 RXD_232 12
RXD RXD
13 E10 1 2
4
5
RXD- BRD- BWR- 40
RD
WR
PB0
PB1
21 DATA_1 10
-
-
-
-
1 OUT_6 13
14
DB6 19
20
GND A
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
SERVO+ RXD RTS BWR- BA00 DATA_2 BFLD- BFLD-
5 6 2 10 22
RXD E107 RXD_422 6 DSR BA00 BA01 A0 PB2 DATA_3 .1UF 21 GND
3 10 7 E13 1 2 9 24
3.3KSIP8I RTS RTS 7 N.C. BA01 RESET A1 PB3 DATA_4 +5V GND C70 IPLD- 22 IPLD-
39 25
RP20D E108 1 CTS_232 9
CTS CTS
8 E14 1 2
8
9
GND RESET
CS00-
CS00- 7
RESET
CS
PB4
PB5
26 DATA_5 U33
.1UF
23
24
GND
7 8 CTS- 2 +5V 27 DATA_6 2 18 DAT0 +5V
VSS
CTS- E108 10 PB6 A1 B1 25 INIT-
3 CTS_422 28 DATA_7 3 17 DAT1 ADDED RP38 & RP39 RP31 RP32 INIT-
10
10
3.3KSIP8I PB7 A2 B2 DAT2 26
1
HEADER 10 4 16 10KSIP10C 10KSIP10C
JUMP 1 TO 2 FOR "RS232" USE MI1 A3 B3 DAT3
RP21A MAX202ECWE 16 5 15 +5V
15
PHASE- PC0 MI2 A4 B4 DAT4 GND GND
1 2 (SOL16) 17 6 14
JUMP 2 TO 3 FOR "RS422" USE PC1 MI3 A5 B5 DAT5
18 7 13
3.3KSIP8I +5V PC2 MI4 A6 B6 DAT6 +5V
19 8 12
PC3 MI5 A7 B7 DAT7
RP21B 15 9 11
PC4 MI6 A8 B8
10
3 4 29 14
VCC PC5
1
GND C63 13 MI7 RESET 19 20 C41
3.3KSIP8I SOCKET REQ'D PC6 MI8 OUT_4 G VCC
8 11 1 10 +5V
GND PC7 DIR GND
RP21C
5 6 SERVO- +5V .1UF 82C55A (PLCC44) 74AC245 .1UF 10KSIP10C RP26
3.3KSIP8I
GND (SOL20) GND
+5V J2 J2 (JPAN)
+5V
E7
9
8
7
6
5
4
3
2
RP21D U29 U34
1
7 8 BD08 38 5 2 18 +5V 1
BD08 BD09 D0 PA0 A1 B1 1 GND
RP1E RP1D RP3D RP1A RP3A RP3E 37 4 3 17 E7 2
3.3KSIP8I BD09 BD10 D1 PA1 A2 B2 2 FPD0-
10
3.3K 3.3K 3.3K 3.3K 3.3K 3.3K 36 3 4 16 3
D2 PA2 A3 B3 3
1
GND BD10 BD11 XJMI- RP33
35 2 5 15
BD11 BD12 D3 PA3 A4 B4 4 FPD1- 3.3KSIP10C
33 44 6 14
BD12 BD13 D4 PA4 A5 B5 5 XJPL-
6
32 43 7 13
BD13 D5 PA5 A6 B6 6
U21
+5V
GND
5
RP2C
6 2
RP2A
1
GND J4A J4A (JRS422)
BD14
BD15
BD14
BD15
31
30
D6
D7
PA6
PA7
42
41
8
9
A7
A8
B7
B8
12
11
7
8
PREJ-
STRT-
STEP- U38
J5 J5 (JOPT)
PHASE- CHASSI BRD- SEL_0 RESET 9 STOP- MI8 MI8
9
8
7
6
5
4
3
2
1 16 6 20 19 20 C42 18 2 1 2
IN-A VCC RX RX 1 S+5V BWR- RD PB0 SEL_1 OUT_2 G VCC 10 HOME- MI7 Y1 A1 1 GND
40 21 1 10 +5V 17 3 RP34 3 4
PHASE+ 2 RD- BA00 WR PB1 SEL_2 DIR GND 11 HOLD- MI6 Y2 A2 2 MI7
2 15 10 22 16 4 5 6
IN-A IN-B 3 RD+ BA01 A0 PB2 SEL_3 .1UF 12 FPD2- MI5 Y3 A3 3 GND
9 24 74AC245 15 5 10KSIP8I 7 8
PHA 4 SD- RESET A1 PB3 SEL_4 (SOL20) GND 13 FPD3- MI4 Y4 A4 4 MI6
3 14 39 25 14 6 1 2
PHA OUT-A IN-B 5 SD+ CS00- RESET PB4 SEL_5 INIT- 14 INIT- MI3 Y5 A5 5 GND
7 26 U35 13 7 RP35 3 4
RESET- RXD_422 6 CS+ CS PB5 SEL_6 SEL0 INIT- HWCA 15 HWCA MI2 Y6 A6 6 MI5
4 13 27 18 2 12 8 5 6
RESET- EN-A,C OUT-B 7 CS- PB6 SEL_7 B1 A1 SEL1 IPLD- 16 IPLD- MI2 MI1 Y7 A7 7 GND
28 17 3 11 9 10KSIP8I 7 8
SER 8 RS+ PB7 B2 A2 SEL2 BFLD- 17 BFLD- MI1 Y8 A8 8 MI4
5 12 16 4
SER OUT-C EN-B,D 9
10
RS-
PC0
16 MO1 15
B3
B4
A3
A4
5 SEL3
CHA2+
CHA2+ E23 1 E23 2 ERLD- 18
19
ERLD- C66 20
VCC G1
1
9
10
GND
SERVO+ 6 11 CTS_422 DTR 17 MO2 14 6 SEL4 WIPER WIPER 10 19 MI3
IN-C OUT-D INIT- 11 INIT- PC1 MO3 B5 A5 SEL5 20 (SPARE) GND G2 11 GND
18 13 7
SERVO- 7
IB-C IN-D
10
12
13
GND +5V PC2
PC3
19 MO4 12
B6
B7
A6
A7
8 SEL6
CHB2+
CHB2+ E22 1 E22 2 HWCB 21
22
HWCB .1UF 74AC540
12
13
MI2
DSR 15 MO5 11 9 SEL7 F1LD- F1LD- +5V GND (SOL20) GND GND
14 SDIO- PC4 MO6 B8 A8 F2LD- 23 F2LD- 14 MI1
8 9 29 14
GND IN-D 15 SDIO+ VCC PC5 MO7 RESET 24 +5V 15 GND
C62 13 C46 20 19
16 SCIO- PC6 MO8 VCC G OUT_5 25 GND 16 MO8
MC34C86D 8 11 10 1
(SO16) C59
17
18
SCIO+ GND PC7 GND DIR 26 E0 R10
D12
17
18
GND
SCK- .1UF 82C55A (PLCC44) .1UF 74AC245 1 2 MO7
19 SCK+ GND +5V GND GND E0 19 GND
(SOL20) 3.3K
B SERVO- 20 SERVO- 20 MO6 B
C69 .1UF MBRS140T3
SERVO+ 21 SERVO+ +5V (DIP20) 21 GND
GND +5V U22 U30 U26
PHAS PHASE- 22 PHASE- BD16 22 MO5
1 16 38 5 1 20
.1UF PHAS IN-A VCC PHASE+ 23 PHASE+ BD16 BD17 D0 PA0 MO8 1S VCC 23 GND
10
37 4 2 19
24 D1 PA1 1A 1Y 24
1
DSW0 PHASE+ TXD GND BD17 BD18 RP27 MO7 MO4
2 2 15 TXD 36 3 3 18
DSW1 OUT-A IN-B 25 +5V BD18 BD19 D2 PA2 DSW0 MO6 2A 2Y 25 GND
3 35 2 4 17
DSW2 PHASE- 26 BD19 BD20 D3 PA3 E51 DSW1 MO5 3A 3Y 26 MO3
4 U23 1 3 14 33 44 5 16
DSW3 OUT-A OUT-B BD20 BD21 D4 PA4 E50 10KSIP10C DSW2 MO4 4A 4Y 27 GND
5 HEADER 26 32 43 6 15
CARD0 GND BD21 BD22 D5 PA5 E49 DSW3 MO3 5A 5Y 28 MO2
13 4 13 31 42 7 14
(SO14) EN-A,C OUT-B BD22 BD23 D6 PA6 E48 MO2 6A 6Y 29 GND
9 30 41 8 13
SERVO- ENA422 BD23 D7 PA7 MO1 7A 7Y 30 MO1
9
8
7
6
5
4
3
2
10 5 12 9 12
OUT-C EN-B,D BRD- E40 8A 8Y 31 GND
10
11 74HC4078A 6 20 2 1 E40 10 11
RD PB0 GND 2S 32
2
3
4
5
6
7
8
9
12 SERVO+ 6 11 BWR- 40 21 E41 2 1 E41 +V
OUT-C OUT-D BA00 WR PB1 E42 33 GND
10 22 2 1 E42 XOR8-PLUS153
SERV BA01 A0 PB2 E43 OR 34
7 10 9 24 2 1 E43
SERV IN-C OUT-D RESET A1 PB3 E44 ULN2803A C65
39 25 2 1 E44
RESET CS00- RESET PB4 E45 OR
8 9 7 26 2 1 E45
GND IN-D CS PB5 E46 UDN2981A .1UF
27 2 1 E46 3.3KSIP10C
PB6
1
E47 (IN-SOCKET)
1
MC34C87D 28 2 1 E47 (SIP SOCKET)
PB7 +5V +5V
(SO16) 2 1 E48 RP36
C60 3 WDO 16 U36 2 1 E49 SHOULD BE
Q9 PC0 RP28 25mill ETCH
.1UF 2N7002
SOT23 17 1 2 2 18 2 1 2 1 E50
PC1 A1 B1
2
EACLK
2
18 3 3 17 3 2 1 E51
PC2 A2 B2
GND
+5V
29
PC3
PC4
19
15
14
ENA422
INPOS
BFUL
4
5
6
4
5
6
A3
A4
B3
B4
16
15
14
4
5
6
RP29
10KSIP10C GND
E2 1
E2
3 E1 1
E1
3
VCC PC5 EROR A5 B5
C61 13 7 7 13 7
PC6 F1ER A6 B6
8 11 8 8 12 8 D13 F1
GND PC7 A7 B7
10 9 9 11 9 10
+5V .1UF A8 B8
82C55A (PLCC44) 10KSIP10C
GND RESET 19 20 C44 1SMC33AT3 2AMP_FUSE
OUT_3 G VCC
10
1 10 +5V
DIR GND
1
RP23
C68 74AC245 .1UF
GND +5V (SOL20) GND GND
4.7KSIP10C
.1UF
U25D
9
8
7
6
5
4
3
2
U31
OUT_6 9 8 OUT_6- 2 18 BR/W
OUT_7- 1A1 1Y1 BE
4 16
OUT_8- 1A2 1Y2 BRS
6 14
1A3 1Y3
74AC14 8 12
R/W 1A4 1Y4
(SO14) 11 9
E 2A1 2Y1 IPOS
U25E 13 7 IPOS
RS 2A2 2Y2 BFUL
15 5 BFUL
OUT_7 2A3 2Y3 EROR
11 10 17 3 EROR
2A4 2Y4 F1ER
F1ER
1 20 C43 NOTE 1:
1G VCC
74AC14 19 10 +5V
2G GND
C (SO14) 74AC245 OPTION C
U25F 74ACT241 .1UF
(SOL20) +5V NOT AVAILABLE
OUT_8 13 12
E109
10
1
E109 RP30 18 2
B1 A1
74AC14 2 1 17 3
B2 A2
(SO14) 16 4
E 10KSIP10C B3 A3
15 5
E GND B4 A4
14 6
B5 A5
U37A 13 7
B6 A6
9
8
7
6
5
4
3
2
12 8
INPOS IPLD- B7 A7
1 2 11 9
B8 A8
SN7406N 20 19
(DIP14) VCC G
10 1
GND DIR
U37B
74AC245
BFUL 3 4 BFLD- (SOL20) U32
-11V R8 +11V
SN7406N
50K POT (DIP14)
12 TURN U37C
CW
EROR 5 6 ERLD-
R6 SN7406N
(DIP14)
RP22D 1M
U37D
7 8 C51
F1ER 9 8 F1LD-
10KSIP8I C50
RP22A 2200PF SN7406N
WIPER 1 2 6 - U44 CK05 .1UF (DIP14)
R5
7 1 14 U37E
10KSIP8I U24B IIN INCOM
5 +
56.2K
RP22B 2 13 WDO 11 10 F2LD-
LF453CM VIN AGND WDO
3 4 (SO8)
3 12 +5V SN7406N
10KSIP8I +5VO VOUT (DIP14)
4
-VS COMP
11 E28
1
U37F
5 10 R7 2 13 12 FEFC-
ENA +VS E28 FEFC-
Q5 1K 3
1
2N7002 6 9 U25B SN7406N

COS N.C. (DIP14)
3 7 8 3 4 FOUT- C67
DGND FOUT FOUT-
SOT23 GND +5V
2
VFC110
C47 C48 (DIP14) C49 74AC14 .1UF
D (IN-SOCKET) (SO14) D
330PF .1UF .1UF
CK05
C52
+11V
OUT_2
GND OUT_2
.1UF
SIGN- OUT_3
SIGN- OUT_3
8
RP22C U25A OUT_4

OUT_4
5 6 3
+ R66 OUT_5
1 1 2
10KSIP8I U24A OUT_5
2 10K
- OUT_6
LF453CM OUT_6
(SO8) 74AC14
OUT_7 DELTA TAU DATA SYSTEMS, Inc.
4
(SO14)
OUT_7
C53 OUT_8
OUT_8 Title
-11V
UNIVERSAL-PMAC-LITE, (I/O SECTION)
.1UF
GND Size Document Number Rev
D -
402-5SH2.SCH 602402-325
Date: Tuesday, September 28, 1999 Sheet 2 of 5
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
P1A
SA00
31 SA01 +5V +5V
30 SA02
29 RP40
SA03 MEMR- 2 1
28 SA04 MEMW-
27 3
SA05 SIOR- 4
26 SA06 SIOW-
25 5
5
SA07 SMEMR- 6
24 (SOT23-5)
SA08 NC7SZ125M5 SMEMW- 7
23
22
SA09 IRQ2 2 E86 1 R11 4 2 BALE 8
SA10 +5V U43 SBHE-
21 33 47KSIP10C 9 10
SA11
10
20 47KSIP10C
1
SA12 IRQ3 2 E81 RP42
10
19 1 R12
1
SA13
1
3
18 470 RP41
SA14 INT- 2 1
17
2 E82
A A
SA15 RP44 IRQ4 1 C167 PULLUP1 3
16 SA16 PC_CLK
15 10KSIP10C 4
SA17 AEN 5
14 SA18 IRQ5 2 E83 .1UF IOCHRDY
9
8
7
6
5
4
3
2
13 1 6
SA19 MEMCS16-
9
8
7
6
5
4
3
2
12 7
11
AEN XIN_1 QL_1-
QL_1- 1 E71 2 DSW04 PC_RST 8
10
IOCHRDY IRQ7 2 E84 1 PINIT- 9 10
9
SD00 XIN_2 QL_2-
QL_2- 1 E70 2 DSW05
47KSIP10C
SD01
8
7
SD02 XIN_3 QL_3-
QL_3-
IRQ10 2 E80 1 1 E69 2 DSW06
SD03
6
5
SD04 XIN_4 QL_4-
QL_4- 1 E68 2 DSW07
4
SD05 IRQ11 2 E79 1
3
SD06 XIN_5 TBD_0 1 E67 2 DSW08
SD07
2
1
XIN_6 TBD_1 IRQ12 2 E78 1 1 E66 2 DSW09
PC-HEADER A31 XIN_7 PWR_GUD-

PWR_GUD- 1 E92 2 DSW10
IRQ14 2 E77 1
P1B 1 E91 2 DSW11
31 GND
30 HDB00
HDB00 IRQ15 2 E76 1 DSW12
+5V HDB01 DSW13
29 BALE HDB01 HDB02 DSW14
28 HDB02 HDB03 DSW15
27 HDB03 HDB04
26 IRQ3 HDB04 HDB05
25 IRQ4 HDB05 HDB06 GND
24 IRQ5 HDB06 HDB07 U25C
23 HDB07
22 IRQ7 HREQ-
21 6 5 HREQ-
PC_CLK
20 GND
19
U40 (SOL20) C106 74AC14
18 OEL- IPOS
1 10 +5V (SO14) IPOS
17 LBEN- DIR GND BFUL
19 20 U68 BFUL
16 G VCC .1UF HDB00 EROR
15 11 D0 IR0 18 EROR
B SIOR- SD00 9 11 HDB00 HDB01 10 19 F1ER B
14 A8 B8 D1 IR1 F1ER
SIOW- SD01 8 12 HDB01 HDB02 9 20
13 SMEMR- SD02 A7 B7 HDB02 HDB03 D2 IR2
12 7 A6 B6 13 8 D3 IR3 21
SMEMW- SD03 6 14 HDB03 HDB04 7 22
11 A5 B5 D4 IR4
10 GND SD04 5 A4 B4 15 HDB04 HDB05 6 D5 IR5 23 1 E65 2 EQU1
EQU1
+12V SD05 4 16 HDB05 HDB06 5 24
9 SD06 A3 B3 HDB06 HDB07 D6 IR6
8 3 A2 B2 17 4 D7 IR7 25
7 -12V SD07 2 A1 B1 18 HDB07 1 E63 2 E63
E63
BSA00 27
6 GND ICS- A0
74ALS245 1
5 CS
4
IRQ2 U41 (SOL20) C107 OEL- 3 RD 1 E62 2 MI1
MI1
+5V 1 10 +5V IWR- 2
3 PC_RST HLBEN- DIR GND WR
2 19 G VCC 20 16 SP/EN CAS0 12
GND .1UF INT- 17 13
1 SD00 HDB08 INT CAS1
9 A8 B8 11 26 INTA CAS2 15
PC-HEADER B31 SD01 8 A7 B7 12 HDB09 1 E61 2 EQU2
EQU2
SD02 7 13 HDB10 82C59A
SD03 A6 B6 HDB11
P2C 6 14 (PLCC28)
A5 B5
1
SBHE- SD04 5 A4 B4 15 HDB12 1 E59 2 E59
E59
LA23 SD05 4 16 HDB13
2 LA22 SD06 A3 B3 HDB14
3 3 A2 B2 17
4
LA21 SD07 2 A1 B1 18 HDB15 1 E58 2 MI2
MI2
LA20
5 GND
74ALS245
6
U42 (SOL20) C108
7
8 1 DIR GND 10 +5V
9
MEMR- HBEN- 19 G VCC 20 1 E57 2 EQU3
EQU3
MEMW- .1UF
10 SD08 HDB08
11 9 A8 B8 11
12
SD09 8 A7 B7 12 HDB09 1 E55 2 EQU4
EQU4
SD10 7 13 HDB10
13 SD11 A6 B6 HDB11
14 6 A5 B5 14
15
SD12 5 A4 B4 15 HDB12 +5V 1 E54 2 WDO
WDO
9
8
7
6
5
4
3
16
SD13 4 A3 B3 16 HDB13 2
SD14 3 17 HDB14 RP43
17 SD15 A2 B2 HDB15
18 2 A1 B1 18 4.7KSIP10C
PC-HEADER C18 74ALS245
4
C U48A C
10
P2D BSA01
1
2 5
PR
MEMCS16- D Q
1 GND
2 3 CLK
IRQ10
3 IRQ11 6
CL
4 IRQ12 Q
5 IRQ15 74LS74
6 IRQ14
1
7
8 PINIT-
9
10
11
12
13
10
14 U48B
15 BSA02 12 9 1 E93 2
PR
16 +5V D Q
17
18 GND TP3 11 CLK 1 E39 2
+11V D14
PC-HEADER D18 8 1 E94 2 3 1 INIT-
CL
Q
C168 M1 D16 74LS74 MMBD301LT1
13
+12V +11V
.1UF HOLE MBRS140T3
TP4
1
C169 M2 + C2 -11V
22UF Q6
35V PC_RST 3 2N7002
.1UF HOLE D17 SOT23
2
-12V -11V
C170 M3
MBRS140T3 C3 GND
+ TP2
.1UF HOLE 22UF +5V
D 35V D
C171 M4
+5V +5V
.1UF HOLE
SBHE-
GND LA23
(JPWR) LA22 GND
TB1 D15 + C1
-12V 22UF TP1 THIS DOCUMENT IS THE CONFIDENTIAL PROPERTY OF DELTA TAU DELTA TAU DATA SYSTEMS, Inc.
+12V 4 35V DATA SYSTEMS INC. AND IS LOANED SUBJECT TO RETURN UPON
1SMC5.0AT3 GND
+5V 3 DEMAND. TITLE TO THIS DOCUMENT IS NEVER SOLD OR GND
GND 2 TRANSFERRED FOR ANY REASON. THIS DOCUMENT IS TO BE USED Title
1 ONLY PURSUANT TO WRITTEN LICENSE OR WRITTEN INSTRUCTIONS UNIVERSAL-PMAC-LITE, opt#2 DUAL-PORT-RAM
TERMBLK 4 OF DELTA TAU DATA SYSTEMS INC. ALL RIGHTS TO DESIGNS AND
GND GND
.150 PITCH INVENTIONS ARE RESERVED BY DELTA TAU DATA SYSTEMS INC. Size Document Number Rev
POSSESSION OF THIS DOCUMENT INDICATES ACCEPTANCE OF THE C -
ABOVE AGREEMENT. 402-5SH3.SCH 602402-325
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+5V
"DGND" PLANE
`DGND' GND +5V (JMACH1)
J11
+5V GND CHA1+
CHB1+
J6 (JXIO)
1
2
CHA1+
CHB1+
CHC1+ CHC1+
10
10
1 2 3
1
È27,E26,E25,E24' CHA3+ CHA3+
CHC3+ 3 4 CHC4+ CHB3+ 4 CHB3+
`SING' ENCODER = 1-TO-2 CHC3- 5 6 CHC4- CHC3+ 5 CHC3+
U50 RP59 RP61
CHA1- `DIFF' ENCODER = 2-TO-3 CHB3+ 7 8 CHB4+ E63 6 E63
16 1 2.2KSIP10C 1KSIP10C
VCC IN-A CHB3- 9 10 CHB4- E63 E59 7 E59
ENC_A1 3
OUT-A IN-A
2 CHA1+ 3 E27 RP55
RP51 CHA3+ 11
13
12
14
CHA4+ E59 SCLK 8
9
SCLK
CHA1- CHA1+ CHA3- CHA4- DCLK
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
2 1 2 1 2
E27 CHB1- CHB1+ CHC1+ 15 16 CHC2+ 10
4 1 3 4 3 4
ENA-A,C CHC1- CHC1+ CHC1- 17 18 CHC2-
5 6 5 6 HEADER 10
ENC_A2 CHA2+ QL_ENA1 CHB1+ 19 20 CHB2+
5 6 7 8
OUT-C IN-C CHB1- 21 22 CHB2- +5V
2.2KSIP8I 220SIP6I
IN SIP SOCKET 23 24
7 CHA2- CHA1+ CHA2+ J7 (JS1)
IN-C CHA1- 25 26 CHA2- DCLK DCLK
IN-B
15 CHA3- 3 E26 RP52 DAC03+ 27
29
28
30
DAC04+
DAC04+
BDATA1 1
2
BDATA1
5
RP56 CHA2- CHA2+ DAC03+ DAC03- DAC04- U65 ASEL0- ASEL0-
2 1 2 1 2 DAC04-
ENC_A3 CHA3+ E26 CHB2- CHB2+ DAC03- AENA3/DIR3 31 32 AENA4/DIR4 ASEL1- 3 ASEL1-
13 14 1 3 4 3 4 AENA4/DIR4 1
OUT-B IN-B CHC2- CHC2+ AENA3/DIR3 FAULT3 33 34 FAULT4 ADCVRT01- CNVRT01 4 CNVRT01
5 6 5 6 4
QL_ENA2 MLIM3 35 36 MLIM4 ADCIN1 5 ADCIN1
12 7 8 2
A ENA-B,D PLIM3 37 38 PLIM4 OUT1- 6 OUT1- A
2.2KSIP8I 220SIP6I C17
ENC_A4 CHA4+ HMFL3 39 40 HMFL4 OUT2- 7 OUT2-
11 10 NC7SZ00M5
OUT-D IN-D DAC01+ 41 42 DAC02+ .1UF OUT3- 8 OUT3-
3
DAC01+ 43 44 DAC02+ (SOT32-5) 9
8 9 CHA4- DAC01- DAC02- OUT4- OUT4-
GND IN-D DAC01- 45 46 DAC02- 10 HF4_1
AENA1/DIR1 AENA2/DIR2 HF4_1
10
10
47 48 AENA2/DIR2 11
1
AENA1/DIR1 FAULT1 FAULT2 HF4_2 HF4_2
MC34C86D (SO16)
MLIM1 49 50 MLIM2 GND HF4_3 12 HF4_3
C8 51 52 13
RP60 RP62 PLIM1 PLIM2 HF4_4 HF4_4
HMFL1 53 54 HMFL2 14 +5V
2.2KSIP10C 1KSIP10C 55 56 +5V 15
.1UF FEFCO- GND
GND
3 E25 RP57
RP53
FEFCO- 57
59
58
60
16
CHA3- CHA3+
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
U51 2 1 2 1 2 HEADER 16
CHB1- E25 CHB3- CHB3+
16 1 1 3 4 3 4 HEADER 30X2
VCC IN-A
5 6 CHC3- 5 6 CHC3+ ÀGND' ÀGND' BD00
BD00
ENC_B1 3 2 CHB1+ QL_ENA3 7 8 A+15V A-15V AGND BD01
OUT-A IN-A BD01
220SIP6I BD02
2.2KSIP8I IN SIP SOCKET BD02
4 BD03
ENA-A,C BD03
BD04
BD04
ENC_B2 5
OUT-C IN-C
6 CHB2+ 3 E24 RP58
RP54 BD05
BD05
2 1 2 CHA4- 1 2 CHA4+ BD06
E24 BD06
7 CHB2- 1 3 4 CHB4- 3 4 CHB4+ BD07
IN-C BD07
5 6 CHC4- 5 6 CHC4+ BD08
BD08
15 CHB3- QL_ENA4 7 8 BD09
IN-B BD09
220SIP6I BD10
2.2KSIP8I BD10
ENC_B3 13 14 CHB3+ GND BD11
OUT-B IN-B BD11
BD12
BD12
12 BD13
ENA-B,D BD13
BD14
È-POINTS' SHOULD BE IN ORDER AS SHOWN BD14
ENC_B4 11 10 CHB4+ BD15
OUT-D IN-D BD15
BD16
GUARD BAND BD16
8 9 CHB4- BD17
GND IN-D BD17
BD18
BD18
MC34C86D (SO16) BD19
E34A BD19
C9 U53 19.6608Mhz 1 2 E34A BD20
E34 BD20
1 3 9.8304Mhz 1 2 E34 +5V BD21
19.6608Mhz CLK_1 QA_1 E35 BD21
4 4.9152Mhz 1 2 E35 BD22
QB_1 E36 R23 BD22
.1UF 5 2.4576Mhz 1 2 E36 BD23
QC_1 E37 BD23
2 6 1.2288Mhz 1 2 E37
CLR_1 QD_1 E38 10K
U52 ENC_C4 1 2 E38 U64
16 1 CHC1- 13 11 16 BA00
VCC IN-A CLK_2 QA_2 E33 VCC BA00
10 36.14Khz 1 2 E33 1 BA01
QB_2 E32 BA01
ENC_C1 3 2 CHC1+ 9 18.07Khz 1 2 E32 2 DCLK DACOUT1 1 2 BDATA1 BA02
DCLK BA02
OUT-A IN-A
12
CLR_2
QC_2
QD_2
8 9.035Khz 1 2 E31 E31 E98 3
E98 IN-A OUT-A BA03
BA03
4 4.53Khz 1 2 E30 E30 3
ENA-A,C 2.26Khz E29 OUT-A BX/Y
7 14 1 2 E29 4 BX/Y
GND VCC EN-A,C
ENC_C2 5 6 CHC2+ SCLK
SCLK 5 1 E73 2 CHB4+ BWR-
BWR_
OUT-C IN-C OUT-C BRD_
74HCT393 BRD_
7 CHC2- (SO14) C11 +5V SIGN- 7 6 1 E72 2 CHA4+
IN-C SIGN- IN-C OUT-C BA12
U63 BA12
15 CHC3- 1 20 FOUT- 15 14 BA13
B IN-B PHASE SELECT CLOCK VCC FOUT- IN-B OUT-B BA13 B
.1UF 2 19 PHAS
E3 PHASEB PHASE PHAS
ENC_C3 13 14 CHC3+ GND +5V 1 2 E3 3 18 SERV 13 CS2-
OUT-B IN-B E4 S0 SERVO SERV OUT-B CS2-
1 2 E4 4 17 12 CS3-
S1 Q0 EN-B,D CS3-
12 ASEL0 E5 1 2 E5 5 16 C15 11 1 E74 2 CHC4-
ENA-B,D E6 S2 Q1 OUT-D PHA
1 2 E6 6 15 PHA
S3 Q2 .1UF
ENC_C4 11 10 CHC4+ BWR- 7 14 SCLK 9 10 1 E75 2 CHC4+ SER
SER
OUT-D IN-D BWR- BRD- WR Q3 E IN-D OUT-D
8 13 E
CHC4- BRD- BA02 RD E CS00-
8 9 9 12 CS00- 8
GND IN-D BA02 A2 CS16 GND
10 11 C16
MC34C86D (SO16)
GND ENA
MC34C87D "DGND" PLANE
2
3
4
5
6
7
8
9
C10 SCLOCK-G16V8A (SO16)
RP50 (DIP20) .1UF
(IN SOCKET) GND
10KSIP10C
.1UF
+5V GND
È-POINTS' SHOULD BE IN ORDER AS SHOWN GND
10
1
+5V
"DGND" PLANE "AGND" PLANE

+5V
10
RP63 AMP+V U59A

10KSIP10C 1 U60A
E90_PIN2 3 1
E90_PIN2 (SO14)
2 3
(SO14)
CHA1+ 1 RP77
9
8
7
6
5
4
3
2
U55 2 2
HF1_1 16 1 HMFL1 CHA1- 3 4 74AC86
C1 ACI1A RP65 CHB1+
15 2 1 2 5 6 74HC132
E1 ACI1B CHB1-
3 4 7 8 U59B
HF2_1 14 3 PLIM1 5 6 4 R15
C2 ACI2A 10KSIP8I
13 4 7 8 6 2.2K
E2 ACI2B (SO14)
5
HF3_1 MLIM1 4.7KSIP8I +5V
12 5 U60B
C3 ACI3A
11 6 1 RP66 2 74AC86 5
E3 ACI3B QL_1-
3 4 6 QL_1- U66
HF4_1 FAULT1 QL_ENA1 (SO14) ASEL0 ASEL0-
10 7 5 6 4 2 18 ASEL0-
C4 ACI4A ASEL1 A1 Y1 ASEL1-
9 8 7 8 C18 3 17 ASEL1-
E4 ACI4B EQU1 A2 Y2 EQU1-
+5V GND 74HC132 4 16 EQU1-
C RP67 4.7KSIP8I C19 EQU1 EQU2 A3 Y3 EQU2- C
PS2705-4NEC 2 1 C20 5 15 EQU2-
.1UF EQU2 EQU3 A4 Y4 EQU3-
(SMT16) 4 3 .1UF +5V GND 6 14 EQU3-
EQU3 EQU4 A5 Y5 EQU4-
6 5 7 13 EQU4-
EQU4 DCLK A6 Y6 DCLK-
8 7 U59C .1UF 8 12 EQU5-
GND RESET A7 Y7 RESET-
10 U60C 9 11 RESET-
1KSIP8I RESET A8 Y8
8 10
(SO14)
9 8 19 20
(SO14) G2 VCC
U56 CHA2+ 1 RP78 2 9 1 10
HF1_2 HMFL2 CHA2- G1 GND
16 1 3 4 74AC86
C1 ACI1A RP68 CHB2+
15 2 1 2 5 6 74HC132 R24 74ACT540
E1 ACI1B CHB2-
3 4 7 8 U59D 10K (SOL20)
HF2_2 14 3 PLIM2 5 6 13 R16
C2 ACI2A 10KSIP8I
13 4 7 8 11 2.2K C26
E2 ACI2B (SO14)
12
HF3_2 MLIM2 4.7KSIP8I
12 5 U60D
C3 ACI3A
11 6 1 RP69 2 74AC86 12 .1UF
E3 ACI3B QL_2- GND
3 4 11 QL_2-
HF4_2 FAULT2 QL_ENA2 (SO14)
10 7 5 6 13
C4 ACI4A +5V
9 8 7 8
E4 ACI4B
74HC132
+5V RP70 4.7KSIP8I C21
10
PS2505-4NEC 2 1
1
(DIP16) 4 3 .1UF
10
(IN SOCKET) 6 5
1
8 7 U61A
1 GND U62A RP81 3.3KSIP10C
1KSIP8I
RP64 3 1 C27
(SO14)
10KSIP10C 2 3 GND +5V
(SO14)
CHA3+ 1 RP79 ADCIN1
9
8
7
6
5
4
3
2
2 2
CHA3- 3 4 74AC86 .1UF
CHB3+
9
8
7
6
5
4
3
2
U57 5 6 74HC132 U67A

HF1_3 16 1 HMFL3 CHB3- 7 8 U61B 1 E17A 2 1
C1 ACI1A RP71 R17 OUT1-
15 2 1 2 10KSIP8I 4 3 OUT1-
E1 ACI1B OUT1 (SO14)
3 4 6 2.2K 2
HF2_3 PLIM3 (SO14)
14 3 5 6 5
C2 ACI2A
13 4 7 8 U62B 74ACT86
E2 ACI2B
74AC86 5
HF3_3 MLIM3 4.7KSIP8I QL_3-
12 5 6 QL_3- U67B
C3 ACI3A (SO14)
11 6 1 RP72 2 QL_ENA3 4 1 E17B 2 4
E3 ACI3B OUT2-
3 4 C22 6 OUT2-
HF4_3 FAULT3 OUT2 (SO14)
10 7 5 6 +5V GND 74HC132 5
C4 ACI4A C23
9 8 7 8 C24
E4 ACI4B .1UF
.1UF +5V GND 74ACT86
RP73 4.7KSIP8I
PS2705-4NEC 2 1
(SMT16) 4 3 U61C .1UF U67C
6 5 10 GND U62C OUT3 9
8 7 8 10 8 OUT3-
(SO14) (SO14) OUT3-
9 8 1 E17C 2 10
1KSIP8I (SO14)
CHA4+ 1 RP80 2 9
CHA4- 3 4 74AC86 74ACT86
U58 CHB4+ 5 6 74HC132
D HF1_4 16 1 HMFL4 CHB4- 7 8 U61D U67D D
C1 ACI1A RP74 R18 OUT4
15 2 1 2 10KSIP8I 13 12
E1 ACI1B OUT4-
3 4 11 2.2K 11 OUT4-
(SO14) (SO14)
HF2_4 14 3 PLIM4 5 6 12 1 E17D 2 13
C2 ACI2A
13 4 7 8 U62D
E2 ACI2B
74AC86 12 74ACT86
HF3_4 MLIM4 4.7KSIP8I QL_4- GND
12 5 11 QL_4-
C3 ACI3A (SO14)
11 6 1 RP75 2 QL_ENA4 13
E3 ACI3B
3 4
HF4_4 10 7 FAULT4 5 6 74HC132
C4 ACI4A C25
9 8 7 8
E4 ACI4B .1UF
PS2505-4NEC 2 RP76 1
4.7KSIP8I "DGND" PLANE
(DIP16) 4 3
GND (IN SOCKET) 6 5 GND
8 7 DELTA TAU DATA SYSTEMS, Inc.
1KSIP8I
Title
UNIVERSAL-PMAC-LITE, MACHINE I/O SECTION
Size Document Number Rev

"DGND" PLANE "AGND" PLANE "DGND" PLANE 402-5SH4.SCH D -
602402-325
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
"DGND" PLANE "AGND" PLANE "AGND" PLANE

3 +11V
E90_PIN2 2 FL1
E90_PIN2 E90
1 2 E89 1 A+15V
55FZ103N
A+5V
+5V
ODCLK+
C136
10
10
C128 SA+14V
1
ODATA1 .1UF
.1UF RP124A
U120 RP120A 1 2
RP110 RP112 1 16 1 2
VL VBL 330K
470SIP10C 470SIP10C 33KSIP8I
OSEL0+ 2 15
LL VS
4
C137 5 LF347M RP132A
ODATA1 LF347M +
2 DAC01+
9
8
7
6
5
4
3
2
2
3
4
5
6
7
8
9
U110 3 14 3 RP128A 7 1 DAC01+
DL VOL + U122B
1 8 C129 RP120B 1 1 2 6 220SIP8I
ANODE#1 VCC ODCLK+ U122A -
+
4 13 3 4 2 47KSIP8I (SO14)
CK NRL
8
BDATA1 -
2 7 U116A 33KSIP8I (SO14)
BDATA1 CATHODE#1 VO1
1 5 12 4.7UF RP128B
11
DCLK R25 FEFCO- DR AGND
3 6 (DIP8) 3 FEFCO- C130 3 4
A DCLK CATHODE#2 VO2 10K OSEL0- A
+
2 6 11 RP124B 47KSIP8I
LR NRR
4 5 3 4
ANODE#2 GND
C120 DS75452N C122 7 10 4.7UF R38 C138 RP132B
DGND VOR 330K
4 DAC01-
4
HCPL-0630 1MEG 3 DAC01-
(S08) 8 9 220SIP8I
VBR VS
.1UF U116B .1UF
U111 6 AD1866R (SOL16) C131 C139
SA-14V
1 8 (DIP8) 5 .1UF
ANODE#1 VCC .1UF
U115 7
ASEL0- 2 7 14 AGND
ASEL0- CATHODE#1 VO1 VDD
DS75452N
ASEL1- 3 6 1 2 (IN SOCKET) ODATA1-
ASEL1- CATHODE#2 VO2 IN1 OUT1
4 5 3 4 ODCLK-
ANODE#2 GND IN2 OUT2
C121
HCPL-0630 5 6 OSEL0+ R30 50K POT C140
IN3 OUT3
(S08) RP120C RP124C
.1UF 9 8 OSEL1+ R31 50K POT 5 6 5 6
IN4 OUT4
33KSIP8I 330K
11 10 10 LF347M RP132C
IN5 OUT5 LF347M +
U112 12 RP128C 8 5 6 DAC02+ DAC02+
+ U122C
1 4 13 12 14 5 6 9 220SIP8I
FEFC- ANO1 C1 IN6 OUT6 U122D -
2 3 13 47KSIP8I (SO14)
FEFC- CAT1 E1 -
7 C123 (SO14)
VSS
PS2701-1NEC RP120D RP124D RP128D
(SMT4) 74AC14 .1UF 7 8 7 8 7 8
+5V (SOL14) OSEL0-
33KSIP8I 330K 47KSIP8I
C141 RP132D
OSEL1- FA+5V R39
8 DAC02-
10
7 DAC02-
1
1MEG 220SIP8I
AGND
RP111
470SIP10C
A+5V
9
8
7
6
5
4
3
2
U113
1 16 AENA1/DIR1 C132 C142
ANO1 C1 AENA1/DIR1 SA+14V
EQU1- 2 15 .1UF
EQU1- CAT1 E1 .1UF RP125A
AENA2/DIR2 U121 RP121A 1 2
AENA2/DIR2
3 14 1 16 1 2
EQU2- ANO2 C2 AENA3/DIR3 VL VBL 330K
4 13 AENA3/DIR3 33KSIP8I
EQU2- CAT2 E2 OSEL1+ 2 15
LL VS
4
5 12 AENA4/DIR4 C143 5 LF347M RP133A
ANO3 C3 AENA4/DIR4 +
EQU3-
EQU3- 6
CAT3 E3
11
U54 J8 (JEQU)
ODATA1
ODCLK+
3
DL VOL
14
C133 RP121B
3
+
LF347M
U123A
1 1
RP129A
2 6
U123B
-
7 1
220SIP8I
2 DAC03+ DAC03+
+
7 10 U54 4 13 3 4 2 47KSIP8I (SO14)
EQU4- ANO4 C4 EQU1/ CK NRL -
8 9 1 18 33KSIP8I (SO14)
EQU4- CAT4 E4 IN1 OUT1/ 1 EQU2/
2 17 5 12 4.7UF RP129B
11
IN2 OUT2/ 2 EQU3/ DR AGND
PS2701-4NEC 3 16 C134 3 4
(SMT16) IN3 OUT3/ 3 EQU4/ OSEL1-
+
4 15 6 11 RP125B 47KSIP8I
B IN4 OUT4/ 4 AENA1/ LR NRR B
5 14 3 4
IN5 OUT5/ 5 AENA2/
U114 6 13 7 10 4.7UF R40 C40 RP133B
IN6 OUT6/ 6 AENA3/ DGND VOR 330K
1 16 7 12 1MEG 3 4 DAC03- DAC03-
OUT1- ANO1 C1 IN7 OUT7/ 7 AENA4/
2 15 8 11 8 9 220SIP8I
OUT1- CAT1 E1 IN8 OUT8/ 8 A+V VBR VS
9 10
GND V+ 9
3
ANO2 C2
14
10
10
AGND
J9 AD1866R (SOL16) C135 C144
SA-14V
2
3
4
5
6
7
8
9
OUT2- 4 13 ULN2803A .1UF
OUT2- CAT2 E2 .1UF
OR HEADER 10 J9 (JEXP)
2
5 12 UDN2981A RP113 BD00 BD01 AGND

OUT3- ANO3 C3 BD02 1 2 BD03
6 11 E102 (DIP18) E101
OUT3- CAT3 E3 BD04 3 4 BD05
1 3 (IN SOCKET) 1 3
BD06 5 6 BD07
7 10 3.3KSIP10C
OUT4- ANO4 C4 BD08 7 8 BD09
1
8 9 (SIP SOCKET)
OUT4- CAT4 E4 BD10 9 10 BD11
1 A+14V
BD12 11 12 BD13 R32 50K POT C145
PS2701-4NEC 2
(SMT16) E100 BD14 13 14 BD15
3 A+V RP121C RP125C
BD16 15 16 BD17
D18 D19 R33 50K POT 5 6 5 6
BD18 17 18 BD19
AMP+V 19 20 33KSIP8I 330K
BD20 BD21 10 LF347M RP133C
BD22 21 22 BD23 LF347M +
1SMC33AT3 MBRS140T3 12 RP129C 8 5 6 DAC04+ DAC04+
23 24 + U123C
AGND
BA04
E110 1 E110
BA00
BA02
25
27
26
28
BA01
BA03
13
U123D
-
14 5
47KSIP8I
6 9
-
(SO14)
220SIP8I
29 30 (SO14)
2 BX/Y RP121D RP129D
31 32 RP125D
CS02- 3 CS2- CS3- 7 8 7 8 7 8
CS04- 33 34 CS06-
NOTE: 35 36 33KSIP8I 330K 47KSIP8I RP133D
CS10- CS12- C146
CS14- 37 38 CS16- R41
7 8 DAC04- DAC04-
E101 O O
1 2
O
3
E101,E102 BA04 39
41
40
42
BA05
1MEG 220SIP8I
BWR- BRD-
MUST NUMBER IN THE 43 44
E102 O O O RESET 45
47
46
48
WAIT2-
SAME DIRECTION SER PHA
49 50
HEADER 25X2
GND GND
C C
"AGND" PLANE
RAISE R65 OFF BOARD
"DGND" PLANE
(ON HEATSINK)
TP7 WITH COPPER PAD
A+14V D25
A+14V A+15V
E85
MBRS140T3
+11V 1 E85 2 R65
(TO-220) 18 OHM
TP6 VR1 2.25W
A+5V LM7805T
A+5V 3 1
OUT IN
GND
+ C5 + C4 D26
22UF 22UF
C6 25V 25V
2
1SMC18AT3
TP5 1UF
AGND 50V
AGND AGND
E87
GND 1 E87 2 D28
+ C7
TP8 22UF 1SMC18AT3
A-14V 25V D27
A-14V A-15V
E88
MBRS140T3
-11V 1 E88 2
TP9 TP10
SA+14V SA-14V
A+5V
C125 3 R28
RP114A RP114B
ODCLK- 1 2 3 4 SA+14V 4 330 "DGND" PLANE
2.2KSIP8I 2.2KSIP8I
ANALOG-PWR 5 A+14V
.01UF
MMBD301LT1 GOOD-LED K1
10 R29
AGND
1 3 SA-14V 9 330 "AGND" PLANE
RP114C D21 8 A-14V
1
D20 5 6 +5V 1
D 12 D
2.2KSIP8I
3
(SOT23) 3 2 LED-GRN
FBR12ND05
RP114D
Q7 7 8
MMBT3906LT1
U117 D22 MMBD301LT1
2.2KSIP8I
1 14 U118
VREF VDD
1
2 13 1 8
GND OUT1 N.C. VCC
A+5V 3 12
+5V OUT2 R27 RESET-
4 11 2 7 RESET-
-5V OUT3 ANO VE
A+14V 5 10 330
+12V OUT4 PWR_GUD-
A-14V 6 9 3 6 PWR_GUD-
-12V DOUT CAT VOUT
7 8
DIN PGND
4
N.C. GND
5 "AGND" PLANE
1
MAX8215CSD C126
R26 C124 (SO14) C127 Q8 6N137 (DIP8) .1UF
3 2N7002 DELTA TAU DATA SYSTEMS, Inc.
100K .1UF .1UF SOT23
(SOT23)
2
GND Title
UNIVERSAL-PMAC-LITE, ANALOG OUTPUT SECTION
AGND Size Document Number Rev

"DGND" PLANE "AGND" PLANE "AGND" PLANE "DGND" PLANE "AGND" PLANE 402-5SH5.SCH D -
602402-325
1 2 3 4 5 6 7 8

Manual - PMAC-LITE Hardware Reference Manual

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Manual - PMAC-LITE Hardware Reference Manual

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Hardware Reference

Manual P/N 400-602402-363

Hardware Updates ...................................................................................................................................................... 4

E-POINT DESCRIPTIONS ..............................................................................................7

E1 - E2: Machine Output Supply Voltage Configure .............................................................................................. 7

E3 - E6: Servo Clock Frequency Control................................................................................................................. 8

E7: Machine Input Source/Sink Control.................................................................................................................. 9

E9, E10, E13, E14: Serial Interface Direction Control ........................................................................................... 9

E17A-D: Amplifier Enable/Direction Polarity Control ......................................................................................... 10

E22 - E23: Control Panel Handwheel Enable........................................................................................................ 10

E24 - E27: Encoder Single-Ended/Differential Control........................................................................................ 11

E28: Following Error/Watchdog Timer Signal Control....................................................................................... 11

E29 - E33: Phase Clock Frequency Control .......................................................................................................... 12

E34 - E38: Encoder Sampling Clock Frequency Control ..................................................................................... 12

E39: Reset-From-Bus Enable.................................................................................................................................. 13

E40 - E43: Servo and Phase Clock Direction Control .......................................................................................... 13

E44 - E47: Serial Baud Rate Control ..................................................................................................................... 14

E48: CPU Clock Frequency Control ...................................................................................................................... 15

E49: Serial Communications Parity Control ......................................................................................................... 15

E50: Non-Volatile Memory Save Control .............................................................................................................. 16

E51: Normal/Re-initializing Power-Up .................................................................................................................. 16

E54 - E65: Host Interrupt Signal Select ................................................................................................................. 17

E66 - E71: Bus Base Hardware Address (Low Bits) ............................................................................................. 18

E72 - E73: Panel Analog Time Base Signal Enable............................................................................................... 18

E74 - E75: Clock Output Control for Ext. Interpolation...................................................................................... 19

E76 - E84: Host Interrupt Signal Select ................................................................................................................. 20

E85: Host-Supplied Analog Power Source Enable................................................................................................ 21

E86: Host Interrupt Signal Select ........................................................................................................................... 21

E87 - E88: Host-Supplied Analog Power Source Enable...................................................................................... 22

E89: Amplifier-Supplied Switch Pull-Up Enable .................................................................................................. 22

E90: Host-Supplied Switch Pull-Up Enable........................................................................................................... 23

E91 - E92: Bus Base Address Select (High Bits).................................................................................................... 23

E93 - E94: Reset from Bus by Software Enable ..................................................................................................... 24

E98: DAC/ADC Clock Frequency Control ............................................................................................................ 25

E100: Output Flag Supply Select............................................................................................................................. 25

E101 – E102: Output Flag Supply Voltage Configure........................................................................................... 26

E103: Watchdog Disable Jumper ............................................................................................................................ 27

E106: Firmware Reload Enable............................................................................................................................... 27

E110: Expansion Port Configuration ...................................................................................................................... 27

HOST PC-AT I/O ADDRESS MAP................................................................................29

BUS ADDRESS JUMPER SETUP................................................................................31

MATING CONNECTORS ..............................................................................................33

CONNECTOR PINOUTS ..............................................................................................37

J1 (JDISP): Display Port Connector ....................................................................................................................... 37

J2 (JPAN): Control Panel Port Connector ............................................................................................................. 38

J3 (JTHW): Multiplexer Port Connector ............................................................................................................... 40

J4 (JRS232) Serial Port Connector ......................................................................................................................... 42

J4A (JRS422): Serial Port Connector ..................................................................................................................... 43

J5 (JOPTO): I/O Port Connector ............................................................................................................................ 44

J6 (JXIO): Auxiliary I/O Port Connector...............................................................................................................................45

J7 (JS1): A/D Port Connector ..................................................................................................................................................46

J8 (JEQU): Position-Compare Connector...............................................................................................................................47

J11 (JMACH1): Machine Port Connector.............................................................................................................................48

TB1 (JPWR): Power Supply......................................................................................................................................................51

Table of Contents iii

Option 2: Dual Ported RAM

Option 5: CPU & Memory Configurations

Option 6: Extended Servo Algorithm

Option 7: Plate Mounting

Option 8: High-Accuracy Clock Crystal

Option 9: RS-422 Interface (now standard)

Option 10: Firmware Version Specification

Option 14: Replacement of flag Opto-Isolators with Socketed Shunts

Option 15: V-to-F Converter for Analog Input