WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS Pijit Kochcha, Sarawut Sujitjorn

Isolated Zeta Converter: Principle of Operation and Design in

Continuous Conduction Mode
PIJIT KOCHCHA, SARAWUT SUJITJORN*
School of Electrical Engineering, Institute of Engineering
Suranaree University of Technology
111 University Avenue, Muang District, Nakhon Ratchasima, 30000
THAILAND
pijit_sut@hotmail.com
*
corresponding author: sarawut@sut.ac.th

Abstract: - The principle of operation of the zeta converter is explained in the article. Small-signal and
steady-state models of the converter are presented. The design formulas for the continuous conduction mode
(CCM) are given together with some design examples and simulation results. The power factor and harmonic
issues are also addressed.

Key-Words: - zeta converter, continuous conduction mode (CCM), harmonic, power factor.

1 Introduction Section 3 presents an overview of the state-space

Vast majority of power converters used nowadays
employ front-end diode bridge rectifiers. Such
rectifiers draw pulsating currents which leave
behind a great amount of harmonics, and
considerably low power factor. For a single
converter of this type used with a single-phase load
such as in a consumer electronic equipment, the
problems may not seem serious. However, a great
number of those equipments in parallel connection
at a point of common coupling (PCC) to draw
power simultaneously introduce some serious
effects concerning reactive power and harmonic.
The situations are quite common in offices and
industries.
Several types of AC-DC converters have been
introduced to achieve the demanded power
conversion, and the less problems on harmonic and
power factor [1]. To name a few, these include the
Cuk converter [2], the Sepic converter [3]-[6], the
combined boost with double winding flyback
converter [7], and the zeta converter [8]-[13].
Among those, the zeta converter, which is originally
the buck-boost type, can be regarded as a flyback
type when an isolated transformer is incorporated.
An isolated zeta converter has some advantages
including safety at the output side, and flexibility
for output
adjustment [14]-[16].
This article describes the operation principle of
the isolated zeta converter in the CCM in Section 2.
averaging technique, while the transfer function
model can be found in Section 4. Section 5 presents
the steady-state time-domain model in CCM.
Section 6 provides design examples, simulation
results with discussions. The harmonic, and power
factor issues are also discussed. Conclusion follows
in Section 7.
2 Principle of Operation
Fig.1(a) depicts the circuit diagrams of the isolated
zeta converter such that its operation principle in the
CCM could be readily explained.
Fig.1(b) represents the 1st region of operation in
which the switch S is “on”, and the diode D is “off”.
This region takes the time from 0 to d1Ts seconds.
The inductor Lm stores the energy received from the
rectifier. The capacitor C1 supplies energy to the
load (R) via the inductor Lo, and the capacitor Co.
the currents through the inductors Lm and Lo
increase linearly, while no current flows through the
diode.
Fig.1(c) represents the 2nd operation region in
which the switch S is “off”, and the diode D is “on”.
This region begins at the time d1Ts seconds, and
ends by d2Ts seconds. The diode D is forward biased
due to the voltage across the inductor Lm has
reversed polarity, while the currents iLm and iLo
decrease linearly. The stored energy in the inductor
Lm is transferred to the capacitor C1. The load R

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ig C1
1: n Lo
+ + +
is + −vC1 + +vLo −
vLm Lm Co vCo R Vo
vs − − −
vg
S
−

(a) an isolated zeta converter

ig ip iC1 iLo io ig ip iC1 iLo io
1: n 1: n
+ +
is + is +
iLm iD iCo Vo iLm iD iCo R Vo
R
− vs −
vs vg vg

− −

(b) region 1 of operation (c) region 2 of operation

Fig.1 Circuit diagrams of the isolated zeta converter.

S S
ON OFF ON OFF
t t
iLm Vg ∆iLm vC1 vLm vg
−
Lm nLm
t
t vC1
iLo nvg + vC1 − vo ∆iLo v
− o vLo nvg + vC1 − vo
n
Lo Lo
t
t
iC1 vC1 n ( nvg + vC1 − vo ) vo
− ig vg
+
n 2 Lm Lm Lo
nvg + vC1 − vo
−
Lo
t
t
v v
iCo iD − 2C1 − o
n Lm Lo
nvg + vC1 − vo v
− o
Lo Lo
t t

d1Ts d 2Ts d1Ts d 2Ts

Ts Ts

Fig.2 Current and voltage waveforms.

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receives energy from the inductor Lo. Hence, the X = − Aav −1 BavU
current iD=iC1+iLo. Y (4)
Fig.2 illustrates the steady-state current and = −C av Aav −1 Bav .
voltage waveforms in one switching cycle. These U
curves will be referred to for the development of the
Under small-signal assumption, taking the Laplace
design formulas. transform to Eq. (3) results in

3 Overview of The State-Space

xɺ ( s ) = [ sI − Aav ]  Bav vɶg ( s )
−1

Averaging Technique
Considering the operation of the converter during + ( A1 − A2 ) X + ( B1 − B2 )Vg  dɶ1 ( s )  (5).
the on- and off-time intervals denoted as ton or d1Ts ,
yɶ ( s ) = Cav xɶ ( s ) + ( C1 − C2 ) X  dɶ ( s )
and toff or (1 − d1 ) TS , respectively, the state
equations in one switching cycle can be written as Finally, one can obtain the following transfer
functions: for nvɶg = 0

xɺ = As x + Bs u yɶ ( s )
= Cav [ sI − Aav ] ( A1 − A2 ) X + ( B1 − B2 )Vg 
−1
(1)
y = Cs x d1 ( s )
ɶ (6)
+ ( C1 − C2 ) X
, where
, and for dɶ1 = 0
As = [ A1d1 + A2 (1 − d1 )], Bs = [ B1d1 + B2 (1 − d1 )],
Cs = C1d1 + C2 (1 − d1 )  . yɶ ( s )
= Cav [ sI − Aav ] Bav
−1
(7).
ɶvg ( s )
Linearization can be made to the above equations by
considering small-signal perturbations such that
x = X + xɶ , y = Y + yɶ , d1 = D1 + dɶ1 , u = U + uɶ 4 Transfer Function Models
Referring to the circuit in Fig. 1(a), the parameters
where X >> xɶ , Y >> yɶ , U >> uɶ and D >> dɶ be 1 1 transferred from the secondary onto the primary side
substituted into Eq. (1). Under the steady-state are
condition of the state variables, one may write the
following equations
vo′ = vo n , Lo′ = Lo n 2 , C1′ = n 2 C1 , Co′ = n 2Co ,
R′ = R n 2 .
X = Aav X + BavU = 0
(2)
Y = Cav X According to the operation in one switching cycle,
the circuit equations can be written as
, and
diLm ( t ) Vg v
= ( d1 ) − C1′ (1 − d1 )
xɺ = Aav xɶɺ + ( A1 + A2 ) X + ( B1 + B2 )U  dɶ + Bav uɶ dt Lm Lm
(3)
yɶ = Cav xɶ + ( C1 − C2 ) X  dɶ diLo′ ( t ) n 2Vg n 2 vC1′ n 2 vCo′
= ( d1 ) + ( d1 ) −
dt Lo Lo Lo
, where dvC1′ ( t ) iLo′ i
=− 2 ( d1 ) + 2Lm (1 − d1 ) (8)
Aav = A1 D1 + A2 (1 − D1 ) , Bav = B1 D1 + B2 (1 − D1 ) , dt n C1 n C1
Cav = C1 D1 + C2 (1 − D1 ) . dvCo′ ( t ) iLo′ v
= 2
− Co′
dt n Co RCo
vo′ = vCo′ .
From Eq. (2), Eq. (4) below are obvious.

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Let the state, input and output vectors be 

−
(1 − D1 ) 
represented by  0 0 0 
 Lm 
T  iɺɶ   2
n D1 n 2   iɶLm 
x = iLm′ iLo′ vC1′ vo′  , u =  vg  , y =  vo′  ,  Lm   0 0 −  
     iɺɶLo′   Lo Lo   iɶLo′ 
ɺ  =    vɶ 
the coefficient matrices of the state-variable models vɶC1′   (1 − D1 ) −
D1
0 0  
C1′

can be obtained as  vɺɶ′   n 2C1

 o   n 2C1   vɶo′ 

 0 1 1 
0 −
 2
n Co RCo 

−
(1 − D1 ) 
 0 0 0   dɶ 
 Lm   D1   0 0 − 1 0
 2 2   L   Lm  I 
n D1 n
 0 0 −   m   2 ɶ
n d1   Lm 
 Lo Lo   n 2 D1   0 0 0   I Lo′ 
Aav =   (9) +   vɶg  +  Lo  V 
 (1 − D1 ) −
D1
0 0   Lo   ɶ   C1′ 
 0   d1 dɶ1
 n 2C1 n 2 C1  − 0 0   Vo′ 
     n 2C1 n 2C1 
 0 1
0 −
1   0   
 2
n Co RCo   0 0 0 0 

T  Vg 
D n 2 D1   
Bav =  1 0 0 (10)  Lm 
 Lm Lo   n 2V 
+ g
  dɶ1  (13)
Cav = [ 0 0 0 1] (11).  Lo 
 
 0 
By substituting Eqs. (9)-(11) into Eq. (4), the  0 
following steady-state relations can be obtained
 iɶLm 
 n D1 2
 2 ɶ 
i
 2  vɶo′  = [ 0 0 0 1]  Lo′ 
ɺ (14).
 R (1 − D1 )   vɶC1′ 
 I Lm   n 2 D   
I   1   vɶo′ 
 Lo′  =  R (1 − D1 )  V 
VC1′   D1
 g The transfer function models of the isolated zeta
   
 Vo′   (1 − D1 )  converter can be derived from the above Eqs. (13)-
  (14), and obtained as
 D1 
 (1 − D ) 
  vɶo′ ( s )
Gvd ( s ) =
1

(12). dɶ1 ( s )
Vo′ D1 =
1 avd s 2 + bvd s + cvd
= (15)
Vg (1 − D1 ) (1 − D1 ) as 4 + bs 3 + cs 2 + ds + e
2

vɶo′ ( s )
Gvv ( s ) =
The small-signal models as shown in Eqs. (13)-(14) vɶg ( s )
can be obtained from substituting Eqs. (9)-(11) into
1 avv s 2 + bvv
Eq. (5). = (16)
(1 − D1 ) as 4 + bs 3 + cs 2 + ds + e
2

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, where iCo
avd = n 2 RLm C1Vg (1 − D1 ) , bvd = −n 2 D12 LmVg ,
∆Q
cvd = RVg (1 − D1 )
2
∆iCo ∆iCo
2 t
avv = n 2 D1 RLmC1 , bvv = D1 (1 − D1 ) R Ts 2
a = n RLm Lo C1Co , b = n Lm Lo C1
2 2 Ts
c = RLo Co (1 − D1 ) + n 2 D12 RLmCo + n 2 RLm C1
2

Fig. 3 The current iCo waveform.

d = Lo (1 − D1 ) + n 2 D1 Lm , e = R (1 − D1 ) .
2 2

The voltage ripple ∆VC1 can be expressed as

5 Steady-State Models
1 d1Ts 1 d1Ts i dT
Referring to the waveforms in Fig. 2 and the
analysis principle presented in [17], the steady-state
∆VC1 =
C1 ∫0
iC1dt = ∫ io dt = o 1 s
C1 0 C1
(23).

models of the isolated zeta converter in CCM can be

developed as follows. Vo
The turn-on and turn-off times (ton and toff) can be From Eq. (23) and i = , one can obtain
R
expressed as
Vo d1
L ∆i L ∆i C1 = (24).
ton = d1Ts = m Lm = o Lo (17) f s R∆VC1
Vg nVg
Referring to the waveforms of iCo and iLo in Figs.
nL ∆i L ∆i
toff = (1 − d1 ) Ts = m Lm = o Lo (18). (2)-(3), and the fact that ∆VCo = ∆Q Co , one may
VC1 Vo derive

Since the voltage VC1 = nVg d1 (1 − d1 ) = Vo , one Vo (1 − d1 )

Co = (25).
can obtain the voltage gain 8 f s 2 Lo ∆VCo

Vo nd1
M= = (19)
Vg (1 − d1 ) 6 Design Examples
Designing the isolated zeta converter in the CCM
, and the duty cycle requires the knowledge of critical inductances
denoted as Lmc and Loc .
M Based on the assumptions of lossless and the
d1 = (20).
n+M average load current being equal to the average
current in Lo , the terms Loc and Lmc can be found
1 as follows:
Due to the fact that Ts == ton + toff , and from
fs
Eqs. (17)-(19), one may derive the current ripple (1 − d1 ) R
Loc = (26)
terms obtained as 2 fs

VgVC1 Vg d1 (1 − d1 ) 2 R
∆iLm = = (21) Lmc = (27)
f s Lm (VC1 + nVg ) f s Lm 2 n 2 f s d1

nVgVo nVg d1 The design criteria are that Lo ≥ Loc , Lm ≥ Lmc ,

∆iLo = = (22).
f s Lo (Vo + nVg ) f s Lo Vo d1 V (1 − d1 )
C1 ≥ , and Co ≥ o 2 to achieve
f s R∆VC1 8 f s Lo ∆VCo

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%γ ≤ 1% and ∆VC1 = ∆VCo = 2 3γ Vo . The formulas Table 1 Design results (converter with an R load).
dignify the smallest components possible. In
practice, the output qualities must be considered for Parameters Values
a proper component sizing. peak input voltage (Vg) 311 V 50 Hz
Let us consider the requirement that the converter
produces the average output voltage of 105 Vdc, and avg. output voltage (Vo) 105 V
the current of 2.1 Adc from the ac input of 311 Vpk,
avg. output current (Io) 2.1 A
50 Hz. The first step is to calculate the gain
M = Vo Vg = 105 311 = 0.3376 , the duty cycle switching frequency (fs) 50 kHz
d1=0.6280, and the turns ratio n. Then select the Lm , Lo 3 mH, 200 uH
switching frequency fs. The expressions (26) and
C1 , Co 20 uF, 1.41 mF
(27) are used next to obtain the inductances Lo and
Lm as follows: turns ratio
0.2
of hf transformer (n)
(1 − d1 ) R (1 − 0.6280)(50)
Lo ≥ = duty cycle (d1) 0.6280
2 fs 2(50 × 103 )
= 186 µ H M 0.3376

(1 − 0.6280 ) ( 50 )
2
(1 − d1 ) 2 R
Lm ≥ =
2 ( 0.2 ) ( 50 × 103 ) ( 0.6280 )
2 2
2 n f s d1
= 2.75mH .

Thus, the chosen inductances are Lo = 200 µ H ,

and Lm = 3mH .

The capacitances Co and C1 are calculated according

to Eqs. (24) and (25), and obtained as

Vo (1 − d1 ) (105 )(1 − 0.6280 )

Co ≥ =
8 f s Lo ∆VCo 8 ( 50 × 103 ) ( 200 × 10−6 ) (1.82 )
2 2
(a) source voltage and current waveforms
= 5.36 µ F

Vo d1 (105)( 0.6280 )
C1 ≥ =
f s R∆VC1 ( 50 × 103 ) ( 50 )(1.82 )
= 14.49µ F

The design results are summarized by Table 1.

(b) output voltage and current waveforms

Fig. 4 Simulation results (R load, without LC filter).

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The simulation results using PSIM are illustrated 5(b)-(c) show the simulation results indicating that
in Fig. 4. Very large transient voltage can be the output transient peaks are well suppressed, and
observed, and later suppressed by an LC filter. The the outputs become steady in a short time. The
average output voltage and current are 105.48 Vdc , average outputs of 105.35 Vdc , and 2.11 Adc are
and 2.11 Adc, respectively. A high current harmonic obtained. At PCC, the current harmonic distortion is
of 123.53 % THDi, and a low power factor of reduced to 30.81 % THDi, and the power factor is as
0.6270 (lagging) are observed at the PCC. high as 0.9096 (lagging).
Let’s consider another design example where the
1: n C1 Lo load of the converter is a series RL. This can be a
+ good representation of a motor load in steady-state
Lf
Lm Co R Vo operation. The zeta converter has 220V (311 peak
vs Cf − voltage), 50Hz supply. Its load is assumed to be
23.7 mH series with an R, 800W, 11A rated. Firstly,
the equivalent load resistance, and the average
output voltage can be calculated as Po I o 2 = 800/112
= 6.6116 Ω, and Po I o = 800/11 = 72.73 Vdc,
(a) zeta converter with the LC-filter respectively. The voltage gain and the duty cycle are
M = Vo Vg = 72.73 311 = 0.2339 , and d1 = 0.5391,
respectively. The expressions (26) and (27) are used
next to obtain the inductances Lo and Lm as
follows:

(1 − d1 ) R (1 − 0.5391)(6.6116)
Lo ≥ =
2 fs 2(50 × 103 )
= 30.47 µ H

(1 − 0.5391) ( 6.6116 )
2
(1 − d1 ) 2 R
Lm ≥ =
2 ( 0.2 ) ( 50 × 103 ) ( 0.5391)
2 2
2 n f s d1
= 651.31µ H .
(b) source voltage and current waveforms
Thus, the chosen inductances are Lo = 40 µ H ,
and Lm = 700 µ H .

The capacitances Co and C1 are calculated according

to Eqs. (24) and (25), and obtained as

Vo (1 − d1 ) ( 72.73)(1 − 0.5391)
Co ≥ =
8 f s Lo ∆VCo 8 ( 50 × 103 ) ( 40 × 10−6 ) (1.26 )
2 2

= 43.66 µ F

Vo d1 ( 72.73)( 0.5391)
C1 ≥ =
(c) output voltage and current waveforms f s R∆VC1 ( 50 × 103 ) ( 6.6116 )(1.26 )
Fig. 5 Simulation results (R load, with LC filter). = 94.14 µ F

An LC filter designed by a conventional method

(Lf = 100 mH, Cf = 137 nF) is incorporated into the Table 2 summarizes the case.
converter as shown by the diagram in Fig. 5(a). Figs

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Table 2 Design results (converter with an RL load). The voltage and current waveforms obtained
from PSIM are illustrated in Fig. 7. With the
Parameters Values assumed RL load, the average output voltage and
current of the converter are 72.83 Vdc, and 10.93
peak input voltage (Vg) 311 V 50 Hz Adc, respectively, according to the expectation.
Without a filter, the current harmonic is as high as
avg. output voltage (Vo) 72.73 V 143%, and the power factor is 0.5844 (lagging). An
avg. output current (Io) 11 A LC filter having Lf = 50 mH and C f = 137 nF is
added to the input frontend. The duty cycle is also
switching frequency (fs) 50 kHz
increased to 0.5861 to compensate for the associated
Lm , Lo 700 uH, 40 uH voltage drop. The simulation results indicate that the
average output voltage is 72.34 Vdc, the average
C1 , Co 100 uF, 4.4 mF output current is 10.86 Adc, with 28.83 %THDi and
turns ratio power factor of 0.8842 (lagging). It is observed that
0.2 the LC filter significantly decreases the pulsation of
of hf transformer (n) the source current, in turn drastically reduces the
harmonic distortion, and increases the power factor
duty cycle (d1) 0.5391 of the circuit.
M 0.2339

(a) source voltage and current waveforms

(a) source voltage and current waveforms

(b) output voltage and current waveforms

(b) output voltage and current waveforms
Fig. 8 Simulation results (RL load, with LC filter).
Fig. 7 Simulation results (RL load, without LC
filter).

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 WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS
7 Conclusion
This paper has explained the principle of operation
of the zeta converter with the design formulas for
the continuous current mode (CCM) of operation. It
also presents the development of the state-variable,
and the transfer function models of the isolated zeta
converter. Two design examples are given for the
cases of R, and series RL loads. Detailed simulation
results are presented, and the following conclusions
are drawn: (i) the output voltage and current contain
a considerable amount of ripples which have to be
limited in practice, (ii) the converter without an
input filter produces a great deal of current
harmonic, and possesses a low power factor, and
(iii) a simple LC input-filter can be used at first
sight to reduce the harmonic, and to increase the
power factor. The issues concerning the
discontinuous current mode (DCM), the control of
the output power, the power factor correction, and
the harmonic reduction are under investigations.
Acknowledgements
The authors are thankful to the Mechatronics
Program-SUT for financial supports of the project.
The first author’s thank is due to SUT for the
doctoral scholarship.
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LIST OF SYMBOLS
d1 = “on” duty cycle of switch S
d2 = “off” duty cycle of switch S
fs = switching frequency (Hz)
iC1 = current of capacitor C1 (A)
iCo = current of capacitor Co (A)
iD = current of diode D (A)
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 WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS Pijit Kochcha, Sarawut Sujitjorn

ig = output current of rectifier (A)

iLm = current of inductance Lm (A)
iLo = current of inductance Lo (A)
io = output current (A)
ip = primary current of transformer (A)
is = input current (A)
n = turns ratio of high frequency
transformer
vC1 = voltage of capacitor C1 (V)
vg, Vg = output voltage of rectifier (time
domain), peak value (V)
vLm = voltage of inductance Lm (V)
vLo = voltage of inductance Lo (V)
vo, Vo = output voltage (time domain),
average value (V)
vs = sinusoidal source voltage (V)
Gvd(s) = transfer function of duty cycle to
output voltage
Gvv(s) = transfer function of input to output
voltages
M = voltage gain of peak input to output
voltages
THDi = total harmonic current distortion
Ts = switching period (s)
iLm = current ripple of inductor Lm (A)
iLo = current ripple of inductor Lo (A)
VC1 = voltage ripple of capacitor C1 (V)
VCo = voltage ripple of capacitor Co (V)
γ = output ripple factor
 = small-signal perturbation
 = transferred circuit parameters from
secondary to primary

ISSN: 1109-2734 492 Issue 7, Volume 9, July 2010