Small Signal Model of Boost DC-DC Converter Operating in CCM

The averaged model is obtained by averaging the N sets of differential equations that represent the N operating states of a given converter. Considering the boost converter operating in the CCM, for the first stage the transistor S is conducting, the state equations for the first stage may be written as is presented in (1).
diL Vin = dt L dVC V = C dt RC

(1)

For the second stage, the transistor is turned OFF and the diode is forward biased by the inductor L. The state equations representing this stage are presented in (2).
diL Vin VC = dt L dVC iL VC = dt C RC

(2)

Averaging the equations from both states, it is obtained (3).

diL Vin (1 D ) VC = dt L dVC (1 D ) iL VC = dt C RC

(3)

Replacing the control parameters, input and state variables with a dc steady-state value and a small time-varying component:

%L ) d ( IL + i dt

% %in 1 D + d Vin + v

( (
))
C

) ) (V

%C ) +v (3)

%C ) d (VC + v = dt

( (

% 1 D + d

( I L + i%L )

%C ) (VC + v RC

Rewriting the equations in terms of-small signals, neglecting small-signal and DC products, and treating DC steady-state values as constant parameters equation (3) may be rewritten as:
% +v %L dV % (1 D ) v %C di = C in dt L % %L dI %C (1 D ) i % dv v L = C dt C RC

(4)

Using equation (4) it is build the linearized block diagram presented in figure 1.
Vin

%I d L

%V d C

1 i%L sL

(1 D )

1 sC

%C v

1 R

(1 D )
Figure 1. Block diagram of the linearized model. To obtain the transfer functions of VC and IL in relation to the duty cycle, the block diagram may be simplified as it is presented in the table 1 and the result is presented below.

(1 D )VC LI L s vC = d LCs 2 + L s + 1 D 2 ( ) R V Cs + 2 (1 D ) I L IL = C d LCs 2 + L s + 1 D 2 ( ) R (1 D )VC LI L s vC = I L VC Cs + 2 (1 D ) I L

Table 1. Block Diagram simplification to obtain the transfer functions. VC IL

IL
IL

% d

VC

1 sL

%L i

(1 D )

% d

(1 D )

C s+ 1 RC

VC

(1 D )

1 C 1 s+ RC

%C v

sL

(1 D )
(1 D ) sL
1

IL

IL

% d

VC sL

%L i

(1 D )
VC C 1 s+ RC

% d

(1 D )

(1 D )VC
sL

1 C s+ 1 RC

%C v

(1 D )
VC

% d

VC sL

%L i
2
+

(1 D )

VC C 1 s+ RC
IL (1 D )

% d

(1 D ) 1 IL sL

(1 D )VC 1 sL s+ RC 1 (1 D )VC (1 D ) 1+ C 1 sL VC s+ RC

1 C

%C v

% d

VC Cs + 2 (1 D ) I L L 2 LCs 2 + s + (1 D ) R

%L i

% d

(1 D )VC LI L s
LCs 2 + L 2 s + (1 D ) R

%C v