Professional Documents
Culture Documents
January-May 2006
Outline
Uniform Interconnects
Waveguide
a
b
w
Coaxial
Twisted-pair
h
h
εr
w1
w
w2
Coplanar Microstrip
Dr. J.E. Rayas Sánchez (Hewlett-Packard's RF Design and Measurement Seminar, 2000) 3
PCB
(add-in card)
Components
(Chip + Pkg)
PCB Connector
(Motherboard)
(A. Weisshaar, Tutorial on High-Speed Interconnects, IMS June 2004, Fort Worth, TX)
(A. Weisshaar, Tutorial on High-Speed Interconnects, IMS June 2004, Fort Worth, TX)
Dr. J.E. Rayas Sánchez 7
(A. Weisshaar, Tutorial on High-Speed Interconnects, IMS June 2004, Fort Worth, TX)
Dr. J.E. Rayas Sánchez 8
(A. Weisshaar, Tutorial on High-Speed Interconnects, IMS June 2004, Fort Worth, TX)
Dr. J.E. Rayas Sánchez 9
(A. Weisshaar, Tutorial on High-Speed Interconnects, IMS June 2004, Fort Worth, TX)
Dr. J.E. Rayas Sánchez 10
Skin Effect
(A. Weisshaar, Tutorial on High-Speed Interconnects, IMS June 2004, Fort Worth, TX)
Dr. J.E. Rayas Sánchez 11
(A. Weisshaar, Tutorial on High-Speed Interconnects, IMS June 2004, Fort Worth, TX)
Dr. J.E. Rayas Sánchez 12
Proximity Effect
(A. Weisshaar, Tutorial on High-Speed Interconnects, IMS June 2004, Fort Worth, TX)
Dr. J.E. Rayas Sánchez 13
FR4
W 1 GHz
H
W = 5 mm L = 25 mm
H = 5 mm εr = 4.5
dielectric loss tan = 0.025
(A. Weisshaar, Tutorial on High-Speed Interconnects, IMS June 2004, Fort Worth, TX)
Dr. J.E. Rayas Sánchez 15
(A. Weisshaar, Tutorial on High-Speed Interconnects, IMS June 2004, Fort Worth, TX)
Dr. J.E. Rayas Sánchez 16
On-chip Interconnects
– lumped C if very short
– lumped RC if very short and R significant
– cascaded lumped RC if short
– distributed RC if long
– RLC distributed line (high performance VLSI circuits
and microwave ICs)
(A. Weisshaar, Tutorial on High-Speed Interconnects, IMS June 2004, Fort Worth, TX)
Dr. J.E. Rayas Sánchez 19
Dr. J.E. Rayas Sánchez (R. Ludwig and P. Bretchko, RF Circuit Design, Prentice Hall, 2000) 22
Zo , γ
Zo , γ
z
l
Dr. J.E. Rayas Sánchez 0 27
Reflection Coefficient
l
0
Reflection coefficient at the load
Vo− Z L − Z o
Γ = Γl (l = 0) = =
Vo+ Z L + Z o
Input Impedance
Zo , γ ZL
l
0
V (l ) Z + Z o tanh(γl )
Z in (l ) = = Zo L
I (l ) Z o + Z L tanh(γl )