Power +5V Group

GND A I/O
Supplies
Group Port PA7-PA0
A A
Control (8)

Group
Bidirectional Data Bus A I/O
Port C PC7-PC4
Data Upper
D7-D0 Bus (4)
Buffer
8-Bit
Internal Group
Data B
Bus Port C I/O
Lower PC3-PC0
(4)

RD
Read Group Group
WR Write B I/O
B
A1 Control Control PB7-PB0
Port
A0 Logic B
RESET (8)

CS

VLSI training ttm inc.,

 +5V
- 15 V +5V
26 7
VCC GND 12 10

NC 1 18 NC
27
D7 D7 37
PA7 2 D7 13
38 Analog Impute
Data Bus PA6 3
39
PA5 4
34 40 16
D0 D0 PA4 5 AD570 Digital Common (+ 5 V Common
1 15
PA3 6 Shorted to Common
2
PA2 7 For Unipolar ( 0 to 10 V)
3
PA1 8 D0
4 14
PA0 9
DR B/C

6 17 11 Analog
A15 CS PC7 Common
A1 8 (- 15 V Common)
A1
A0 9 PC0
A0 14 START Plus
5
MEMR RD At least
36
MEMW WR Port B Not Used 2µs
RESET
35

RESET
OUT (8085)

VLSI training ttm inc.,

 CLK 0
Date
Counter
D7-DO 8 Bus GATE 0
Buffer = 0
OUT 0

RD CLK 1
Read/
WR Counter
Write = 1 GATE 1
AO Logic
A1 OUT 1

CS

CLK 2
Control
Counter GATE 2
Word
= 2
Register
OUT 2

Internal Bus

VLSI training ttm inc.,

 INTA RST 6.5 TRAP
SID SOD
INTR RST 5.5 RST 7.5

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus

Accumulator Temp. Reg.. Instruction

(8) (8) Register (8) Multiplexer
W (8) Z (8)
Temp. Reg.. Temp. Reg..
B (8) C (8)
Flag (5) Reg.. Reg..
Flip-Flops D (8) E (8)

Reg.. Select
Instruction Reg.. Reg.. Register
Decoder H (8) L (8) Array
Arithmetic Reg.. Reg..
and
Logic Stack Pointer (16)
Unit Machine
(ALU) Cycle (16)
(8) Program Counter
Encoding
Incrementer/Decrementer
Power Supply +5V Address Latch (16)
GND

Training and Control

X1 CLK
Reset
X2 GEN Control Status DMA Address Buffer (8) Data/Address Buffer (8)

CLK OUT HLDA RESET OUT

RD WR ALE S0 S1 10/M A15-A8 AD7-AD0
READEY HOLD RESET IN Address Bus Address/Data Bus

VLSI training ttm inc.,