Designing

Arithmetic Logic Unit (ALU) and

a combinational barrel shifter

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 Design Specification of ALU

Design an ALU which performs a set of arithmetic and logic

operations on two 8-bit input busses namely A[7:0] and B[7:0]
depending on 5 select lines SEL[4:0] and a carry input, Cin.
Arithmetic operations include addition, subtraction, increment,
decrement. Logical operations include AND, OR,
Complementing and ex-Oring. There are few shifting operations
like left shift by 1-bit and right shift by 1-bit.

The output of the ALU also is an 8-bit bus, namely Y[7:0] and
any carry output, if generated, can be ignored. The functions ALU
needs to perform can be represented in the following table format.

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 SEL[4:0] Cin Operation
00_0_00 0 Y1=A
00_0_00 1 Y1=A+1
00_0_01 0 Y1=A+B
00_0_01 1 Y1=A+B+1
00_0_10 0 Y1=A+B* ( B* is complement of B)
00_0_10 1 Y1=A+B* +1
00_0_11 0 Y1=A-1
00_0_11 1 Y1=A

00_1_00 0 Y1=A AND B

00_1_01 0 Y1=A OR B
00_1_10 0 Y1=A EX-OR B
00_1_11 0 Y1=A*

00_0_00 0 Y=Y1
01_0_00 0 Y=Y1<<1
10_0_00 0 Y=Y1>>1
11_0_00 0 Y=0

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Analysis :
If we closely observe, the operations to be performed by ALU can
be categorized into three namely, Arithmetic, Logical and Shifting.
So whole ALU can be thought of consisting of three sub units in it.

Let us name them as Arithmetic Unit, Logic Unit and Shifter

unit. If we observe the functionality table, SEL[2] line decides
whether ALU is supposed to output arithmetic result OR logical
result. And SEL[4:3] decides whether the arithmetic result or
logical result has to be shifted or not. So, considering all these
issues, the block diagram of ALU and inter-connections between
them can be represented as follows.

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 Block Diagram of ALU

A[7:0]

.
LU[7:0]
B[7:0] Logic Unit

1 Y[7:0]
SEL[1:0] Y1[7:0] Shifter
A[7:0] 0
B[7:0] AU[7:0]

.
Arithmetic
Unit
Cin
SEL[2]

SEL[1:0] SEL[4:3]

SEL[4:0]

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 Logic Unit
• The operations to be performed by this sub unit are AND, OR,
EX-OR and Complement of A.

• The type of operation to be performed is decided by SEL[1:0]

SEL[1:0] Operation

00 A AND B
01 A OR B
10 A EX-OR B
11 A*
• Out of these four operations, the one to be output is decided by
SEL[1:0]. So we need a 4 to 1 multiplexer.

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 .
B[7:0]
. A[7:0]

. . 0
1

. . 2
LU[7:0]

.
3
A[0]
A[1]
.. .. ..
.. .. ..
A[7] Complement block SEL[1:0]

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 Arithmetic Unit
• The operations to be performed by this sub unit are additions
and subtractions
• The type of operation to be performed is decided by SEL[1:0]
and Cin
SEL[1:0],Cin Operation

00_0 A
00_1 A+1
01_0 A+B
01_1 A+B+1
10_0 A+B*
10_1 A+B*+1
11_0 A-1
11_1 A
• Out of these eight operations, the one to be output is decided by
SEL[1:0] and Cin. So we need a 8 to 1 multiplexer.
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 .
.
adder

..
1 A[7:0]
0

..
adder 1
2

.
adder

.
1 3 AU[7:0]
adder
4

.
Compl
5

.
adder
6
1
7
A[7:0]
subtracter
1
{SEL[1:0],Cin}
B[7:0] A[7:0]

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 Shifter Unit
• The operations to be performed by this sub unit are left shift,
right shift, making output zero and no shifting.

• The type of operation to be performed is decided by SEL[4:3]

SEL[4:3] Operation

00 Y=Y1
01 Y=Y1<<1
10 Y=Y1>>1
11 Y=0
• Out of these four operations, the one to be output is decided by
SEL[4:3]. So we need a 4 to 1 multiplexer.

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 Y1 0
{Y1[6:0],0} 1
Y[7:0]

{0,Y1[7:1]} 2

0 3

SEL[4:3]

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 Design Specification of barrel shifter

Design a 6-bit combinational barrel shifter which simply rotates

the bits of A[5:0] depending on a field rotate[2:0] . The function
table of this barrel shifter is shown below.
rotate[2:0] function
000 Y=A
001 Y=A rot 1.
010 Y=A rot 2
011 Y=A rot 3
100 Y=A rot 4
101 Y=A rot 5
110,111 Y=A

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Analysis :
This is a very simple shifter and which requires 8 to 1 multiplexer
because out of 8, only one has to be driven onto output.

Here rotate means, left shifting with MSBs occupying LSB

positions. For example, 101010 is rotated by 1-bit, then the result
would be 010101.

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 A[5:0] 0
{A[4:0],A[5]} 1
{A[3:0],A[5:4]} 2
{A[2:0],A[5:3]} 3 Y[5:0]
{A[1:0],A[5:2]]}
4
{A[0],A[5:1]}
5
A[5:0] 6
A[5:0] 7

rotate[2:0]

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