2020 6th International Conference on Advanced Computing & Communication Systems (ICACCS)

Implementation of optimized digital filter using

sklansky adder and kogge stone adder
Ajay Prasath A M Arjun R V
UG Student, Department of ECE UG Student, Department of ECE
Sri Krishna College of Technology Sri Krishna College of Technology
Coimbatore,India Coimbatore,India
16tuec007@skct.edu.in 16tuec014@skct.edu.in

Deepaknath K Gayathree K
UG Student, Department of ECE Asst Professor, Department of ECE
Sri Krishna College of Technology Sri Krishna College of Technology
Coimbatore,India Coimbatore,India
16tuec031@skct.edu.in gayathree.k@skct.edu.in

Abstract— In Digital era, filters can be used as memory input signal by analyzing the different types of multiple
elements to store data. The most commonly used adders to and accumulate performance.
implement digital filters, are the full adders. Here in this project
the implementation of digital filter is done with PPA. Among
Normal serial adder has been replaced by the parallel
various PPA, the sklansky adder is more efficient than others.
prefix adder. In PPA there are four adders here we use
When implementing kogge stone adder, it experiences a larger
hardware complexity. So that it is necessary to reduce the
sklansky and kogge stone adder in FIR filter.
hardware complexity the architecture of sklansky adder has been
introduced using Xilinx ISE. The comparative analysis made II. EXISTING WORK
among various parameters such as numbers of logic gates and
delay. The above proposed architecture tends to reduce the A. Kogge stone adder
hardware complexity using various parameters.

Keywords— FIR filter, Kogge-stone adder (KSA), sklansky Kogge-stone adder is a parallel prefix adder obtained from
adder, Parallel prefix adder(PPA), power and area. carry look in advance structure with awareness on design time
and is the common place preference for high performance
adders in industry[4]. The KSA consume more area then the
I. INTRODUCTION BK.
Generally there are some basic processes to design a digital
filter. The design filter needs to be redesign the frequencies, Parallel prefix adders are classified in to three stages:
calculate the parameters and have to adjust the filter at each i) Pre-processing.
time. In some rare cases, the redesign requires filters to be ii) Generation of carry.
exchanged with their filter types or with its length to fit iii) Final processing.
according to their requirements. [1].
• Pre processing :
A complicated DSP system consists of multiple adders and
multipliers[2]. The effective design of DSP machine enchance
In pre-processing stage, the generate and propagate signals are
the performance of the system. An adder, which is a
given as:
fundamental component is frequently employed in many
networks that are used in system like controllers and Pi= Ai ْBi (1)
processing chips[3]. In this system a performance is improved Gi=Ai . Bi (2)
by the running ability of adder and multiplier.
• Generation of carry :
In Digital filters can use FIR or IIR filter systems for
implement and there adaptive algorithm to update their In this stage the carries are calculated with the equivalent bits.
parameters but in practice, FIR structured digital filters can be
effortlessly done with high performance so that it has being Gi=(Pi.Giprev)+Gi (3)
more widely used. We also use FIR digital filter for our
studies[5]. Normally FIR filter will compute the sum of

978-1-7281-5197-7/20/$31.00 ©2020 IEEE 661

Authorized licensed use limited to: University of Canberra. Downloaded on June 08,2020 at 06:08:43 UTC from IEEE Xplore. Restrictions apply.
 2020 6th International Conference on Advanced Computing & Communication Systems (ICACCS)
Pi=(Pi.Piprev) (4) B. Sklansky adder
• Final processing :
Sum and Carry outputs bits are calculated by Sklansky adder has a simple prefix design by divide and
Si=Pi Ci-1 (5) conquer concept and it gives a delay of log2n stages by
calculating intermediate prefix bits along with large prefixes.
A=1001 B=1100 SUM=10101
The sklansky adder was constructed using of latches,
AND, OR, XOR gates.
The output two bits Sumi=ai Å bi Å ci.

Fig. 1. Working of KSA.

Fig 4. RTL view of Sklansky adder.

Fig. 5. Waveform of Sklansky adder.

III. IMPLEMENTATION OF ADDER IN DIGITAL FILTER

The FIR filter are commonly designed using basic building

blocks of multiplier, adders and the series number of delays (D
flip flops). As shown in the Fig 1 the common FIR filter of
length L. The delays considered in the filter operate on the
input data. The coefficient values added to the filter is used for
multiplication [6].

Fig. 2. RTL view.

Fig. 6. Architecture of FIR

Fig. 3. Waveform of kogge stone adder.

978-1-7281-5197-7/20/$31.00 ©2020 IEEE 662

Authorized licensed use limited to: University of Canberra. Downloaded on June 08,2020 at 06:08:43 UTC from IEEE Xplore. Restrictions apply.
 2020 6th International Conference on Advanced Computing & Communication Systems (ICACCS)
kogge stone to check which makes the filter efficient. The
filter is designed with the series of D flip flop with each
connected with each one of the multiplier to multiply the
given input then it connected with the sklansky adder. By
using sklansky adder in the filter we came to know that the
power and the LUTs are less than the kogge-stone adder
shown in the Table I.
Fig 6 shows the common FIR filter structure of length L,
where Xn represents the filter coefficients which is to be
multiplied with input sample and D represents the delay
samples and H0, H1, H2….. represents the filter coefficients
which is to be multiplied with input sample. Where if an L tap
of FIR filter is designed it consists of (L-1) delay and L filters
coefficients and (L-1) adders.

A. Kogge-stone adder in FIR filter

Fig. 9. RTL view of FIR filter using sklansky adder.

The FIR filter is designed as shown above architecture

with the slight change of adder incited of sklansky adder we
use kogge stone adder to compare with the sklansky which
makes the filter efficient. The filter is designed with the series
of D flip flop with each connected with each one of the
multiplier to multiply the given input then it connected with
the KSA. By using KSA in the filter we came to know that the
power and the LUTs are larger shown in the Table II.

Fig. 10. Waveform of FIR filter using sklansky adder.

IV. RESULT & DISCUSSION

The design of FIR filter using kogge-stone adder and

Fig. 7. RTL view of FIR filter using Kogge-stone adder. sklansky adder has done in HDL using Xilinx ISE 12.2. The
given tabulation shows the parameters of area are utilized and
power consumption are obtained through simulation.

A. LUT
Table I

Fig. 8. Waveform of FIR filter using Kogge-stone adder.

B. Sklansky adder in FIR filter

The FIR filter is designed as shown in the fig 3

architecture. We use sklansky adder to compare with the FIR FILTER using sklansky adder

978-1-7281-5197-7/20/$31.00 ©2020 IEEE 663

Authorized licensed use limited to: University of Canberra. Downloaded on June 08,2020 at 06:08:43 UTC from IEEE Xplore. Restrictions apply.
 2020 6th International Conference on Advanced Computing & Communication Systems (ICACCS)

The number of 4 input LUTs used in the FIR are 749 which is Table V
less than kogge-stone adder.
SI.NO Types of FIR LUTs used Power(μw)
Table II filter
1 FIR filter using 873 0.139
kogge stone adder
2 FIR filter using 749 0.108
sklansky adder

The performance of two FIR filters is compared by

changing the parallel prefix adders in the filters at the final
stage. The comparative results are tabulated in Table V.

FIR FILTER using kogge-stone adder.
The number of 4 input LUTs used in the FIR are 873 which
is more in the kogge-stone adder than the sklansky adder.
B. Power
Table III
Power of the FIR FILTER using sklansky adder
Table IV
V. CONCLUSION
The FIR filter was designed and UHVXOW VKRZHG in Xilinx
ISE 12.2. The DSSHULDQFH of the FIR filter using KSA
is compared with the FIR filter using sklansky adder.
After comparison we came to know that FIR filter using
sklansky adder architecture is faster compared to FIR filter
using KSA.
References
[1] Haichen Zhao, Shaolu Hu, Linhua Li, Xiaobo Wan. “NLMS Adaptive
FIR Filter Design Method”.
[2] B. Ramkumar and Harish M Kittur, “Low-Power and Area
Efficient Carry Select Adder”, IEEE Transsactions on Very Large Scale
Integration (VLSI) Systems, VOL. 20, No. 2 Feb 2012.
[3] Deepak Kumar Patel, Raksha Chouksey, Dr. Minal Saxena “Design of
Fast FIR Filter Using Compressor and Carry Select Adder”, 2016 3rd
International Conference on Signal Processing and Integrated Networks
(SPIN).
[4] A.Abinaya , M.Maheswari. “Implementation of Kogge Stone Adder for
Signal Processing Applications”, International Journal of Advanced
Research in Computer and Communication Engineering Vol. 8, Issue 5,
May 2019.
[5] S. Madhavi, K. Rasagna, N. Kavya, M. Sindhu. “Implementation of
programmable fir filter using dadda multiplier and parallel prefix
adder”,IEEE Xplore Compliant Part Number:CFP18N67-ART;
ISBN:978-1-5386-2456-2.
[6] V. Jamuna, P. Gomathi and A. Arun, “Design and Implementation of
FIR Filter Architecture using High Level Transformation Techniques”
Indian Journal of Science and Technology.
[7] M.Moghaddam, M. B. Ghaznavi-Ghoushchi. “A New Low-Power, Low-
area, Parallel Prefix Sklansky Adder with Reduced Inter-Stage
Connections Complexity”.
[8] Aung Myo San, Alexey N. Yakunin “Reducing the Hardware
Complexity of a parallel prefix adder”.

Power of the FIR FILTER using kogge stone adder

978-1-7281-5197-7/20/$31.00 ©2020 IEEE 664

Authorized licensed use limited to: University of Canberra. Downloaded on June 08,2020 at 06:08:43 UTC from IEEE Xplore. Restrictions apply.