Final Assessment Test – November 2019

Course: ECE3013 - Linear Integrated Circuits

Class NBR(s): 2415 / 2417 Slot: D1+TD1
Time: Three Hours Max. Marks: 100
KEEPING MOBILE PHONE/SMART WATCH, EVEN IN ‘OFF’ POSITION, IS EXAM MALPRACTICE
Answer ALL Questions

1. a) Find the maximum possible output offset voltage of Figure 1, which is caused by the input offset [5]
voltage Vio=10mv?

Figure 1
b) Determine the output voltage for the circuit shown in Figure 2. [5]

Figure 2

2. a) Data given for the differential amplifier as, inputs = −30 mV, and = +30 mV, has a output [5]
VO = 1V. With inputs = = 5.5 V, the output is = 0.5 V. Determine the CMRR, expressed in
dB.

b) Find of the given circuit in Figure 3. [5]

Figure 3

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3. a) Sketch the output waveform for the circuit shown in Fig. 4, if the input is a 5 sine wave. [5]

Figure 4
3. b) Compute ⁄ and for the circuit given in Figure 5, if = 10V, = 5V and = 2V. [5]

Figure 5
4. For the voltage series feedback amplifier, the values of and are 1 KΩ and 10 KΩ. The various [10]
specifications for the op-amp used are : open loop gain is 2 × 10 , input resistance is 1 MΩ, output
resistance is 75 Ω,single break frequency is 3 kHZ, supply voltages = ± 13V. Calculate the closed loop
voltage gain, input resistance and output resistance.

5. Design a circuit to meet the following specifications: integration constant of -2000, lower limit of [10]
integration ( ) not greater than 100 , input impedance( ) at least 6 KΩ and DC gain not more
than 25 dB .

6. a) Calculate the values of resistors and capacitors shown in Figure 6 to sustain its oscillation [10]
= 25 . The minimum resistance to be used is 10 Ω. Derive the expression of output
frequency ( ).

Figure 6

[OR]

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6. b) Determine the expression for frequency of oscillation and the condition for sustained oscillation for [10]
the circuit shown in Figure 7. Assume the ideal used in the circuit.

Figure 7
7. Determine the output frequency and amplitude of Figure 8. Obtain the output waveform if the [10]
position of op-amp A1 and A2 will interchange. Assume = ±13 .

Figure 8
8. a) Identify the filter circuit shown in Figure 9 and derive its gain magnitude function. Plot the [10]
frequency response plot of this filter.

Figure 9

[OR]
8. b) Design a wide band pass filter with fL= 200Hz, fH= 1kHz and a pass band gain = 6. Draw the frequency [10]
response plot of this filter and calculate the value of Q for the filter.
9. Design NE-565 with a neat diagram and define the functioning of it with different circuit stages. [10]
10. A 8-bit DAC has a step size of 20 mV. Determine the full-scale output voltage reading and the [10]
percentage resolution. Suggest a way out to increase the percentage resolution of the DAC.

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