Digital Electronics Number Systems Guide

DIGITAL ELECTRONICS
1STSem BCA
Digital Electronics GFGC Tumkur
Chapter-1
Number system
Number a quantity or value expressed by a word or a symbol is called Number

Number system a set of symbols & rules for representation of numbers is called
Number System
They are classified into two types they are
a. Positional number system
b. Non positional number system
a. Positional number system
The value of the digit depends on the position in which they appear in the number
Eg: decimal,binary,octal & hexa decimal number system
b. Non positional number system
In this type each symbol represents a definite value irrespective of the position in which
they appear
Eg: Roman number system.
Base or radix
The total number of different digits or symbols available in the number system is called
“base or radix”
Positional number system
The positional number system are classified into four types they are
1. Decimal number system

2. Binary number system
3. Octal number system
4. Hexa decimal number system
Decimal number system
It is also called as Hindu Arabic numerals

The symbols used in this system are 0,1,2,3,4,5,6,7,8,9
The radix or base of this number system is 10
Weight structure of this number system is
…..104 10 3 10 2 10 1 10 0 . 10 -1 10 -2 10 -3 ……
Binary number system
The symbols used in this system are 0,1 0 & 1 are called “bits”
Bit is an abbreviation for a binary digi t

…..24 2 3 2 2 2 1 2 0 . 2 -1 2 -2 2-3 ……….
The weights increases from right to left by a power of two for each bit
The left most bit is the MSB & right most bit is the LSB
1 1 1 1 0 1 1 1 1
MSB LSB
Terms used in binary number syst em
The symbols used in this system are 0,1 0 & 1 are called “bits”
Bit is an abbreviation for a binary digi t
Nibble: A group of 4 bits called a Nibble
Byte: A group of 8 bits called a Byte.
Word: A group of 16 bits called a word or 2 Bytes is equal to 1 word
LSB(Least significant bit): which has the lowest place value in the number
MSB(Most significant bit): which has the highest place value in the number
Octal number system
The symbols used in this system are 0,1,2,3,4,5,6,7

……..83 8 2 8 1 8 0 . 8 -1 8 -2 8 -3 …………
Hexa decimal number system
The symbols used in this system are 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

…..163 16 2 16 1 16 0 . 16 -1 16 -2 16 -3 ……..
Conversions
Decimal to binary conversion

Binary to decimal conversion
2. Octal number system
Decimal to octal conversion

Octal to decimal conversion

Octal to binary conversion
Binary to octal conversion
3. Hexa decimal number system
Decimal to Hexa decimal conversion

Hexa decimal to decimal conversion
Hexa decimal to binary conversion
Binary to Hexa decimal conversion
4.Other conversions
Octal to Hexa decimal

Hexa decimal to Octal
Decimal to binary conversion
In this conversion the given decimal number is repeatedly divide by 2 for integer part until
the quotient is 0 and for fraction successively multiplying by 2
Eg: Convert 28.3125 (10) ---- (?)2
Binary to decimal conversion
1. Determine the positional value of each digit

2. Multiply the obtained value by the digit in the corresponding position
3. Sum the products calculate in the previous step to get the decimal number
2 62 52 4 2 32 22 1 2 02 -12 -2 2 -3 2 -4
64 32 16 8 4 2 1 0.5 0.25 0.125 0.0625
Eg:1110.011(2) -- (?)10
=1x23 +1x22 +1x21 +1x20 +0x2-1 +1x2-2 +1x2-3

=1x8+1x4+1x2+0x1+0x0.5+1x0.25+1x0.125
=8+4+2+0+0+0.25+0.125
1110.011(2) =14.375(10)
Octal number system
Decimal to octal conversion
Eg: Convert 549.1325 (10) ----- (?)(8)
Octal to decimal conversion

8 48 38 28 18 08 -1 8 -2 8 -3
4096 512 64 8 1 0.125 0.0156 0.00195
Eg: Convert 763.375 (8) ---------- (?)(10)
7x82 +6x81 +3x80 +3x8-1 +7x8-2 +5x8-3
7x64+6x8+3x1+3x0125+7x0.0156+5x0.00195
448+48+3+0.375+0.1092+0.00975
763.375(8) = 499.49395(10)
Octal to binary conversion
1. Convert each digit of the octal number to a 3 digit binar y number

2. Combine all the resulting binary groups into a single binary number
Octal Binary
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
Eg: 4632.51(8) -------- (?)2

4 6 3 2 . 5 1
100 110 011 010 101 001
4632.51(8) =100110011010101001 (2)
Binary to octal conversion
1. The bits of the binary numbers are grouped into groups of 3 bits starting from LSB for
integer and from MSB for fraction
2. If the last group contains less than 3 bits then place 0 for those place
3. Convert each group into a octal equivalent digit
Eg:01111.1101011 (2) ->(?)8
1.
2.
3. 1 7 . 6 5 4
4.17.654(8)
5. 01111.1101011(2) = 17.654 (8)
Hexa decimal number system
Decimal to Hexa decimal conversion
Eg:Convert 512.625 (10) ----- (?)16

Hexa decimal to decimal conversion

164 163 162 161 160 16-1 16-2 16-3

65536 4096 256 16 1 0.0625 0.0039 0.00024
Eg: 36F.ABC(16) ------ (?)10

3x162 +6x161 +Fx160 +Ax16-1 +Bx16-2 +Cx16-3
3x256+6x16+15x1+10x0.0625+11x0.0039+12x0.00024
879.67078(10)
36F.ABC(16) = 879.67078(10)
Hexa decimal to binary conversion
1. convert each digit of the Hexa decimal number to a 4 digit binary number
2. combine all the resulting binary groups into a single binar y number
Decimal Hex binary

0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
10 A 1010
11 B 1011
12 C 1100
13 D 1101
14 E 1110
15 F 1111
Eg: 10A4.FACE(16) ------ (?)2

1 0 A 4 . F A C E
0001 0000 1010 0100 1111 1010 1100 1110
0001000010100100.1111101011001110 (2)
10A4.FACE(16) = 0001000010100100.1111101011001110 (2)
Binary to Hexa decimal conversion
1. The bits of the binary numbers are grouped into groups of 4bits starting from LSB for
3. Convert each group into a Hexa decimal equivalent digit
Eg: 11100.01(2) =(?)16
1 C . 4
11100.01(2) = 1 C .4(16)
4.Other conversions
Octal to Hexa decimal
1. convert each digit of the Octal number to a 3 digit binary number

4. Convert each group into a Hexa decimal equivalent digit
Hexa decimal to Octal
1. convert each digit of the Hexa decimal number to a 4 digit binary number
4. Convert each group into a octal equivalent digit
Complements of binary numbers
They are
1 s complement
2 s complement
1’s complement
The 1 s complement of a binary number is obtained by changing each 0 to 1 and 1 to

0
Eg:101011
010100->1 s complement
2’s complement
The 2 s complement of a binary number is formed by taking the 1 s complement of

the number and then adding 1 to LSB position
Eg: 101011
1
Signed binary numbers
Numbers that contain a sign bit followed by magnitude bits are called “sign
magnitude number”
In this MSB always represents the sign whether +ve or –ve
The remaining bits represent magnitude which is the value of the number
The negative numbers are represented as sign magnitude,1 s complement & 2 s

complement
Bit->0,1
Nibble->4 bits
Byte->8 bits
Word-.2bytes->16 bits
Floating point numbers
Floating point numbers consists of mantissa, exponent and a sign

The Floating point numbers are represented as „any number y which is represented as
„a x rp
Where a->mantissa
r-.radix
p->exponent
Floating point numbers can be expressed in three formats
1. Single precision (32 bits)
2. Double precision (64 bits)
3. Extended precision (80 bits)
S Exponent Mantissa
Normalization
“The number succeeding the floating point is a non-zero number is called

normalization”
Eg: 0.0047x10 9 is represented as 0.49x10 7
0.00236x10-7 is the normalized form is 0.236x10 -9
Binary arithmetic
Binary arithmetic consists of the operations such as addition, subtraction, multiplication,

division
Binary addition
The rulesof binary addition are
0+0=0
0+1=1
1+0=1
1+1=0 with a carry 1
1+1+1 with a carry 1
Addition of unsigned number
Addition of bits according to the rules of binary addition
Addition of signed numbers
There are 4 cases
1. Both positive number

2. Larger positive and smaller negative number
3. Smaller positive and larger negative number
4. Both negative numbers
Both positive numbers
1. Convert decimal to binary

2. Then add according to the rules
Eg: 128 64 32 16 8 4 2 1
64 0 1 0 0 0 0 0 0
+32 0 0 1 0 0 0 0 0
+96 0 1 1 0 0 0 0 0
Larger positive and smaller negative number

2. Then take 2 s complement for smaller negative number
3. Add according to the rules
4. Discard carry bit and represent sign bit
Eg: Add -16 from 32
step-1 128 64 32 16 8 4 2 1
+32 0 0 1 0 0 0 0 0
-16 0 0 0 1 0 0 0 0
+16
step-2 0 0 0 1 0 0 0 0
1's
1 1 1 0 1 1 1 1 complement
1
2's
1 1 1 1 0 0 0 0 complement
step-3 0 0 1 0 0 0 0 0
1 1 1 1 0 0 0 0
1 0 0 0 1 0 0 0 0
step-4 Ingnored carry bit
Smaller positive and larger negative number

2. Then take 2 s complement for larger negative number
4. Represent sign bit Then take 2 s complement for obtain the result
Eg: Add -32 from 20
step-1 128 64 32 16 8 4 2 1
20 0 0 0 1 0 1 0 0
-32 0 0 1 0 0 0 0 0
-12
step-2 0 0 1 0 0 0 0 0 =>32
1 1 0 1 1 1 1 1 1's complement
1
1 1 1 0 0 0 0 0 2's complement
step-3 0 0 0 1 0 1 0 0 =>20
1 1 1 0 0 0 0 0 =>2’s com of 32
1 1 1 1 0 1 0 0
sign
step 4 1 1 1 1 0 1 0 0
0 0 0 0 1 0 1 1 1's complement
1
0 0 0 0 1 1 0 0 2's complement
Both negative numbers

2. Then take 2 s complement for both negative number
4. Discard carry bit and represent sign bit
5. Then take 2 s complement for obtain the result
Eg: Add -16 from -32
step-1 128 64 32 16 8 4 2 1
-32 0 0 1 0 0 0 0 0
-16 0 0 0 1 0 0 0 0
-48 Take 2's complement for 32
step-2 0 0 1 0 0 0 0 0
1 1 0 1 1 1 1 1 1's complement
1
1 1 1 0 0 0 0 0 2's complement
Take 2's complement for 16

0 0 0 1 0 0 0 0
1 1 1 0 1 1 1 1 1's complement
1
1 1 1 1 0 0 0 0 2's complement
step-3 add
1 1 1 0 0 0 0 0
1 1 1 1 0 0 0 0
1 1 1 0 1 0 0 0 0
sign
Discard carry bit MSB is 1 i.e sign
step-4 bit=1
step-5 1 1 0 1 0 0 0 0
0 0 1 0 1 1 1 1 1's complement
1
0 0 1 1 0 0 0 0 2's complement
Binary subtraction
The rulesof binary subtraction are
0-0=0
0-1=1 with borrow 1
1-0=1
1-1=0
Subtraction can be performed using 3 methods
a. Ordinary binary subtraction

b. Subtraction using 1 s complement
c. Subtraction using 2 s complement
Ordinary binary subtraction

This is the simple method of subtraction of bits according to the rules of binary subtraction
Eg:
1 0 0 1
-0 1 0 1
0 1 0 0
1 1 0 . 1 0 1 1 1 0
-0 1 0 . 0 0 0 1 0 1
1 0 0 . 1 0 1 0 0 1
1 0 1 1 . 0 0 1
-0 1 1 1 . 1 0 1
0 0 1 1 . 1 0 0
Subtraction using 1’s complement
Unsigned numbers
There are twocases
1. The number of digits of minuend are less than the comprehend

2. The comprehend is smaller than minuend or the number of digits of comprehend are
lesser than minuend
1. The number of digits of minuend are less than the comprehend
Inserting zero s to left of the minuend

Take 1 s complement for minuend
Add both comprehend and minuend
Carry that is generated is added to LSB to obtain result
Eg: Subtract 1100 from 1101001
1 1 0 1 0 0 1 comprehend
1 1 0 0 minuend
step-1 Inserting zero s to left of the minuend

0 0 0 1 1 0 0
step-2 Take 1 s complement for minuend

0 0 0 1 1 0 0
1 1 1 0 0 1 1 1's complement
step-3 Add both comprehend and minuend

1 1 0 1 0 0 1
1 1 1 0 0 1 1
1 1 0 1 1 1 0 0
step-4 Carry that is generated is added to LSB to obtain result

1 0 1 1 1 0 0
1
1 0 1 1 1 0 1
2. The comprehend is smaller than minuend or the number of digits of comprehend are
lesser than minuend
Inserting zero s to left of the comprehend

There is no end around Carr y so the result is to be again take 1 s complement
1 1 0 1 0 1 comprehend
1 1 0 1 0 0 1 0 1 minuend
step-1 Inserting zero s to left of the comprehend

0 0 0 1 1 0 1 0 1 comprehend

1 1 0 1 0 0 1 0 1 minuend
0 0 1 0 1 1 0 1 0 1's complement min

0 0 0 1 1 0 1 0 1 comprehend
0 0 1 0 1 1 0 1 0 1's complement min
0 1 0 0 0 1 1 1 1
There is no end around Carry so the result is to be again take 1 s

step-4 complement
0 1 0 0 0 1 1 1 1
1 0 1 1 1 0 0 0 0 Final result
Signed numbers
Case 1: subtracting smaller number from a larger number
Convert decimal number to binary number

End around carry bit is added to LSB of the r esult
step-1 Convert decimal number to binary number

25 0 0 0 1 1 0 0 1 comprehend
16 0 0 0 1 0 0 0 0 minuend

0 0 0 1 0 0 0 0 minuend
1 1 1 0 1 1 1 1 1's complement min

0 0 0 1 1 0 0 1 comprehend
1 0 0 0 0 1 0 0 0
step-4 End around carry bit is added to LSB of the result

0 0 0 0 1 0 0 0
1
0 0 0 0 1 0 0 1 Final result
Case 2: subtracting larger number from a smaller number

To verif y the magnitude the result is converted to its 1 s complement again

16 0 0 0 1 0 0 0 0 comprehend
25 0 0 0 1 1 0 0 1 minuend

0 0 0 1 1 0 0 1 minuend

0 0 0 1 0 0 0 0 comprehend
1 1 1 1 0 1 1 0
sign
step-4 To verify the magnitude the result is converted to its 1 s complement again
1 1 1 1 0 1 1 0
0 0 0 0 1 0 0 1 1's complement & final result
Subtraction using 2’s complement
Unsigned numbers

Inserting zero s to left of the minuend
Carry is ignored

114 1 1 1 0 0 1 0 comprehend
28 1 1 1 0 0 minuend
step-2 Inserting zero s to left of the minuend

28 0 0 1 1 1 0 0 minuend

0 0 1 1 1 0 0 minuend
1 1 0 0 0 1 1 1's complement
1
1 1 0 0 1 0 0 2's complement min

1 1 0 1 0 1 1 0
step-5 Carry is ignored

1 0 1 0 1 1 0 Final result
Case 2: subtracting larger number from a smaller number

Inserting zero s to left of the comprehend


28 1 1 1 0 0 comprehend
114 1 1 1 0 0 1 0 minuend
step-2 Inserting zero s to left of the comprehend

28 0 0 1 1 1 0 0 comprehend

1 1 1 0 0 1 0 minuend
0 0 0 1 1 0 1 1's complement
1

0 1 0 1 0 1 0
step-5 There is no end around Carry so the result is to be again take 2 s complement
0 1 0 1 0 1 0
1 0 1 0 1 0 1 1's complement
1
1 0 1 0 1 1 0 2's complement & final result
Signed numbers

Carry is ignored and repr esent sign bit

128 64 32 16 8 4 2 1
64 0 1 0 0 0 0 0 0 comprehend
-32 0 0 1 0 0 0 0 0 minuend
32

0 0 1 0 0 0 0 0 minuend
1 1 0 1 1 1 1 1 1's complement
1

0 1 0 0 0 0 0 0 comprehend
1 0 0 1 0 0 0 0 0
step-4 Carry is ignored and represent sign bit

0 0 1 0 0 0 0 0 Final result
sign
Case2: subtracting larger number from a smaller number


128 64 32 16 8 4 2 1
32 0 0 1 0 0 0 0 0 comprehend
-64 0 1 0 0 0 0 0 0 minuend
-32

0 1 0 0 0 0 0 0 minuend
1 0 1 1 1 1 1 1 1's complement
1

0 0 1 0 0 0 0 0 comprehend
1 1 1 0 0 0 0 0
sign
step-4 There is no end around Carry so the result is to be again take 2 s complement
1 1 1 0 0 0 0 0
0 0 0 1 1 1 1 1 1's complement
1
0 0 1 0 0 0 0 0 2's complement & final result
Binary multiplication
In most computers multiplication is achieved using addition
In this method the multiplicand is multiplied by each multiplier digit beginning with the least
significant digit. The result of the multiplication of the multiplicand by a multiplier digit is
called a “partial product”
Partial product method of multiplication
1. Determine the sign of the product depending on whether the signs of multiplicand and
multiplier are the same or different
2. Negative number which may be in 2 s complement form should be converted to the true
form( uncomplement form)
3. The partial products are generated starting with the least significant bit (LSB) of the
multiplier
If multiplier bit is 0.partial product is 0.if multiplier bit is 1.partial product is shifted one bit
to the left
4. The final product is obtained by adding each successive partial product to the sum of the
previous partial products
5. If the product is negative, the 2 s complement of the product is determined. If the sign bit
is positive, the true form is retained. The sign bit is attached to the product
Eg: Multiply the signed numbers 01010011(multiplicand) & 10111011(multiplier)
1. Sign bit of multiplicand is 0 & sign bit of multiplier is 1.so the sign bit of product will be 1
2. Take 2 s complement for multiplier
3. Only magnitude bits are used for multiplication

4.
5. Sign of the product is 1.magnitued of product is 1011001011111.

So the final result is 1 1011001011111
Binary division
Method of binary division
1. The sign of the quotient is determined depending on whether the signs of the dividend and
divisor are the same or different, the quotient is initialized to zero
2. The divisor is subtracted from the dividend using 2 s complement addition so as to get the
first partial remainder. a 1 is added to the quotient is incremented by 1.if this partial
remainder is positive, we move on to the next step. If this partial remainder is zero or
negative, the division is complete
3. Subtract the divisor from the partial remainder and add 1 to the quotient. If the result is
positive, repeat for the next partial remainder. If the result is zero or negative, the division is
complete
Example:Divide 01100100 by 00011001
Solution: 01100100 ->dividend
00011001->divisor
1. Sign bit of both are positive. so quotient is positive. it is initialized to 00000000
2. The divisor is subtracted from the dividend so take 2 complement for divisor
00011001->divisor
Add dividend & divisor
Discard carry bit . The sign bit is 0 so move to the next step
Add 1 to quotient
3.The divisor is subtracted from the 1 st partial remainder using 2 s complement addition
The sign bit is 0 so move to the next step
Add 1 to quotient
4.Add 2nd partial remainder with 2 s complement of divisor
The sign bit is 0 so move to the next step
5. Add 3rd partial remainder with 2 s complement of divisor
The remainder is zero .so division is complete

Final product is 00000100
Digital codes
Code is a symbolic representation of discrete elements of information which may be

in the form of numbers, letters or any other varying physical quantities
The symbol used is a string of binary digits 0 & 1 & these are arranged according to
the rules of code. The group of bits(0 & 1) is known as a “binary code or digital code”
There are two types of digital codes
1. Numeric codes
2. Alphanumeric code(character codes)
Numeric codes are broadly divided into 4 classes they are
1. Weighted codes
2. Self-complementing codes
3. Cyclic or reflected codes
4. Error detecting & correcting codes
Alphanumeric code (character codes)
Alphanumeric code are used to represent numbers, letters, symbols and instructions
Eg: ASCII code
Weighted codes
It obeys the positional weighting principles. In weighted code, the bits are multiplied by the
weights indicated and the sum of the weighted bits gives the decimal digit
Eg: The codes 8421(BCD), 2421 code
Binary coded decimal (BCD) [8421 code]
BCD uses the binary number system to specify the decimal number 0 to 9.it is
composed of four bits
The weights are assigned according to the position occupied by these digits
BCD code
Decimal 8421
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
Eg: Write BCD code for a decimal number 96.42
=>9 6 . 4 2
=>1001 0110 0100 0010
=>[ 1001011001000010]BCD
Disadvantages of BCD
1. Only 10 possible combinations are used to represent decimal numbers. remaining six
combinations of 4 bits are wasted
2. It is difficult to obtain complements used in subtraction
The 8421 code
A weighted code is the 8421 code. Here the weight 2 is repeated twice
Decimal 8421 code

0 0000
1 0001
2 0010
3 0011
4 0100
5 1011
6 1100
7 1101
8 1110
9 1111
Self complementing codes
The self complementing code may or may not be weighted

If a code is constructed such that when we replace a 1 by a 0 or 0 by a 1 in the 4 bit
code. a code for the 9 s complement of the digit is obtained then such a code is called
self complementing code
Example of self complementing weighted code is the 2421 code
code for Digit

2421 complement complement
Decimal code 2421 decimal
0 0000 1111 9
1 0001 1110 8
2 0010 1101 7
3 0011 1100 6
4 0100 1011 5
5 1011 0100 4
6 1100 0011 3
7 1101 0010 2
8 1110 0001 1
9 1111 0000 0
Excess-3 code
It is an important unweighted self complementing code

It is formed by adding 0011(3) to the BD in the normal weighted form so it is called
excess-3 or xs-3 code
Example for self complementing non weighted code is the Excess-3 code
Digit
code for complement
Decimal Excess-3 complement decimal
0 0011 1100 9
1 0100 1011 8
2 0101 1010 7
3 0110 1001 6
4 0111 1000 5
5 1000 0111 4
6 1001 0110 3
7 1010 0101 2
8 1011 0100 1
9 1100 0011 0
Gray code
The gray code is a non weighted code. It differs from the preceding number by a single bit.
So it is called the “ unit distance code ”. It is also called reflected code or cyclic code
Binary to gray code conversion
1. The MSB in the gray code is same as the corresponding MSB in the binary number
2. Going from left to right each adjacent pair of binary code bits are added to get the
next gray bit. The carries generated are ignored
Eg:
Gray to binary conversion
1. The MSB in the binary is the same as the corresponding MSB in the gr ay code
2. Going from left to right each binar y code generated is added to the gray code bit in
the next adjacent position .the carries generated are ignored
Eg:
Gray
Decimal Binary code
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000
Error detection & correction codes
Parity bit
Parity bit is a additional bits is used for a bit error detection

Parity bit are of two types
1. Even parity
2. Odd parity
Even parity
If the total number of 1 s is even in the code or number then it is called as even parity
Odd parity
If the total number of 1 s is Odd in the code or number then it is called as Odd parity
Even parity Odd parity

BCD P BCD P
0000 0 0000 1
0001 1 0001 0
0010 1 0010 0
0011 0 0011 1
0100 1 0100 0
0101 0 0101 1
0110 0 0110 1
0111 1 0111 0
1000 1 1000 0
1001 0 1001 1
Only single bit errors can be detected using this method if doesn t check for 2 bit
errors in a group
Error correction code
Hamming code
The hamming code is used not only to detect a bit error but also to identif y the bit that
is in error so that it can be corrected
The hamming code uses a number of parity bits depending on the number of
information bits, located at certain position in the code group
The steps are
1. Number of parity bits
2. Placement of parity bits in code
3. Assignment of parity bit values
4. Detecting & correcting an error
Number of parity bits
The number of parity bits to be included with the information bits is to be determined
by the relationship
2P >=M+P+1
P->number of parity bits

M->number of information bits
The information bits are known but parity bit are found by trial & error method until
the relationship is satisfy
Placement of parity bits in code
The parity bits are placed in the position that are ascending power of 2 (1,2,4,8…)
1 2 3 4 5 6 7
Bits P1 P2 M1 P3 M2 M3 M4
P1,P2,P3=>parity bits
M1,M2,M3 & M4=>message bits or information bits
Assignment of parity bit values
Each parity bit should be assigned value of 1 or 0
Bit designation P1 P2 M1 P3 M2 M3 M4
Bit position 1 2 3 4 5 6 7
Binary position 001 010 011 100 101 110 111
Information bits (M n )
Parity bits(Pn )
Each bit position is numbered is binary

Information or message and parity bit locations are indicated in two rows
Parity bit 1 checks all bit positions including itself that have 1 s in the same
location(right most) in the binary position number i.e,p1 checks positions 1,3,5 &7
Parity bit 2 checks has a 1 in the middle position & so it checks positions 2,3,6 &7
Parity bit 3 checks has a 1 in the left most in the binary position and so it checks
positions 4,5,6 &7
Detecting & correcting an error
The number of parity checks made depend on the number o parity bits in the error
correcting code
The method is as follows
a. Checks the p1 group for proper parity
A „0 represent good parity check
A „1 represent bad parity check
b. Repeat this for each parity group
c. The binary number formed by the result of all parity checks designates the
position of the code bit that is an error. This is the error position code
If checks are good that means there is no error. The first parity check generate the
LSB and the last parity check generate the MSB
Problem
1. Find single error correcting code for 1001 using even parity
Solution:
a. Number of parity bits required
By relation 2p >=m+p+1
M=4
P=1 21>=4+1+1
2>=6----- F
P=2 22>=4+2+1
4>=7------- F
P=3 23>=4+3+1
8>=8-------T
So the number of parity bits is 3
The information bits are 4
Total number of bits is code 4+3=7bits
b. Placement of parity bits in code is
20 ,21 ,22 ,………….
1,2,4,………
c. Assignment of parity bit values
Binary position 001 010 011 100 101 110 111
Information bits (M n ) 1 0 0 1
Parity bits(P n ) 0 0 1
Parity bits are to be determined
P1 checks position 1,3,5,7 =>-101

Total number of 1 s is 2 for even parity P1 should be 0
Total number of 1 s is 2 so good parity is 0
Total number of 1 s is 1 so bad parity is 1
The single error correcting code for information 1001 using even parity is 0011001
Problem 2
Suppose information transmitted is the code word 0011001 if it is received as 0010001, find
the error that has occurred in transmission if even parity is used
Solution: construct bit position table
Binary position 001 010 011 100 101 110 111
Transmitted code 0 0 1 1 0 0 1
Received code 0 0 1 0 0 0 1
Here we are using detecting and correcting an error

There are 3 parity checks because number of parity bits is 3
First parity check
P1 checks position 1,3,5,7=0101(even number of 1 s) ->good parity=>0(LSB)
Second parity check
P2 checks position 2,3,6,7=0101(even number of 1 s) ->good parity=>0
Third parity checks
P3 checks position 4,5,6,7=0001(odd number of 1 s)->bad parity=>1(MSB)
so the error position code is 100.this shows that the bit in position 4 is in error
it is 0 in the received code but it should be a 1 so then the corrected code will be
0011001which will match the transmitted code
character code
ASCII[American standard code for information interchange)
It is a 7 bit code proposed by ANSI(American national standard institute)

The ASCII code is a 7 bit code with the format X6 X5 X4 X3 X2 X1 X0
Where each X is a 0 or 1
ASCII character set

From the table the ASCII code of the upper case letter „A has a code 100 0001 whose
equivalent in decimal number is 65
The range of ASCII set is from 0 to 127
Answer the following question
1. Give the radix of octal and hexa decimal number system (2M,DEC-2010)
2. Define radix of a number system with an example (2MNOV/DEC-2009)
3. Give 1 s complement of 38 10 (2M,DEC-2010)
4. Convert (4M,DEC-2010)
a. 35 8 into hexa decimal
b. 2A16 into decimal
c. 3A16 into octal (4M,NOV/DEC-2009)
d. 258 into decimal
e. 10110112 into octal (4M,OCT/NOV- 2011)
f. 458 to binary
g. 12310 to binary (4M,OCT/NOV-2012)
h. 523.218 to decimal
i. 35.128 to binar y
j. 10112 to hexadecimal
5. Find the sum of decimal numbers 40 and 75 in binary addition method. (4M,DEC-2010)
6. Subtract 4510 from 25 10 in 2 s complement method (3M,DEC-2010)
7. Subtract 2510 from 4010 in 2 s complement method (3M,NOV/DEC-2009)
8. Subtract 2610 from 36 10 in 2 s complement method (3M,OCT/NOV- 2011)
9. Subtract 7710 from 99 10 in 2 s complement method (3M,OCT/NOV-2012)
10. Give 2 s complement of 1100(2) (2M,OCT/NOV-2012)
11. The sum of decimal number 30 10 and 45 10 in binary addition method. ( 3M,OCT/NOV-
2011)
12. Explain binary multiplication procedure with an example?
13. Explain the procedure of binary division with suitable example.

14. What are BCD codes? Explain 8421 code. Mention its application (4M,NOV/DEC-2009)
15. Explain self complementing property of excess-3 code (4M,NOV/DEC-2009)
16. Define excess-3 code of a number system (3M,OCT/NOV- 2011) (OCT/NOV-2012)
17. Convert 1101 2 to gray code (2M,OCT/NOV- 2011)
18. Define gray code of a number system (2M,OCT/NOV-2012)
19. Explain steps involved in using hamming code for single –error correction
20. Suppose information transmitted is the code word 0101011.if it is received as 0100011,
find the error that has occurred in transmission, if even parity is used
Chapter-2
Boolean algebra
Introduction
In 1854 George Boole introduced a systematic treatment of logic and developed for
this purpose an algebraic system known as symbolic logic, or Boolean algebra.
Boolean algebra is a branch of mathematics and it can be used to describe the
manipulation and processing of binar y information or used in the design ,maintenance
and analysis of logical circuits in digital computers
Boolean algebra
Boolean algebra uses Boolean variables and Boolean operators .
Boolean variables are binary variables or symbol used to represent a logical quantity.
Some examples of Boolean variables are A, B, C, a, b, c, X, Y, and Z.
Boolean operators are logical operators There are three basic logical operators: AND,
OR, and NOT.
A Boolean expression is a combination of Boolean variables and Boolean operators.
There are many Boolean expressions that are logically equivalent to one another.
There are called equivalent expressions .
A Boolean function typically has one or more input variables and produces a result
that is based on these input values. The result can have a value of 0 or 1.
Truth Tables
A truth table is a useful visual tool for defining the input-output relationship of binary
variables in a Boolean function.
A function of n variables hasn rows 2 of possible input combinations, each row
specifying the value of the function for a different combination.
A truth table can be used to represent one or more functions.
Complement
It is the inverse of a variable and is indicated by a bar over the variable ex: A=>A
Literal:
It is a variable or the complement of a variable
The Duality Principle
Given a Boolean expression, the dual is formed by replacing AND with OR, OR with
AND, 0 with 1, 1 with 0.
The duality principle states that if two Boolean expressions are equal, then their duals
are also equal.
Ex: ab+ab =a Dual is (a+b).(a+b )=a
Basic Postulates, Laws, and Theorems
Laws of Boolean Addition

x+0=x (Identity law in OR form)
x+1=1 (Null law in OR form)
Laws of Boolean Multiplication
x 0=0 (Null law in AND form)
x 1=x (Identity law in AND form)
Idempotent Laws
x+x=x x x=x
Involution Law
(x ) = x
Laws of Complementarities
x+x =1 (Inverse law in OR form)
x x =0 (Inver se law in AND form)
Commutative Laws
x+y=y+x x y=y x
Associative Laws
(x + y) + z = x + (y + z) = x + y + z
(x y) z = x (y z) = x y z = xyz
Distributive Law
x (y+z) = x y +x z or x(y+z) = xy + xz
x+(y.z)=(x+y)(x+z)
Absorption Laws
x (x+y) = x x + xy = x
De Morgan’s Laws
(x+y)’ = x’ y’
The complement of a sum of variables is equal to the product of the complements of
the individual variables
LHS RHS
X Y X' Y' X+Y (X+Y)' ( X'.Y')
0 0 1 1 0 1 1
0 1 1 0 1 0 0
1 0 0 1 1 0 0
1 1 0 0 1 0 0
(x y)’ = x’ + y’
The complement of a product of variables is equal to the sum of the complements of

the individual variables
LHS RHS
X Y X' Y' X.Y (X.Y)' ( X'+Y')
0 0 1 1 0 1 1
0 1 1 0 0 1 1
1 0 0 1 0 1 1
1 1 0 0 1 0 0
1.Find the complement of W’X+YZ’

Sol:=(W X+YZ )
=(W X) .(YZ )
=(W +X ).(Y +Z )
=(W+X ).(Y +Z)
2. Apply Demorgan’s theorem to the expression (A+B) (B+C) (A+C)

Sol:=((A+B)(B+C)(A+C))
=(A+B) +(B+C) +(A+C)
=A .B +B .C +A .C
=A B +B C +A C
Factoring
In the reverse direction, the distributive law also expresses the process of factoring in which
the common variable X is factored out of the product terms
1.X+XZ=X
=X(1+Z)
=X(1)
=X
2.(X+Y)(X+Z)=X+YZ
=XX+XZ+XY+YZ
=X+ XZ+XY+YZ
=X(1+Z+Y)+YZ
=X(1)+YZ
=X+YZ
Representations of Boolean Functions

A Boolean function can be described or represented by any one of the following:
A Boolean expression (one of many equivalent Boolean expressions)
A truth table
A circuit diagram (one of many equivalent circuit diagrams)
Logical functions:
Boolean expressions are represented in two forms based on their structure
1. Sum of products form (SOP) or disjunctive normal form
2. Product of sums form (POS) or conjunctive normal form
Product term
A term consisting of the product of literals or a single liter al is said to be a product term
Eg: XY, X, X Y , XY
Sum term
A sum term consisting of the sum of literals or a single literal is said to be a sum term
Eg: X+Y, X +Y, X +Y , X
Domain of Boolean expression

It is the set of variables contained in the expression is either complemented or
uncomplemented form
Eg: AB +A BC is the set of variables ABC
SOP function:
SOP is two or more AND functions ORed together.
Or
It is a product term or several product terms logically added
EX: 1.ABC +D EF +FGH+AF G
2. AB+BCD
POS function :
It is two or more OR functions ANDed together. It is also known as the dual of the
SOP
Or
It is a sum term or several sum terms logically multiplied
EX: 1.(A+B+C )(D +E+F)
2.(A+B)(C+D+E )
Standard SOP:
It is also SOP but each product should contain all variables that are in the Boolean
expression. Each product term or AND function is known as min terms
It can be represented as m
m->min term
Eg: ABC +A BC+AB C
In the above example it has got 3 product ter ms containing all the 3 variables
(i.e.,A,B,C)
Conversion from SOP to standard SOP form

1. Multiply each of the product term by „1 which doesn t consist of all the variables so that
the value doesn t change (A.1=A)
2. Replace „1 by sum of complement and uncomplement of the variable which is missing in
that product term (A+A =1)
3. Repeat the above procedure until each product term consists of all the variables
Eg: write the following in the standard SOP form f(A,B,C)=AB’C+AB+A’

Step1:AB C+AB.1+A .1.1
Step2:AB C+AB(C+C )+A (B+B )(C+C )
Step3: AB C+ABC+ABC +A (BC+BC +B C+B C )
Step4: AB C+ABC+ABC +A BC+A BC +A B C+A B C
Standard SOP forms have 7 minterms or product terms
Assigning the value to each minterm

1. Complement of a variable is taken as „0 and uncomplement variable as 1
2. Convert obtained binary form to its decimal equivalent
Boolean expression and truth tables

1. SOP expressions to truth table
The following steps are-
Step-1: determine the domain of expression & hence number of variables „n
Step-2: find the number of input combinations as 2 n
Step-3: list all possible combination of binary values of the variables in the expression
Step-4: convert the SOP expression to standard form
Step-5:place a 1 in the output column for each binary value that makes the standard SOP
expression a „1 & place a „0 for all remaining binary values
Example:
Develop a truth table for the standard SOP expression A’BC’+AB’C
Solution:
1. Number of variables in domain n=3
2. Number of possible input combination 2 n =23 =8
3. Truth table
Inputs Output product

A B C X term
0 0 0 0
0 0 1 0
0 1 0 1 A'BC'
0 1 1 0
1 0 0 0
1 0 1 1 AB'C
1 1 0 0
1 1 1 0
4. The SOP expression is found to be in the standard form

5. Binary values that make the product terms in the expression equal to „1 are A BC =010 &
AB C=101
For these binary values a „1 is placed in the output column. for each of the remaining binary
combinations a „0 is place in the output column
Standard POS:
It is also POS but each sum function consists of all the variables that are in the Boolean
expression each such OR function/term is known as Max term
It can be represented as M
M->max term
Eg:(A+B+C )(A +B+C)
Conversion from POS to standard POS form

1. ADD each of the sum term by „0 which doesn t consist of all the variables so that the
value doesn t change (A+0 =A)
2. Replace „0 by product of complement and uncomplement of the variable which is missing
in that sum term (A.A =0)
3. Expand the function by using the theor em A+BC=(A+B)(A+C)
4. Repeat the above procedure until each sum term consists of all the variables
Eg: write the following in the standard POS form f(X,Y,Z))=(X’+Y’)(Y+Z)

Step1: (X +Y +0)(0+Y+Z)
Step2: (X +Y +ZZ )(XX +Y+Z)
Step3: (X +Y +Z) (X +Y +Z ) (X+Y+Z) (X +Y+Z)
Standard POS term have 4 max terms or sum terms
Assigning the value to each max term
1. Complement of a variable is taken as „1 and uncomplement variable as 0
2. Convert obtained binary form to its decimal equivalent
POS expression to truth table

They are-
Step-1: determine the domain of expression & hence number of variables „n
Step-2: find the number of input combinations as 2 n
Step-3: list all possible combination of binary values of the variables in the expression
Step-4: convert the POS expression to standard form
Step-5: place a 0 in the output column for each binary value that makes the standard POS
expression a „0 & place a „1 for all remaining binary values
Example:
Develop a truth table for the standard POS expression (A+B’+C)(A+B+C’)(A’+B’+C’)
Solution:
1. Number of variables in domain n=3
2. Number of possible input combination 2 n =23 =8
3. Truth table
Inputs Output
A B C X Sum term
0 0 0 1
0 0 1 0 A+B+C'
0 1 0 0 A+B'+C
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0 A'+B'+C'
4. The POS expression is found to be in the standard form

5. Binary values that make the sum terms in the expression equal to „0 are
(A+B +C)=010,(A+B+C )=001,(A +B +C )=111
For these binar y values a „0 is placed in the output column. For each of the remaining
binary combinations a „1 is place in the output column
Standard SOP & POS expression from truth table

The steps finding standard SOP expression from truth table-
a. List the binary values of the input variable for which the output is „1
b. convert each binary value to the corresponding product term
Eg:1001 can be written as AB C D
c. the SOP expression is formed by adding each individual product term for which output is a
„1
Example
Inputs Output
A B C X
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
step1; output is 1 for the binary values 011,100,110,111

step2: the corresponding product terms are A BC, AB C , ABC ,ABC
step3: output X=A BC+AB C +ABC +ABC
The steps for finding standard POS expression from truth table
a. List the binary values of the input variable for which the output is „0
b. convert each binary value to the corresponding sum term
eg: 1010 can be written as A +B+C +D
c .the POS expression is formed by multiplying each individual sum term for which output is
a „0
Example
Inputs Output
A B C X
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
step1; output is 1 for the binary values 000,001,010,101

step2: the corresponding sum terms are A+B+C, A+B+C , A+B +C, A +B+C
step3: output X= (A+B+C), (A+B+C ) ,(A+B +C),(A +B+C )
Karnaugh map
Karnaugh map provides a systematic method for simplifying Boolean expression. The
simplified expression (SOP or POS) is called the minimum expression
K-map can be used to simplify Boolean expressions with two, three or four variables
The number of cells in a k-map is equal to the total number of possible input variable
combinations
For a 2 variable k-map the number of cells=2 n =22 =4 .The variables are A&B
Each cell value is called a minterm

For a 3 variable k-map the number of cells=2 n =23 =8.The variables are A, B&C
For a 4 variable k-map the number of cells=2 n =24 =16.The variables are A, B, C&D
Cell adjacency
Cell adjacency is defined by a single variable change .cells that are differ by only one
variable are said to be adjacent so the order used in 00,01,11,10 to maintain “cell adjacency”
Wrap around adjacency

The cells in the left most columns are adjacent to the corresponding cells in the right most
columns this is called “wrap around adjacency”
Karnaugh map minimization of Boolean expressions

Minimization can be defined as the process that is used to obtain an expression containing
the fewest possible terms with the fewest possible variables
Minimization of SOP expressions

The following 3 steps
1. Mapping a standard SOP expression
2. Grouping the 1 s
3. Summing the resultant product terms
1. Mapping a standard SOP expression

For each product term in the expression a 1 is placed in the cells corresponding to the
value of the product term
After mapping, the number of 1 s in the k-map will be equal to the number of product
terms in the standard SOP expression
The remaining cells are filled with 0 s
2. Grouping the 1’s

The grouping should be done so as to maximize the size of the groups and to
minimize the number of groups
The 1 s are grouped to produce minimum product term
The groups must have either 1, 2, 4, 8&16 cells each being some power of 2
Sub-cubes
o A sub-cubes or a group is a set of exactly 2 m adjacent cells containing 1 s
Single cell
o For m=0the sub-cubes consists of a single cell. Novariables are reduced it is
an isolated 1
Pair
o For m=1a sub-cube consists of 2 m =21 =2 adjacent cells
o Since m=1 grouping two adjacent cells containing 1 s result in elimination of
onevariables
Quad
o Since m=2 grouping four adjacent cells containing 1 s result in elimination of
twovariables
Octet
o Since m=3 grouping eight adjacent cells containing 1 s result in elimination of

threevariables
Overlapping groups
The same 1 in a k-map cell may be used in more than one group so as to help in forming
largest group possible
Rolling the map

The k map is visualized as if it is rolled so that the left side touches the right side and the top
edge touches the bottom edge
Redundant group
A group whose 1 s are all overlapped by other groups is called a redundant group
3. Summing the resultant product terms

The product terms corresponding to each of the gr oups are written
The variable that changes from the complemented to uncomplemented form or vice
versa is eliminated
Example: the SOP expression by using 4 variables is A’BCD+A’BCD’+ABCD+ABCD’
On grouping into a quad, the SOP expression will be BC

Because A changes from 0 to 1 and D changes from 1 to 0,So both variables A & D are
eliminated
Therefore A BCD+A BCD +ABCD+ABCD can be simplified as BC
The final Boolean expression can be obtained by summing the resultant product terms
corresponding to each group this will be the minimum SOP expression
Example problem
1. Minimize the following standard SOP expression using k-map
AB’C+A’BC+A’B’C+A’B’C’+AB’C’ or f(A,B,C)= m(0,1,3,4,5) or
f(A,B,C)=(m0,m1,m4,m5)
Solution:
Step1: Mapping a standard SOP expression
Step 2: Grouping the 1’s
Step 3: Summing the resultant product terms
A B C +A B C+AB C +AB C=>B

A B C+A BC=>A C
The term corresponding to these groups are B +A C
Don’t care condition

The don t care condition do not have any effect on the output
For these don t care terms ,the output may be assigned either a 0 or a 1
An „X or „d is placed in the cell for each don t care term
These terms need not be covered by the sub-cubes, but can be treated as 1 s to make
grouping so as to simplify the resulting term
Example: Using k-map simplify the expression
A’BCD+A’BCD’+A’BC’D+A’BC’D’+A’B’CD
Solution:
Without using don t care term we can have 2 pairs. The resultant expression will be
A BD+A BC =>here one variable is eliminated
Using the don t care term we can have one group i.e. quad .The resultant expression will be
AB
=>Here 2 variables are eliminated so it is advantageous to use don t care terms in simplifying
expression using k-map
Minimization of POS expressions

The following 3 steps
1. Mapping a standard POS expression
2. Grouping the 0 s
3. Multiplying the resultant sum terms
1. Mapping a standard POS expression

Each 0 is placed in a cell of k-map corresponding to the value of a sum term
The number of 0 s in the k=map is equal to the number of sum terms in t he standard
POS expression
The remaining cells are filled with 1 s
2. Grouping the 0’s

The 0 s are grouped to produce minimum sum terms. The rules for grouping are the
same as for the grouping of 1 s discussed earlier
3. Multiply the resultant sum terms

The sum terms corresponding to each of the groups are written
The variable that changes from the complemented to uncomplemented form or vice
versa is eliminated
The final Boolean expression can be obtained by multiplying the resultant sum terms
corresponding to each group this will be the minimum POS expression
Example problem
1. Use k-map to minimize the standard POS expression
(X+Y’+Z)(X+Y’+Z’)(X’+Y’+Z)(X’+Y+Z)orf(X,Y,Z)= M(3,4,5,6)OR
f(X,Y,Z)=(M3+M4+M5+M6)
Solution:
Step 1: Mapping a standard POS expression
Binary values of the expression

(X+Y +Z)=010
(X+Y +Z )=011
(X +Y +Z)=110
(X +Y+Z)=100
Step 2: Grouping 0’s

As done in the above k-map
Step 3: Multiplying the resulting sum terms

The terms corresponding to these groups are (X+Y ) & (X +Z)
The final minimum POS expression can be written as the product of these 2 terms
corresponding to the 2 groups (X+Y ). (X +Z)
Answer the following question:

1. What are minterms? Give example .(1M,NOV/DEC-2009)
2. State Boolean laws corresponding to basic logic operations. .(3M.NOV/DEC-2009)
3. State and prove demorgan s theorem using truth table (3M,NOV/DEC-2009)
.(3MOCT/NOV -2012)
4. Simplify the Boolean expression given using k-map. .(4M,NOV/DEC-2009)
Y= m(1,3,4,6,8,9,11,12,13,14)
5. Simplify the Boolean expression given below .(2M,DEC-2010)
Y=(AB+AC) +A B C
6. Define the terms
a. overlapping cell
b. Redundant group,
c. adjacency cells,
d. rolling a map
7. Explain the method of converting product terms to standard SOP form and sum terms to
standard POS form
8. Simplify using k-map .(4M,OCT/NOV -2011)
F= m(1,2,3,5,7,10,11)
9. List all Boolean postulates.
F= m(0,1,3,9,11,2)
11. Prove that (A+B)(A+C)=A+BC. .(2M,OCT/NOV -2012)
Y= m(0,1,2,3,8,9,10)+d(4,5,6,7,11)
13. Develop a truth table for the standard POS expression (A+B +C)(A+B+C )(A +B +C )
Chapter-3
Logic gates
A gate is simply an electronic circuit which operates on one or more input signals to
perform a particular logical function
The basic gates are AND gate, OR gate & NOT gate
NAND,NOR,EX-OR & EX-NOR gates are the other most widely used gates
AND gate:
Logic symbol AND gate :
Function:
The AND gate is a logic element having two or more input terminals and only one
output terminal
Its output is at logical 1(high) only when all of its inputs are at logical 1(high)
If any one or more of the inputs are low then output of the gates will be low
Logical expression: Y=AB
Truth table
INPUTS OUTPUT
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
Application
AND gate is commonly used to enable the passage of a signal from one point to another at
certain times and to disable the passage of the signal at other times
OR gate:
Logic symbol OR gate
Function:
The OR gate is a logic element having two or more input terminals and only one
output terminal
The output of an OR-gate is high(1) if any one or more of its inputs are high(1),the
output is low(0) only when all of its inputs are low
Logical expression: Y=A+B
Truth table
INPUTS OUTPUT
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Timing Diagram
Application
OR gate can be used in an detection and alarm system
NOT gate (inverter)
Logic symbol NOT gate
Function:
The NOT gate is having one input and one output terminal.
It is also called as an inverter as it inverts its input.
It performs the operation called inversion or complementation or negation
When a high is applied to an inverter, a low will appear on its output.
When a low is applied to its input, a high will appear on its output
Boolean expression: Y=A
Truth table:
INPUTS OUTPUT
A Y Y=A'
0 1 ON
1 0 OFF
Pin Diagram
Timing Diagram
Application
NOT gates can be used to find the 1 s complement of an 8-bitbinary number.
NAND gate:
Logic symbol:NAND gate
Function:
The NAND logical function is equivalent to AND followed by an inversion
The output of a NAND gate is low only when all of its inputs are high.othrewise its
output is high
Boolean expression: Y= (A.B)
Truth table:
INPUTS OUTPUT
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
NOR gate
Logic symbol: NOR gate
Function:
The NOR logical function is equivalent to OR followed by an inversion
The output of a NOR gate is high only when all of its inputs are low.othrewise its
output is low
Boolean expression: Y= (A+B)
Truth table:
INPUTS OUTPUT
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
EX-OR gate
Logic symbol:EX-OR gate
Function:
The exclusive-OR gate is a combinational circuit with two or more inputs and one
output
The output of the EX-OR is high if one and only one input is high
When both the inputs are equal, then the output is also low
Boolean expression: Y=A + B i.e., A B+AB

Truth table:
INPUTS OUTPUT
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Application
An EX-OR gate can be used as a 2-bit adder
EX-NOR gate
Logic symbol: EX-NOR gate
Function:
The exclusive-NOR gate is a combinational circuit with two or more inputs and one
output
The EX-NOR function is the complement of an EX-OR function, and hence its output
is high only when its inputs are equal
Boolean expression: Y= (A + B) i.e., A B +AB
Truth table:
INPUTS OUTPUT
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
Pin diagram
UNIVERSAL GATE:
Logic gates that can be used to realize any of the basic logical operations like
AND,OR NOT,NAND ,NOR,EX-OR & EX-NOR is called universal gate
EX:NAND & NOR gates are universal gates
NAND as universal gate

Desired NOT Gate NAND Construction
s
Desired AND Gate NAND Construction
Desired OR Gate NAND Construction
Desired NOR Gate NAND Construction
Desired XOR Gate NAND Construction
Desired EX-NOR Gate NAND Construction
NOR as universal gate

Desired Not Gate NOR Construction
Desired OR Gate NOR Construction
Desired AND Gate NOR Construction
Desired NAND Gate

NOR Construction
Desired EX-OR Gate

NOR Construction
Desired XNOR Gate NOR Construction

Application
To implement a logic circuit with various gates, we require various ICs to be connected in the
circuit. but, if the same logic expression can be implemented using only NAND or only NOR
gates in the logic circuit can be used. This simplifies the implementation of logic expressions
Answer the following questions:
1. Write pin diagram of IC 7486 (3M,NOV/DEC-2009)

2. What is NOR gate? Write logic symbol and truth table (3M,NOV/DEC-2009)(DEC-
2010)
3. What is AND gate? Design AND gate using only (3M,DEC-2010)
4. i.NAND gate and
5. ii.NOR gate
6. Write logic symbol, Boolean expression and truth table of AND gate.
(2M,OCT/NOV-2011)
7. What is OR gate? Design OR gate using only. (3M,OCT/NOV-2011)
i.NAND gate and
ii.NOR gate
8. Write pin diagram of IC 7402. (1M,OCT/NOV-2012)
9. Realize AND, OR, X-OR gate using NOR gate and NAND gate (3M,OCT/NOV-
2012)
10. Write timings diagram for all logic gates
Chapter-4
Arithmetic circuits
Introduction
Logic circuit used to perform binary addition is called an adder. The Logic circuit
used to perform binary subtraction is called subtractor
Various types of adders like half adder, full adder, parallel adder, BCD adders
Adders and subtractors can be implemented by using NAND & NOR
The two basic arithmetic functions of addition and subtraction can be defined by the
rules
Binary addition
Inputs Sum Carry
0+ 0 = 0 0
0+ 1 = 1 0
1+ 0 = 1 0
1+ 1 = 0 1
Binary Subtraction
Inputs Diff Borrow
0 - 0 = 0 0
0 - 1 = 1 1
1 - 0 = 1 0
1 - 1 = 0 0
Half Adder
It accepts two binary digits on its inputs and produces two binary digits on its outputs called
the sum bit and carry bit
Logical symbol
Truth table
Inputs Outputs
A B Sum carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Logical expressions
Sum=AB + A B
Sum=A B
Carry=AB
Logic diagram
Half adder using NAND gates
Disadvantage of half adder

The half adder does not have carr y input from the previous stage
Full adder
The full adder circuit takes into account the carry from the previous stage. So it has three
inputs and produces two digits on its output called the sum and the carry out
Logical symbol
Truth table
Inputs Outputs
A B cin Sum carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Logical expression
Sum=A B C+A BC +AB C +ABC
=A (B C+BC )+A(B C +BC)
=A (B C)+A(B C)
Sum =A B C
Carry=A BC+AB C+ABC +ABC

=C(A B+AB )+AB(C +C)
=C(A B)+AB(1)
Carry =C(A B)+AB
Logical diagram
Half adder implementation of full adder
Full Adder Using Nand Gate

Half Subtractor
It accepts two binary digits on its inputs and produces two binary digits on outputs called the
difference bit and borrow bit
Logical symbol
Truth table
Inputs Outputs
X Y DIFF BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Logical expressions
Diff =X Y+XY
Diff =X Y
Borrow=X’Y
Logical diagram
Half subtractor using NAND gate

Full Subtractor
The full subtractor accepts borrow from previous stage .so it has three inputs
XYB0 .It has two outputs Difference and Borrow
Logical symbol
Truth table
Inputs Outputs
X Y B 0
DIFF BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Logical expressions
DIFF =X Y B+X YB +XY B +XYB

=X (Y B+YB )+X(Y B +YB)
=X (Y B) +X(Y B)
DIFF= X Y B
BORROW =X Y B+X YB +X YB+XYB
=X Y B+XYB+X YB +X YB
=B(X Y +XY)+X Y(B +B)
=B(X Y) +X Y(1)
BORROW= B(X Y) +X Y
Logical diagram
Full subtractor using two half subtractors
Parallel binary adder

Parallel binary adder can be formed by connecting two or more full adders. a single
full adder can add only two 1 bit numbers and an input carry
Consider addition of two 4 bit numbers. a group of 4 bits is called a nibble, let the
number be A4 A3 A2 A1 & B4 B3 B2 B1
C3 C2 C1
A4 A3 A2 A1
+ B4 B3 B2 B1
C4 S4 S3 S2 S1
Logic Diagram
4 Bit Parallel Binary Adder

The carries in parallel adder are handled by two methods . They are
1. Ripple carry adder
2. Carry look ahead adder
Ripple carry adder

A Ripple carry adder is one in which the carry output of each full adder is connected to the
carry input of the next higher order stage. This causes time delay because other stages cannot
operate without input carry
Carry look ahead adder

Carry look ahead adder speeds up addition process by eliminating ripple carr y delay.
The look ahead carry the output carry of each stage, and based on the inputs bits of
each stage, produces the output carry by either carry-generation or carry-
propagation
Carry-generation occurs when an output carry is produced internally by the full adder
Carry propagation occurs when the input carry is rippled to become the output carr y
4-bit binary adder-subtractor using IC 7483
Adder-Subtractor
It is a logic circuit that can be used to perform both addition and subtraction
Logic diagram of 4-bit binary adder-subtractor

The circuit is from right to left as in parallel adder circuit. The carry-out from each
full adder is the carry-in to the next –higher full adder.
The first number bits are input to the full adders directly, because whether addition or
subtraction, the first number (A4 A3 A2 A1) is going to be same.
For addition the second number (B4 B3 B2 B1) will be in true form .but in the
subtraction, the second number should be 2 s complement form to be added. this can
be achieved by using EX-OR gates as controlled inverters.
Each EX-OR gate has an input i.e. B4 B3 B2 B1 and another input is SUB
With SUB=0, the Bits reaches the full adders in true form
With SUB=1, the B bits are inverted. this gives the 1 s complement
The SUB line is connected to carry in of LSB full adder. this gives the 2 s
complement of the second number
Pin Diagram Of Adder-Subtractor Circuit
BCD Adder
BCD adder is an arithmetic unit which performs operations on numbers that are stored
in BCD form.
The BCD adder has 4 augends bits and 4 addend bits.
BCD can have only 10 outputs 0000 to 1001
The numbers 1010 to 1111 can be avoided by adding the bit pattern 0110
For solving for the output conditions 1010 to 1111 using K-map,
The Boolean expression is S4S3+S4S2 ,this is implemented using AND gates & OR
gates
IF a carry out is generated or if any of the combinations 1010 to 1111 occur, then any
of the OR gate 3 inputs will be a 1.this is used to generate pattern 0110 to be added to
the augends using another 4-bit binary adder so as to obtain the final sum
Pin Diagram For BCD Adder
Answer the following question

1. What is half adder? Write its truth table and logic gate circuit using XOR and basic
gates.(3M,Nov/Dec -2009) .(3M,Oct -2011)
2. What is half adder and half subtractor?.Write its truth table and logic circuit using NAND
gate
3. With the logical symbol and truth table explain full subtractor.write the logic circuit using
XOR and basic gates. .(4M,Nov/Dec -2009) .(3M,Oct -2011)
4. Write the logic gate circuit of half adder using XOR and basic gates .(1M,Dec -2010)
5. What is an adder? Draw the logic gate circuit of full-adder circuit using XOR and basic
gates explain. (3M, Dec -2010). (3M,Oct/Nov -2012)
Draw the logic circuit of full-adder using 2 half adder
6. What is half subtractor? Explain with logic diagram and truth table
(3M,Dec-2010)
(3M,Oct/Nov -2012)
7. With logic circuit diagram explain the action of 4-bit binary adder-subtractor. (4M,Dec -
2010) (4M,Oct/Nov -2012)
8. With logic circuit diagram, explain the action of 4-bit binary adder. (4M,Oct -2011)
Chapter-5
FLIP FLOP
Digital circuits whose output depends entirely on the inputs to the circuits. such logic
circuits were called combinational logic circuits
Sequential circuits are a digital circuit whose output not only depends on the current
inputs, but also on the previous state of the circuit. It involves timing and memory
devices.
Flip flop is the basic memory element in a digital computer.
It is used to store one bit of information with a 0 or a 1.It is also called the binary or
toggle or latch.
Characteristics of flip flop

1) It is a bistable device. The circuit has only two stable states o & 1. It responds to inputs of
retains its state until some signal causes it to change state.
2) The flip flop has two outputs. One output is the complement of the other.
Latch
It is commonly used at the output of a digital device to hold the data until the next device is
ready to receive the input.
Latch Filp f lop

1.it does not have a clock signal 1.a flip flop always has clock signal
2.a latch is synchronous 2 a flip flop is asynchronous
3.it is level triggered 3.it is edge triggered
4.it is faster 4.it is slower
5.it is sensitive to glitches 5.it is immune to glitches
6.number of gates used are less 6.number of gates used are more
7.implementation takes less power 7.implementation takes more power
Necessity of clock in digital circuits

The clock measures time and sends out regularly spaced signals .these signals are
called clock pulse
The clock wave form is a square wave as shown in fig .there are two edges called
leading edge or positive or rising edge and falling or negative or trailing edge
Types of triggers
Flip flop can either be level triggered, positive edge triggered or negative edge triggered,
depending on which position of the clock wave form is used to activate the flip flop.
a. Negative Edge Trigger b. Level Triggered c. Positive Edge

Trigger
Types of flip flop

1. RS flip flop
2. D flip flop
3. JK flip flop
4. T flip flop
5. Master slave JK flip flop
RS flip flop (Reset-set flip flop)

The flip flop is enabled or activated using logic 0.so S and R inputs have inverted bubbles.
This is shown in the diagram
Inputs Outputs
S R Q Q' Mode Of Operation Effect On Output X
No Change-Previous State
1 1 Q Q Hold Retained
0 1 1 0 Set For Setting X To 1
1 0 0 1 Reset For Resetting X To 0
Prohibited Or
0 0 1 1 Forbidden Invalid Condition
If both S and R inputs are 1 it is the idle this is called the hold condition . There is
no change in the state of the flipflop.the previous state is retained
When input S is 0 and R is 1 , the output Q is set to 1.this is called set condition . It is
used to set the flip-flop to 1
When input S is 1 and R is 0 , the output Q is set to 0.this is called reset condition . It
is used to clear the flip-flop to 0
When both the inputs are 0 , both outputs go to logical 1 or set and reset the flip flop
simultaneously. This state is called forbidden or prohibited or racing or invalid
state
An RS flip flopcan be wired using NAND gates
Timing diagram or wave form for a flip flop the horizontal distance is time and the vertical
distance is voltage
Clocked RS flip flop (Reset-set flip flop)
The logic symbol for clocked SR flip flop is shown in fig
It has 3 inputs, S(set), R(reset), C (clock).

It has an output Q & a complement output Q .The flip flop responds to a positive
transition from 0 to 1 of the input clock signal.
The two important features of clocked RS flip flop are-
1. Synchronous operation: the output of the flip flop changes only on clock pulse
2. Memory characteristic: even if the input are changed the state of flip flop does not
change until a clock pulse is applied
The characteristic table or truth table
Outputs
Inputs Q(t+1)
S R Q Q' Mode Of Operation Effect On Output X
0 0 Q Q Hold No Change
0 1 0 1 Reset Reset To 0
1 0 1 0 Set Set To 0
Prohibited Or
1 1 1 1 Forbidden Should Not Be Used
Working or operation of RS flips flop
When the clock signal changes from 0 to 1 the output is affected according to the values in
inputs S & R.
The following cases occur
If both S & R are 0 during the clock transition, the output does not change.
If S=1 & R=0 the output Q is set to 1
If S=0 & R=1 the output is cleared or reset to 0
If both S & R are 1, the output is unpredictable and may be either 0 or 1 depending on
internal timing delays that occur within the circuit. This is said to be the indeterminate
state of forbidden state.
RS flip flop using NAND gates
Timing diagram for clocked RS flipflop
D flip flop
The D flip flop is a flip flop with a single data input D and a clock input C.therfore it
is called data flip flop.
The D flip flop is also known as the delays flip flop. The word “delay” describes what
happens. To the data at input 0.The data at D input is delayed by one clock pulse
before it gets to the output Q.
Working or operations of D flip flop

CLK D Q Q'
0 0 1 CLEAR TO 0
1 1 0 SET TO 1
The D flip flop can be formed from a clocked RS flip flop by adding an inventor or
NOT gate. The D input is connected to S input of RS flip flop directly
The D input is connected to R input of RS flip flop through the inventor.
The typical commercial D flip flop contain two extra inputs PRESET (P) AND CLEAR
(CLR).
The presetand clear inputs are called asynchronous inputs as they act on the flip
flop independent of the clock.
The bubble at these inputs that the active signal is 0 .
The Dinput is called thesynchronous inputas it activates the flip flop only in
synchronism with the clock pulse.
Always the asynchronous inputs overridethe synchronous inputs.
Working truth table
Asyn-Inputs Syn-Inputs Outputs Mode Of

PRESET CLEAR CLK D Q Q' Operation
0 1 X X 1 0 Asyn SET
1 0 X X 0 1 Asyn RESET
0 0 X X 1 1 Prohibited
1 1 _ 1 1 0 SET
1 1 _ 0 0 1 RESET
When an PRESET=0 and CLEAR=1 input, and the D and CLK inputs may be
anything, the asynchronous input overrides and the flip flop set to 1
When PRESET=1 and CLEAR=0 then the D and CLK inputs may be anything, the
output is asynchronous RESET
When both PRESET & CLEAR are 0 then the output is prohibited
When both inputs of asynchronous are equal to 1(not active) then D is 1after one
clock pulse, the flip flop output set 1
When both inputs of asynchronous are equal to 1(not active) then D is 0 after one
clock pulse, the flip flop output reset0
Applications
1) D flip flop are widely used as temporary memory devices.
2) They are wired together to form shift registers and storage registers commonly used in
digital systems.
JK flip flop (JOCK KILBY)

It is a versatile and widely used type of flip flop
CLK INPUTS OUTPUTS mode of effect on output

J K Q Q' operation Q
0 0 Q Q' Hold no change
0 1 0 1 reset reset or cleared 0
1 0 1 0 set set to 1
0 TO 1 1 TO 0 changes to
1 1 1 TO 0 0 TO 1 Toggle opposite state
Working or operations of JK flip flop

1) When J & K inputs are both 0, the data inputs have no effect on the outputs. The flip flop
is said to be in the hold state.
2) when J=0 & K=1, the flip flop is reset or cleared to 0, then it said to be in the reset state.
3) When J=1 & K=0, the flip flop I s set to 1. Then it is said to be in the set state.
4) When both J & K ar e 1, if the state of the flip flop was 0, applying clock pulse causes it to
change 0 to 1 & vice versa called toggling.
Toggling
It is defined as the change of output in a JK flips flop alternatively b/w 0 to 1 for every clock
transition
Racing
It can be defined as toggling (change of 0 to 1 and 1 to 0 alternatively) more than once during
one clock cycle in JK flip flop.
The J input is equivalent to the S input of SR flip flop and the K input is equivalent to
the R input of SR flip flop.
JK flip flop can also implemented by using NAND gates
JK flip flop can be wired using RS flip flop
J K Q(t+1) mode of operation

0 0 Q(t) Hold
0 1 0 reset
1 0 1 set
1 1 Q(t)' Complement
Working or operations of JK flip flop
1) When J & K inputs are both 0, the data inputs have no effect on the outputs. The flip flop
is said to be in the hold state.
2) when J=0 & K=1, the flip flop is reset or cleared to 0, then it said to be in the reset state.
3) When J=1 & K=0, the flip flop I s set to 1. Then it is said to be in the set state.
4) When both J & K ar e 1, if the state of the flip flop was 0, applying clock pulse causes it to
change to 1 & vice versa called toggling.
In order to avoid the racing condition in JK flip flopnegative

the edgetriggered type or
master slave JK flip flop can be used
The operation of negative edge triggered flip flop can be explained with the truth table
INPUTS OUTPUT
Asynchronous synchronous MODE OF
PR CLR CLK J K Q Q' OPERATION
0 1 X X X 1 0 asynchronous set
1 0 X X X 0 1 asynchronous reset
0 0 X X X 1 1 prohibited
1 1 1 0 0 NO CHANGE hold
1 1 1 0 1 0 1 RESET
1 1 1 1 0 1 1 SET
OPPOSITE
1 1 1 1 1 STATE TOGGLE
Applications
JK flip flop are used in many digital circuits especially its toggle feature is used in counters.
JK flip flop are also used as frequency divider.
T flip flop
It is also known as toggle flip flop
Logical symbol
This type of flip flop can be obtained from a JK flip flop when input J & K are connected to
provide a single input designated by T.
So the T flip flop has only two conditions

1) When T=0 (J=0, K=0) a clock transition does not change the state of the flip flop.
2) When T=1(J=1, K=1) a clock transition complements the state of the flip flop.
Truth table
T Q(t+1)
0 Q(t) No change
1 Q(t)' Complement
Pin diagram of IC 7476
INPUTS OUTPUT
Asynchronous synchronous
PR CLR CLK J K Q Q'
0 0 X X X 1 0
1 1 X X X 0 1
1 1 0 0 Q Q'
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 Q Q'
Master slaves JK flip flop

In Master Slave JK flip flop consists of two flip flops.
The first is the master, which responds to the positive edge of the clock. The second is
the slave, which responds to the negative edge of the clock. The output changes only
during the negative edge transition of the clock.
Logical symbol
This helps in avoiding the racing condition in JK flip flop where it can be triggered
only once within a clock cycle.
Since the output of the second flip flop follows that of the first JK flip flop, the names
master and slave are used.
Operating characteristics of flip flops
Propagation delay time (t d )

It is the interval for time required after an input signal has been applied for the
resulting output change to occur
Set-up time(ts )
It is the minimum time interval required for input logic levels to be maintained constat
before the triggering edge of the clock pulse to have reliability.
Hold time(th )
It is the minimum time interval required for logic levels to remain on the inputs after
the triggering edge of the clock pulse inorder that the levels be reliably clocked into
the flip flop.
Maximum clock frequency(f max )

It is the highest rate at which a flip flop can be reliably triggered
Power dissipation
It is the total power consumption of the device.
Application of flip flops

1. Flip flop have an important characteristic of storage capability so they are widely used
in registers.
2. It can be used to divide frequency of periodic waveform. They are said to be used as
frequency dividers.
3. They can also be used to count the number of clock pulses in digital counters.
1. Mention the advantage of master –slave flip flop(1M, NOV/DEC-2009) (1M,

OCT/NOV-2011)
2. Write the block diagram to show the conversion of J-K flip flop to T flip flop (1M,
NOV/DEC-2009)
3. Explain the action of clocked RS flip flop using NAND gate circuit. Write its operation
table. (3M, NOV/DEC-2009)
4. What is race around condition? How it is eliminated? (3M, NOV/DEC-2009)
5. What are the important characters of flip-flop? (1M,DEC-2010)
6. Give the function of preset and clear input in flip flop. (1M, DEC-2010)
7. With the logic gate circuit and truth explain the operation of D-flip flop. (3M, DEC-
2010)(3M, OCT/NOV-2011)
8. With logic circuit and truth table, explain the action of J-K flip flop. (3M, DEC-2010)
9. What are flip-flops? (1M, OCT/NOV-2011)
10. Write any two differences between flip flop and latch (1M, OCT/NOV-2011)
11. With logic circuit and truth table, explain the action of RS flip flop. (3M, OCT/NOV-
2011) (3M, OCT/NOV-2012)
12. With logic circuit and truth table, explain the action of T flip flop. (3M, OCT/NOV-
2012)
Chapter-6
Shift Register
A register is a group of memory cells grouped together to form a single unit
A register can be used in two ways
1. To simply store information for later use
2. To act on data i.e., contents can be modified by shifting data right or left
The register used to store data may be called latch. These are constructed using D flip
flops
The Shift Registeris another type of sequential logic circuit that is used for the
storage or transfer of data in the form of binary numbers and then "shifts" the data out
once every clock cycle, hence the name "shift register".
The basic functions of shift register are
Storage capacity
Data movement
The storage capacity of a register is the total number of bits of digital data it can
retain, so the number of stages in a register determines its storage capacity.
The shifting capability of a register permits the movement of data from one flip flop
to another within the register or into or out of register by applying clock pulse
Basic data movements in shift registers
Data movement or shifting can be done in two ways
1. Serial shifting : shifting data one bit at a time in a serial fashion beginning with MSB
or LSB bit
2. Parallel shifting : shifting all data bits simultaneously.
Types of shift register
1. Serial-in to Serial-out (SISO)

2. Serial-in to Parallel-out (SIPO)
3. Parallel-in to serial -out (PISO)
4. Parallel-in to Parallel-out (PIPO)
Serial-in to Serial-out (SISO) :

The data is shifted serially "IN" and "OUT" of the register, one bit at a time in either a
left or right direction under clock control.
A 4 bit shift register can be implemented with D flip flops. It can store up to 4 bits of
data
4-bit Serial-in to Serial-out Shift Register
Fig shows entry of 4 bits 0101 into the register. The register is initially CLEAR. It has
all 0s in the 4 flip flops.
The first LSB bit 1 is put onto the data input line making D=1 for FFA.when the first clock
pulse is applied, FFA is set, thus storing a 1
Second bit 0 is applied to data input making D=0 when the second clock pulse is applied, the
0 is shifted into FFA and the 0 from FFA is shifted into FFB
The third bit 1 is applied to data input making D=1 when third clock pulse is applied, 1 is
shifted into FFA, 0 from FFA is shifted into FFB, 1 from FFB is shifted into FFC
The last MSB bit 0 is now applied to data input and fourth clock pulse is applied, then 0 is
shifted into FFA, the 1 shifted from FFA to FFB,the 0 is shifted from FFB to FFC and the 1
is shifted from FFC to FFD
This completes the entry of the 4 bits serially into the shift register on applying 4 clock
pulses.
When fifth clock pulse is applied, the bits keep moving to the right and so the bit 1 appears on
Q output.
Serial-in to Parallel-out (SIPO)
The register is loaded with serial data, one bit at a time, with the stored data being
available in parallel form. This means all bits i.e., output of each stage is available
simultaneously once data is stored.
4 -bit Serial-in to Parallel-out Shift Register
Basic Movement of Data through a Shift Register

Clock Pulse No QA QB QC QD
0 0 0 0 0
1 10 0 0
2 0 10 0
3 0 0 10
4 0 0 0 1
5 0 0 0 0
Parallel-in to Serial-out (PISO)
The parallel data is loaded into the register simultaneously and is shifted out of the
register serially one bit at a time under clock control.
Logical diagram of PISO
There is a SHIFT/LOAD input. It allows two operations

When SHIFT/LOAD is LOW .the data should be placed on D0,D1,D2,D3
and a clock pulse applied to load data into the register
When SHIFT/LOAD is HIGH, data bits can be shifted right from one stage to
the next
Parallel-in to Parallel-out (PIPO)
The parallel data is loaded simultaneously into the register, and transferred together to
their respective outputs by the same clock pulse.
4-bit Parallel-in to Parallel-out Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register. The data
is presented in a parallel format to the parallel input pins P A to P D and then transferred
together directly to their respective output pinsA toQ QA by the same clock pulse.
Then one clock pulse loads and unloads the register.
Shift register application

Some of the applications of shift registers are:
1. Time delay generation
2. Serial to parallel data converter in UART(universal asynchronous receiver
transmitter
3. In a calculator
Time delay generation

The serial in serial out shift register can be used to provide a time delay from input to
output this time delay is a function of the number of stages (n) in the register and the
clock frequency.
For example of a clock frequency of 1MHz is used with an 8 bit register, a time delay
of 8 ms (8 1 ms) can be achieved.
The time delay can also be increased by cascading shift registers and decreased by
taking the outputs from successively lower stages in the register if the outputs are
available.
Universal asynchronous receiver transmitter (UART)

Shift registers can be used to construct serial to par allel data converter. Often
microprocessor based systems that send and r eceive par allel data must communicate
with external devices that send and/or receive serial data. An interfacing device called
UART is used to accomplish serial to parallel and parallel to serial conversions
The UART receives data in serial format, converts the data to parallel format and
transmits them on the data bus. The UART also accepts parallel data from the data
bus, convert the data to serial format, and transmits them to an external device.
The data bus is a set of parallel wires along which data move between the UART and
the microprocessor system. Buffers interface the data registers with the data bus.
In a calculator
We enter each digit on the keyboard of the calculator, the numbers shift to left on the
display.
The key press information from the keyboard encoder is held by the register before
being sent to the processing unit. Another register is used for temporary storage
between the processing unit and the decoder before it is displayed.

1. Differentiate between serial in serial out and parallel in – serial out shift registers .(1M
NOV/DEC 2009)
2. Draw blocks diagram r epresentation of serial in parallel out register. Give its truth
table and draw timing diagram. .(3M NOV/DEC 2009)
3. What are sequential logic circuits? .(1M DEC 2010)
4. What are registers? With logic diagram explain the action of 4 bit SISO register. .(3M
DEC 2010)
5. What are shift registers? With logic diagram explain the action of 4 bit SISO register.
.(4M OCT/NOV 2012)
6. What are shift registers? With logic diagram explain the action of 4 bit SIPO register.
.(4M OCT/NOV 2011)
Chapter-7
Combination logical circuits
When logic gates are connected together to produce a specified output for certain
specified combinations of input variable, the resulting circuit is called a combination logical
circuits .
In this circuit there are inputs logic gates and output. The output is purely dependent
only on the present inputs.
Implementing logic circuit from Boolean expression

An AND-OR logic circuit directly implements an SOP sum of products expression,
assuming the complements of the variables are available.
When AND-OR circuit is complemented, it results in and AND-OR invert logic circuit. This
circuit can be used to implement a POS product of sum expression.
Implementing logical circuit from truth table

Given the truth table first the product terms for output high condition are all listed.
From this sop expression in built.
It is then simplified.
Then logical circuit can be implemented for the simplified sop expression using AND,
OR and NOT gates.
INPUTS OUTPUTS
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1 A'BC
1 0 0 0
1 0 1 1 AB'C
1 1 0 1 ABC'
1 1 1 0
Magnitude comparator
A logic circuit that is used to compare magnitudes is called a
magnitude comparator. It
compares two quantities and indicates whether they are equal.
One number (binary form) is applied to input A, another number (binary form) is applied to
input B.
On comparison of their magnitudes
If A>B, that output is high and two are low.
If A=B then that output line has a high and remaining two outputs are low.
If A<B, then that output line has a high and the remaining two outputs are low.
In a 4 bit comparator, the highest order bits are first examined for inequality in that bit
position. If any inequality is found, the relationship of the two numbers is established and any
other inequalities in lower order bit positions are ignored.
To determine an inequality, the following conditions are possible.

If A=1 and B=0, A is greater than B
If A=0 and B=1, A is less than B
If A=B, then the next lower bit position should be examined for inequality.
Code conversion circuits

A codeis a set of bits arranged in a unique pattern that is used to present specified
information.
A code converteris a circuit used to convert one form of coded information to

another coded form.
Code conversion circuit can per form two typesof functions.
1. Encoding function
2. Decoding function
Encoder
It converts information such as a decimal number or an alphabetic character into some
coded form.
For example a circuit that converts each of the decimal digits 0 through 9, to a binary
code is called decimal to BCD encoder .
Decimal BCD
INPUTS OUTPUT
D A3 A2 A1 A0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
Truth table for decimal to BCD
Logic diagram for decimal to BCD encoder
Decoder
It converts coded information, such as binar y number into a non-coded form, such as
decimal form.
For example. One particular type of decoder converts a 4-bit binary code into the
appropriate decimal digit.
The basic function of a decoder is to detect the presence of a specified combination of

bits (code) on its inputs and to indicate the presence of that code by a specified output
level.
A general decoder has „n input lines to handle „n bits and 2 n output lines to indicate
the presence of one or more n-bit combinations
Ex:- 1 of 4 decoder
Number of input lines is 2
Output combinations possible are 2 2 =4. So there are 4 output lines.
It is named as 1 of 4 decoder because only 1 of the 4 output lines is high, depending on the bit
pattern.
If AB=00, Y0 is high;
If AB=01 then Y1 is high.
If AB=10 then Y2 is high.
If AB=11 then Y3 is high. This is a 2 bit decoder.
Data selection circuits

Circuits that are used for data selection are called data selection circuits. they are of
two types
1. Multiplexer (MUX)
2. Demultiplexer (DEMUX)
Multiplexing means may to one
Demultiplexing means one to many
Multiplexer (MUX)
A multiplexer has several data-input lines and a single output lines. It also has data
select inputs (control lines or control signals) which permit digital data on any one of
the inputs to be switched to the output line. it is also known as data selector
It has 2n input line, n selected lines and 1 output line
For ex, consider a 4-input multiplexer. Control signals or data select signals will be 2
bits because with two bits, any one of the four data input lines can be selected.
If S1S0=00 is applied to the data select lines, data on input D0 appears on the output
line.
If S1S0=01 then data on D1 appears on the output line.
If S1S0=10, then data on D2 will appear on the output.
If S1S0=11, then data on D3 will appear on the output.
Demultiplexer (DEMUX)
It is a logic circuit that switches digital data from one input line to several output lines
in a specified time sequence. it is also known as a data distributor .
It has one input line, „n select lines and 2 n output lines.
For ex: consider a 1 to 4 demultiplexer circuit. The two data select lines enable only
one gate at a time and data appearing on the data-input line will pass through the
selected gate to the output lines.
Parity generators/checkers
In a digital system while codes are being transf erred from one point to another, error
can occur. There will be undesired changes in the coded information like a 0 may
change to 1 may change to 0.
Error detection can be done using parity bit.
The sum of two bits can be generated by an EX-OR gate. When the number is 1s on
the inputs is even, the output is low and when the number of 1s is odd, the output is
high.
It is used to check for odd or even parity on a 9 bit code. (1 bit parity+8 data bits).
The inputs are labelled an A to I.
When number of 1s on the inputs is even, even output is high and odd is low.
When number of 1s on the inputs is odd, an odd output is high and even is low.
Parity checker
When this device is used as an even parity checker , the number of input bits should
always be even. When a parity error occurs the even output goes low and the odd
output goes high.
When it is used as an odd parity checker the number of inputs bits should always be
odd. When a parity error occurs, the odd output goes low and the even output goes
high.
Parity generator
When this device is used as an even parity generator the parity bit is taken at the odd
output because their output is a 0. If there is an even number of input bits and it is a 1
if there is an odd number.
When used as an odd parity generator, the parity bit is taken at the even output
because it is a 0 when the number of inputs is odd.
1. Prove (AB) =A +B by truth table method and write its logic .(2M,OCT/NOV-
cir cuit
2011)
2. Write the Boolean logic diagram for expression Y=AC+AB C+ABC
.(2M,OCT/NOV-
2011)
3. Design a BCD to decimal decoder circuit.
4. Describe the working of an encoder.
5. What is a multiplexer and demultiplexer?
6. Design a 4 to 1 multiplexer and 1 to 8 demultiplexer circuit.
7. Explain parity generator/checkers.
Chapter-8
Integrated circuits and digital functions
Using advanced techniques a manufacturer can produce miniature circuits of the
surface of a small piece of semiconductor material calledchip. a Such a circuit is
called an Integrated circuit(IC).
There are two basic techniques for manufacturing ICs are
1. Bipolar technique.
2. Metal oxide semiconductors (MOS) technique
A digital IC family is a group of compatible devices with the same logic levels and
supply voltages
Scale of integration or Classification of integrated circuits

The number of gats that can be put in a single chip
a) Small scale integration (SSI)
It contains several independent gates in a single package. The inputs and outputs of
the gates are connected directly to the pins in the package. The number of gates is usually less
than 10 and is limited by the number of the pins available in the IC.
b) Medium scale integration (MSI)
It has approximately 10 to 200 gates in a single package. They perform specific
elementary digital functions such as decoders, adders and registers.
c) Large scale Integration (LSI)
It contains b/w 200 and a few thousand gates in a single package. They include digital
systems such as processors, memory chips and programmable modules.
d) Very large scale integration (VSIL)
It contains thousands of gates within a single package. They include large memory
arrays and complex microcomputers chips.
e) Super large scale integration (SLSI)
Between 10,000 and 1, 00,000 transistors within a single package and perform
computational operations such as microprocessor chips, micro-controllers, basic PICs and
calculator
f) Ultra large scale integration (ULSI)
More than 1 million transistor and it is used in computers CPUs, GPUs, Video
processors, micro-controllers
Logic families
The IC technology usually depends on the following factors :-
a) Speed
b) Power dissipation
c) Noise immunity
d) Input/output interface compatibility
e) Cost.
Compatibility
It means that we can connect the output of one device to the input of another.
Interfacing
It is defined as the design of the interconnections between circuits that shif t the voltage levels
and current levels to make the compatible.
Digital integrated circuits

The advantages if ICs being used in digital system are many
Small size
High reliability
Low cost
Low power consumption
There are two broad categories of digital ICs. They are:-

a) Fixed function logic.
b) Programmable logic.
Fixed function logic : - The logic functions of the IC are set by the manufacture and cannot
be altered.
Programmable logic : - The logic functions of the IC can be altered later.
Pin numbering
At the top of the package, pin 1 is indicated by an identifier that can be a small dot, a
notch, or a leveled edge.
The dot is next to pin 1 with the notch oriented upward, the top left pin is 1.
The highest pin number is always to the right of the notch or opposite the dot
The two basic techniques for manufacturing Ics are

a) Bipolar technique.
b) Metal oxide semiconductor (MOS) technique.
Classifications of digital IC families

Digital IC families are broadly classified as
1) Bipolar families
2) MOS families
The basic families in the bipolar category are

1) Resistor transistor logic.
2) Diode transistor logic.
3) Transistor transistor logic.
4) Emitter coupled logic
The basic families in the MOS category are

1) P channel MOSFET (PMOS)
2) N channel MOSFET (NMOS)
3) Complementary MOSFET (CMOS)
Characteristics of IC family gates
There are five basic char acteristics are

Power dissipation
Propagation delay
Fan in
Fan out
Noise margin
Power dissipation
This is the power consumed by the gate
It is the product of dc voltage and current
Power dissipation of a circuit or system defines battery life the greater the power
dissipation the shorter the battery life
Power dissipation is proportional to the heat generated by the chip or system
excessive heat dissipation may increase operating temperature cause gates to
generate improper output values
Propagation delay
The term propagation delay refers to the average time it takes the input signal to
propagate to the output
Fan in
Fan in is the number of inputs a gate has like a 2 input AND gate has fan in of two ,a
3 input NAND gate has fan in of three and so on
Fan out
The number of gates that each gate can drive while providing voltage levels in
the guarantied range is called the standard load or fan out
The fan out really depends on the amount of electric current a gate can source
or sink while driving other gates
Noise margin
Noise margin refers to the maximum noise voltage that can be added to the generated
signal in a digital circuit before an undesirable change is caused in the circuit output
Transistor transistor logic (TTL)
In this technology the diodes were replaced by transistors to improve the circuits
operations and the logic family was called TTL.
It is a class of digital circuits builds from bipolar function transistors and resistors. It
is called TTL
Because both the logic gating function AND and the amplifying function are
performed by transistors
Applications
Computers, industrial control, test equipments and instrumentation, consumer
electronics, synthesizers etc..
TTL ICs are examples of SSI to LSI.
There are several variation of TTL family.

Standard TTL
High speed TTL
Low power TTL
Schottky TTL
Low power schottky TTL
Advanced schottky TTL
Low voltage TTL
Emitter coupled logic (ECL):-

It is a logic family in which current is steered through bipolar transistors to compute
logical function. It is sometimes called current mode logic.
Characteristics
ECL is that the transistors are always in the active region.
It can be change state ver y r apidly.
It operates at very high speed.
The propagation time can be less than a nanosecond.
The large current requirement is approximately constant and does not depend
significantly on the state of the circuit.
Disadvantages
The circuits require a lot of power.
Most of this power is wasted as heat.
Usage
It is used in high speed application.
Older high and mainframe computers used ECL
It is used in systems such as supercomputers and signal processors where high speed
is essential.
Metal oxide semiconductors (MOS)
The metal oxide semiconductor is a unipolar transistor that depends on the flow of
only one type of carrier, which may be electrons (n channel) or hole (p channel).
The triple compound “metal oxide semiconductor” is a reference to the nature of the
physical structure of the field effect transistors.
CMOS complementary MOS

CMOS is sometimes explained as complementary symmetr y metal oxide
semiconductors.
The word “complementary symmetry” refers to the fact that the typical digital design
style with CMOS user complementar y and symmetrical pairs of electronic devices p
type and N type MOSFETs for logic functions.
Characteristics
1) They have a very high input resistance.
2) They are compatible with one another.
3) They possess high noise immunity.
4) They have low static power supply drain.
5) CMOS allows a high density of logic functions on a chip.
6) Heat dissipation is low.
7) It is simple.
8) Sophisticate protection circuitry.
Usage
It is used in chips such as microprocessors, micro controllers, static RAM and other
digital logic circuits.
CMOS technology is also used for a wide variety of analog circuits such as image
sensor, data converts and highly integrated transrecievers for many types of
communication.
Current IBM mainframes use CMOS.
They are also used in battery powered equipment such as pocket calculators, digital
wrist watches and portable computers.
Advantages
These devices dissipate less power.
Their operation speed is high.
Manufacturing costs are low.
Resistance
Free electrons tend to move through conductors with some degree of friction, or
opposition to motion. This opposition to motion is more properly called resistance.
Or
Opposition to the flow of current
Or
The property of the materials which opposes the flow of electric current
The unit of resistance is ohm.
A wire is said to have a resistance of 1 ohm if a potential difference of 1 volt across
its ends causes 1 ampere of current to flow through it.
Short circuit
A short circuit is an electric circuit offering little or no resistance to the flow of
electrons.
Open circuit
An open circuit is one where the continuity has been broken by an interruption in the
path for electrons to flow.
Closed circuit
A closed circuit is one that is complete, with good continuity throughout
Switch
A device designed to open or close a circuit under controlled conditions is called a
switch.
Ohms law
Discovered by George Simon ohm and published in his 1827 paper, the galvanic
circuit investigated mathematically.
“It states that the amount of electric cur rent through a conductor in a circuit is directly
proportional to the voltage across it, for any given temperature.”
If „V be the potential difference across the conductor and „I be the current flowing
through the conductor then I a V or V a I or V=IR where „R is a constant of
proportionality and is called the resistance of the conductor.
The three forms of the ohm s law are
1. V=I.R
2. I=V/R
3. R=V/I
Application of ohm’s law

Ohm s law is a very simple and useful tool for analyzing electric circuits. It is ver y
often in the study of electricity and electronics.
Voltage divider circuit (series circuit)

The circuit in which resistance are connected end to end, so that the same current
flows through all the resistances is called a series circuit or voltage divider circuit .
In fig, three resistances R1, R2 and R3 are connected in series. The source of
electrical energy is the battery V. the direction of current flow is from the positive
terminal of V through the resistors to the negative terminal.
By using ohm s law, the voltage drops across the resistances R1, R2 and R3, can be
written as
V1=IR1
V2=IR2
V3=IR3
The voltage across the batter y is equal to the sum of the voltages across the
resistances.
So
V= V1+V2+V3
IR1+IR2+IR3
V= I (R1+R2+R3)
The total resistance between points A and B is R T =V/I

RT =R1+R2+R3
This is shown in fig
Hence, when a number of resistances are connected in series the total resistances is
equal to the sum of the individual resistances.
The total resistances of a number of resistances connected in series is equal to the
sum of individual resistances
Voltage divider circuit

A series resistor circuit is called a voltage divider circuit because the voltage across
any one resistor is a fraction of the total voltage applied across the series combination
this fraction voltage value can be determined by the values of the resistances
o V1=V x R1/R1+R2+R3
Current divider circuit (parallel circuit)

A circuit in which one end of each resistance is joined to a common point and the
other end of each resistance is joined to another common point so that there are as
many paths for current flow as the number of resistances is called parallel circuit or
current divider circuit .
In figthree resistances R1, R2 and R3 are connected in parallel. The source of dc

energy is the battery V. the direction of current flow is from the positive terminal of V
through the resistors R1.R2 and R3 and then back to negative terminal of V. since
there are three resistances, there are three current paths.
By using ohms law. We have current through each resistance as
I1=V/R1
I2=V/R2
I3=V/R3
The current I is the total of the currents through the individual resistors
So we have I =I1+I2+I3
=V/R1+V/R2+V/R3
I =V (1/R1+1/R2+1/R3)
The total or effective resistance R T of the parallel resistances can be written as
I/RT = 1/R1+1/R2+1/R3
The reciprocal of total resistance of a number of resistances connected in parallel
is equal to the sum of the reciprocals of individual resistances.
From this we observe that the total resistance of a parallel circuit is always less than
the smallest of the resistances.
Also if there are „n resistors Connected in parallel each of R then total resistance
RT =R/n
for ex
If R1=R2=R3=R, Then „n number of resistances is 3
Then 1/RT = 1/R1+1/R2+1/R3
1/R+1/R+1/R
1/RT =3/R or RT =R/3
Current divider circuit .

A parallel resistor circuit is called a current divider circuit because the current across
any one resistor is a fraction of the total current in the circuit. The fractional current
depends on the values of the resistances
Total current I= V/R T
Total resistance I/R T = 1/R1+1/R2+1/R3
RT = R1R2R3/R1R2+R2R3+R3R1
Current through resistor R1 is given by
I1= V/R1
I = V/R T
I1/I= V/R1/V/R T
= R T
/R1
I1 = I [R2R3/ (R1R2+R2R3+R3R1)]
Or
I1= I (R2R3/R1R2+R2R3+R3R1)
I2= I (R1R3/R1R2+R2R3+R3R1)
I3= I (R1R2/R1R2+R2R3+R3R1)
Series parallel circuit

This circuit is a combinational of series and parallel circuit
In fig R2 and R3 resistances are connected in parallel with each other both to-gather
are in series with resistor R1.always first the par allel branches should be reduced to
and equivalent series branch and then he circuit is solved for simple series circuit
For parallel combination of R2 and R3
RTP =R2R3
R2+R3 because 1/R T
=1/R2+1/R3
Total circuit resistance=R1+RTP

RT =R1+ R2R3
R2+R3
Voltage across parallel combination
VP =I x RTP
VP =I x (R2R3/R2+R3)
Total voltage V=voltage across R1+voltage across parallel combination
V=IR1+I(R2R3/R2+R3)
V=I(R1+ (R2R3/R2+R3))
Current I=V/(R1+ (R2R3/R2+R3))
I2=VP/R2
= I x (R2R3/R2+R3)
R2
=I x (R2R3/R2+R3)
R2/1
=I x R2R3 x 1
R2+R3 R2
I2= I x R3
R2+R3
I3=VP/R3
I3= IxR2
R2+R3
Kirchhoff’s laws
Gustov Kirchhoff and German physicist worked on the principles governing the
behavior of electrical circuits. His findings ar e specified in two laws called
(i) Kirchhoff s current law (KCl)
(ii) Kirchhoff s voltage law (KVL)
Important terms
Circuit element
A circuit component with two terminals by which it can be connected to other
electric components is known as circuit element
Eg.resistor, inductor
Active elements
Circuit elements which can work independently and supply energy to a
network are called active elements
Eg: batteries, generators
Passive elements
Circuit elements which either absorb or store energy and their action depends
on the active elements are called passive elements
Eg: Resistors, inductors, capacitors
Branch
A part of any network connected between two nodes is called branch of a
circuit
Loop
A single closed path for the flow of current irrespective of active or passive
elements in a network is called a loop
Mesh
A loop which is independent i.e., which does not contain other loops within is
called a mesh
Node
It is an electrical junction in a circuit at which two or more circuit elements are
connected together
Kirchhoff’s current law (KCL) or Kirchhoff’s node or junction law or Kirchhof f’s first
law
“It is stated as the algebraic sum of all current entering and exiting a junction in an
electrical circuit is zero.”
Ientering - Ileaving = 0
In fig there are four currents I1, I2,I3 & I4 metting at point O.considering all currents
entering point O as positive and all currents leaving the junction O as negative, we
have
I1+I2+I4- I3=0
I1+I2+I4=I3
Incoming currents=Outgoing currents
Based on this KCL can also be stated as
“The sum of the currents flowing towards any junction in an electric circuit is equal to
the sim of currents flowing out of the junction.”
Kirchhoff’s voltage law (KVL)

The algebraic sum of the voltages around any closed path in a network is equal to 0
Or
In any closed path the algebraic sum of the emf s is equal to the algebraic sum of the
product of the currents and the resistances in that loop
o emf+ IR=0
o V= IR
o voltage drops = voltage rise
Kirchhoff s voltage law is a restatement of the law of conservation of energy
Let I1,I2,I3,I4 be the branch currents

Applying KVL to the loop ABEFA we have
-I1R1-I3R3-I1R6+V1=0
I1R1+I3R3+I1R6=V1------------------EQ1
For the BCDEB we have

-I2R2-I2R4-V2-I4R5+I3R3=0
+I2R2+I2R4+I4R5-I3R3=-V2-------------EQ2
For apply KVL for the loop ABCDEFA

I1R1+I3R3+I1R6+I2R2+I2R4+I4R5-I3R3=V1-V2
I1R1 +I1R6+I2R2+I2R4+I4R5 =V1- V2--------------------EQ3
Algebraic signs for voltages

To solve specific problem using kirchhoff s law,algebraic signs of emf s and voltage
drops must be considered
Sign of emf’s
Raise in potential should be treated as +ve and fall in potential as –ve
As we move from –ve terminal of battery to the +ve terminal there is raise in potential
If we move from +ve terminal to the –ve terminal there is a fall in potential
Sign of voltage drops

The flow of current through the resistor result in the voltage drop across it
If we go through a resistor is a same direction of current flow then the voltage drop
should be taken –ve ,because the current flows from higher potential to lower
potential
If we go in the opposite direction of current flow then there is a raise in the potential
and should be taken as +ve
1. State ohm s law . (1M, OCT/NOV 2011)

2. Define node and loop of a network . (1M, OCT/NOV 2011)
3. Define branch and node of a network . (1M, OCT/NOV 2011)
4. State KCL and KVL
5. Derive Series parallel circuit
Chapter-2
Ac fundamental
The advantages of ac system over dc system are:

(i) Alternating voltages can be stepped up or stepped down efficiently by means of a

transformer.
(ii) Electric power is transmitted at high voltages and it is distributed at utilization voltages.
This provides economy.
(iii) AC motors are simpler and cheaper in construction than DC motors.
(iv) Switches and circuit breakers for ac system is simpler than dc systems.
Alternating voltage
An alternating voltage or current changes continuously in magnitude and alternates in
direction (polarity) at regular intervals of time.
An alternating current is a sinusoidal signal that has the form of sin/cos wave
An AC generator is a machine which converts the mechanical energy into electrical
energy in the form of alternating current by using the principle of electromagnetic
induction
Generation of AC voltage
A sinusoidal AC voltage can be generated by rotating a rectangular coil in uniform magnetic

lines of forces. This induces an alternating voltage in the coil one complete rotation of the
coil generates one set of +ve and –ve values
Important definitions
Cycle
It is one complete set of positive and negative values of an alternating quantity.
One cycle corresponds to 360 to 2p radians.
Frequency (f)
It is the number o f cycles of the alternating quantity in one second. It is represented
by f. It is measured in cycles per second or Hertz (1 cycle per second).
F=1/T
Time period (T)

The time taken by the AC or voltage to complete one cycle is called the time period
It is denoted by „T and basic unit is seconds
Frequency and time period are r eciprocals of each other
T=1/F
Instantaneous value
It is the value of an alternating quantity at any instant of time. Instantaneous value of
voltage is represented as „e or „v and instantaneous value of current is represented as
(i).
Expression for instantaneous voltage is given by
V=VmsinT or i=ImsinT
V=Vmsinwt ori=Imsinwt
Amplitude or peak value

It is also called the peak value. IT is the maximum value (positive or negative)
attained by an alternative quantity.
Amplitude is represented by Em(Vm) for alternating voltage and Im for alternating
current.
The peak value applies to either the +ve or –ve peak
Peak to peak value (Vp.p)

It is the sum of the +ve peak and the –ve peak values. It is double the peak value,
because the +ve and –ve peaks are symmetrical
Peak to peak value is equal to 2Vp
Root mean square value (RMS)/effective value

It is the value of the voltage/current at an angle of0 which
45 is 70.7%of the peak
value
i.e., rms value=0.707xpeakvalue
Vrms value=0.707Vp
Or Irms value=0.707 Ip
Average value
This is an arithmetic average of all instantaneous value of AC for one half cycles
The half cycle is used for the average value .because overall full cycle the average
value is 0
Therefore average value=0.637xpeak value
Consider a strip of width dT in the first half cycle of current wave as shown in the fig.
Let I be the mid-ordinate of the strip
Area of half cycle is equal to idT
Area of half cycle is equal to
idT= ImsinTdT
ImsinTdT
=Im[-cosT]
=Im[-cosp – (-cosT)]
=Im[-(-1)-(-1)]
=Im[2+2]
Area of half cycle is equal to =2Im
Therefore average value Iav is equal to
Iav=area of half cycle/base length of half cycle
Iav=2Im/p
Wave form/wave shape

It is the shape of the curve obtained by plotting the instantaneous value of voltage / current
along Y axis against time along X axis
Form factor
It is the ratio of rms value to the aver age value of an alternating quantity
Form factor= rms value
average value
For a sinusoidal voltage or current
Form factor=0.707xmaximum value
0.637x maximum value
Form factor=1.11
It is a useful quantity as given rms value, average value can be found and vice-versa
Peak factor
The peak factor is the ratio of maximum value to the rms value of an alternating
quantity
Peak factor= maximum value
rms value
For a sinusoidal voltage or current
Peak factor= maximum value
0.707x maximum value
Peak factor=1.414
Peak factor is an important quantity because it indicates the maximum voltage being
applied to the various parts.
Phase
Phase of a particular value of an alternating quantity is fractional part of time period
or cycle through which voltage or current has advanced from the selected zero
position of reference
Phase wave form

If 2 alternating quantities reach their maximum and 0 values at same time, then they
are said to be in phase with each other that means phase difference is 0
Phase different
If 2 alternating quantities don t reach their maximum and 0 values simultaneously,
then they are said to have phase difference
Two sinusoidal wave are shown in the fig curve B is displaced from curve A by an
angle that means phase difference between A and B is
Leading
A leading alternating quantity is one which reaches its maximum value earlier than the other
quantity
Lagging
Lagging alternating quantity is one which reaches its maximum value later than the other
quantity.

1. Define RMS value of AC voltage .(1M.NOV-DEC 2009)
2. Define peak value and time period of an AC. signal. (1M DEC 2010)
3. Define peak to peak value of an AC. signal (1M OCT-NOV 2012)
4. Define frequency and time period of an AC. signal. (1M OCT-NOV 2011)
Chapter-3
Atomic structure
Bohr’s atomic model
Atom consists of positively charged nucleolus around which negatively charged
electrons revolve in different circular orbits.
The electrons can revolve around the nucleuses only in certain permitted orbits
The electrons in each permitted orbit have a certain fixed amount of energy.
An electron that has absorbed energy and has jumped to a higher energy level is
called an excited electron .
The electron wants to have the lowest energy possible it quickly releases the added
energy (for example by emitting light) and goes back to its original state, also known
as its ground state.
Ex. silicon
Silicon atom has 14 electrons.

First orbit has 2 electrons and is called the k orbit.
Second orbit has 8 electrons and is called the L orbit.
The third orbit has remaining 4 electrons and is called the M orbit.
Energy levels
Electrons in larger radius orbits have greater energy
Each orbit has fixed amount of energy associated with it
The outer orbit electron possess more energy than the inner orbit electrons
The first orbit represented the first ener gy level, the second orbit represented the
second energy and so on
Unit of energy
Energy is measured in electron volts(eV)
Energy(W)=power(P) x time(t)
Power(P)=voltage(V)x current(I)
W=Pt------1
W=VIt-------2
But scurrent(I)=charge(Q)/time(t)
Or Q=It--------3
W=QV--------4
Energy level is 1eV if charge is of one electron and a potential difference is of 1V
We know that charge of 1 electron is 1.6x10- 19 coulombs
W=QV
=1.6x10- 19 C x 1V
1eV=1.6x10-19 joules
Energy bands
In isolated atom, each orbit has a single energy an electron existing in an orbit can
have only single energy corresponding to the orbit.
In solid the atoms are closely packed. In any orbit, no two electrons see exactly the
same charge environments. So the electrons of an orbit may have slightly differ ent
energies.
“Energy band can be defined as the range of energies possessed by an electron in a
solid.”
Energy bands in solids

There are 3 upper energy bands namely
Conduction band
Forbidden band
Valence band
Conduction band
It is the uppermost band.
The electrons in the conduction band are all free electrons
They can be easily r emoved by applying external voltage.
The conduction band is empty for insulators. It is partially filled for conductors.
Forbidden band
It is a collection of series of energy levels below the conduction band .there are no
electrons found in this band
Valence band
Valence electrons are the electrons in the outermost orbit of an atom
The outermost orbit is called the valence shell. The r ange of energies possessed by
valence electrons is called the valence band.
Classification of solids
They are
1. Conductor
2. Insulator
3. Semi-conductor
Conductor
A substance which has a large number of free electrons at room temperature is
called conductor of electricity
Ex. metals
Insulators
A substance which has a few numbers of free electrons at room temper ature is
called insulators
Ex. rubber, plastic, paper etc
Semiconductor
A substance which has crystalline structure and contains very few electrons at
room temperature, is called semiconductor
At room temperature semiconductors acts like a conductor
At low temperature semiconductors acts like a insulators
Ex. silicon, germanium
As temperature is increased, more valence electrons cross over to the conduction
band and the conductivity increases. So, electrical conductivity of semi conductor
increases with rise in temperature. so resistance reduces. So semiconductor also
has negative temperatur e co-efficient of resistance.
1. Draw the energy level diagram of a conductor and semi-conductor. (1M DEC 2010)
2. What are protons and neutrons of an atom? (1M OCT-NOV 2012)
3. What are valence and free electrons? (1M OCT-NOV 2011)

Chapter-4
Semiconductor
Introduction
There are certain substances that are in neither good conductors (metals) nor
insulators (glass).
A substance which has cr ystalline structure and contains very few free electrons at
room temperature is called semiconductor.
Silicon is the principal material widely used in the manufacture of electronic devices
like diodes, transistors and integrated cir cuits.
Definition of semiconductor
on the basis of physical characteristics
o A substance which hascrystalline structureand contains very few free
electrons at room temperature.
on the basis of electrical conductivity
o A substance which has resistivity in between conductors and insulators.
o Ex. Germanium, Silicon, Selenium, Carbon etc
on the basis of energy bands
o Semiconductors may be defined as substance which has almost filled valence
band and nearly empty conduction band with a small energy gap ( 1 ev)
separating the two.
Properties of semiconductors
A semiconductors has crystalline structure i.e. atoms or molecules of semiconductors
are arranged in an orderly manner
A semiconductor is formed by covalent bonds
The resistivity of a semiconductor is less than that of insulator but greater than that of
conductor
A semiconductor has negative temperature co-efficient of resistance
A semiconductor has almost filled valence band and nearly empty conduction band
with a small energy gap of 1eV
Suitable metallic impurity ( arsenic, gallium etc) can be added to a semiconductor to
have controlled conductivity which is an important property.
Crystal structure of semiconductors

In atoms electrons move around the nucleus (central part of an atom) in different
paths or orbits.
The maximum number of electrons in an orbit can be2 where 2n n is number of
orbit.
In most substances, the last orbit is incomplete. i.e. it does not have eight electrons
Each atom tries to complete its last orbit by acquiring eight electrons in it. To do so
the atom may lose, gain or share valence electrons with other atoms.
Sharing of valence electrons cause bonds to be formed in semiconductors. Such bonds

are called co-valent bonds .
Germanium is an example of semiconductor whose atomic number is +32. The

atomic structure of germanium is shown in fig
Fig Atomic structure of germanium

Germanium atom has four valence electrons so it is called tetravalent atom .
Each germanium atom has the tendency to have 8 electrons in the last orbit.
So each atom positions itself between four other germanium atoms fig shows the
covalent bonds in germanium atom.
Covalent bonds Bonding diagram

Fig Bonds in germanium atom
Effect of temperature on semiconductors
Temperature has an effect on the electrical conductivity of a semiconductor.

(i) Low temperature
At very low temperature, all electrons are tightly held by semiconductor atoms.
The inner orbit electrons are bound.
The valence electrons are bonded by covalent bonds. No free electrons are there. So
conduction is not possible and it does not allow current to flow.
A semiconductor in this state is an insulator.
(ii) Room temperature
At room temperature, some of the covalent bonds of the semiconductors are broken
due to thermal energy.
In the process, electrons engaged in the formation of these bonds are set free. These
free electrons constitute a tiny electric current if potential difference is applied across
the semiconductor crystal.
With rise in temperature the resistance of semiconductors decreases and conductivity
increases. So it is said to have negative temperature co-efficient of resistance.
Hole current
When a covalent bond is broken due to thermal energy, it sets the electrons of the
bond free. The bond from which an electron escapes is left with a deficiency known
as Hole. This hole becomes filled by an electron from a neighboring covalent bond
which, in turn leaves behind another hole, as shown in fig
Fig Hole and Electron

Thermal energy sets electrons free. For each electron set free, a hole is created. So
thermal ener gy creates hole-electrons pairs i.e. There are as many holes as the fr ee
electrons.
If potential differences is applied across the semiconductor, free electrons will move
towards the positive terminal while holes will move towards the negative terminals is
called hole current
Fig Hole current

The total current inside the semiconductor
Total current in conductor=current due to free electrons + hole current
Types of semiconductors
Semiconductors may be classified broadly as
1. Intrinsic semiconductors
2. Extrinsic semiconductors
Extrinsic semiconductors may again be classified as
1. n-type extrinsic semiconductors
2. p-type extrinsic semiconductors
Intrinsic semiconductors
Intrinsic semiconductors is a semiconductors in an extremely pur e form
Even at room temperature, there are hole-electron pairs created and number of holes
equal to number of free electrons.
Fig Movement of Electrons and Holes in Intrinsic Semiconductor
If a potential difference is applied across an intr insic semiconductors electrons will

move towards the positive terminal while holes will drift towards negative terminal.
The total current inside the semiconductors is the sum of the current due to free
electrons and holes.
If the temperature of the semiconductors increase the number of hole electron pairs
increase and current through the semiconductors increases.If temperature falls, the
reverse happens
Extrinsic semiconductors
Extrinsic semiconductors are the semiconductor whose conductivity can be increase
by the addition of a small amount of suitable metallic impurity to the intrinsic
semiconductors.
Doping
The process of adding impurity to a semiconductor is known as doping.
The elements suitable for doping are trivalent or pentavalent .
Trivalent element
Element that has three valence electrons is called trivalent element
Ex: Boron, Gallium, Indium
Pentavalent element
Element that has five valence electrons is called pentavalent element
Ex: antimony, arsenic, phosphorous
Depending upon the type of impurity added, extrinsic semiconductors are classified as
1. n-type semiconductors
2. p-types semiconductors.
n-type semiconductors
When a small amount of pentavalent impurity is added to a pure semiconductor, it is
known as n-type semiconductor.
The addition of pentavalent Impurity provides a large number of free electrons in the
semiconductor crystal.
Such impurities like arsenic (atomic number 33) and antimony (atomic number 51)
are called donor impurities because they provide free electrons to the semiconductor
crystal.
Fig Formation of n-type semiconductor
Four valence electrons of the impurity atom arsenic form co-valent bonds with four
Ge atoms.
The fifth valence electron of arsenic atom is free. So in the germanium crystal for
each arsenic atom added one free electron is available small amount of impurity still
provides enough atoms to supply millions of free electrons and hence it is called n-
type semiconductor. (Here „n stands for negative charge)
At room temperature some of the covalent bonds break, thus releasing a number of
free electrons and holes. In addition there are a number of free electrons due to
impurity added. So n-type material has large number of free electrons and a small
number of holes. The free electrons are called majority carriers and the holes are
called minority carries.
P-type semiconductor
When a small amount of trivalent impurity is added to a pure semiconductor, it is
called p-type semiconductor.
This addition of trivalent impurity provides a large number of holes in the p-type
semiconductor. Gallium (atomic number 31) and indium (atomic number 49) are
examples of trivalent impurities. They are called
acceptor impuritiesbecause the
holes created can accept the electrons.
Fig Formation of p-type semiconductor
Three valence electrons of the impurity atom (gallium) form covalent bonds with
three germanium atoms. In the fourth covalent bond, only germanium atoms.
In the fourth covalent bond only germanium atom contributes one valence electron
while gallium does not have any valence electron to contribute. So the fourth bond is
incomplete, being short of one electron this missing electron is a hole. So for each
gallium atoms added, one hole is created.
A small amount of gallium provides millions of holes. Since there are large numbers
of holes (positive charge) in the material, it is called p-type semiconductor.
In a p-type material, in addition to electron hole pairs due to trivalent impurity the
holes are more so here, holes are the majority carriers and free electrons are
minority carries.
Comparisons of n-type and p-type semiconductors
n-type semiconductors p-type semiconductors

1.pentavelent impurity is added to pure
semiconductor 1.trivalent impurity is added to pure semiconductor
2. There are large number of free electrons 2.there are a large number of holes
3.free electrons ar e majority and holes are3.holes ar e majority carriers and free electrons are
minority carriers minority carriers
4.it is electrically neutral 4. It is electrically neutral.
5.donor impurities used are arsenic and 5. Acceptor impurities used are gallium and
antimony indium.
Extrinsic conduction
Extrinsic conduction is the conduction of current in an extrinsic semiconductor either
the n-type or p-type.
There are two types of conductivity .they are
(i) n-type conductivity
(ii) p-type conductivity
(i) n-type conductivity

It is the current conduction in an n-type semiconductor. This is predominantly by free
electrons having negative charges.
The majority carriers are free electrons and they move towards the positive terminal.
The minority carriers are holes and they move towards the negative terminal. The hole
current is very small and negligible.
(ii) p-type conductivity

It is the current conduction in a p-type semiconductor. This is predominantly by holes
having positive charges.
The majority carries are holes that drift towards negative terminal and the minority
carries are electrons and they move towards the positive terminal. The current due to
free electrons is very small and negligible.
Answer the following questions
1. What are intrinsic semi conductors? (1M.NOV-DEC 2009)
2. What is doping? (1M DEC 2010) (1M OCT-NOV 2012)
3. Name any two trivalent impurities. (1M OCT-NOV 2012)
4. Explain the operation of intrinsic semiconductor. (4M OCT-NOV 2012)
5. Name any two pentavalent impurities. (1M OCT-NOV 2011)
6. What are extrinsic semiconductors? (1M OCT-NOV 2011)
7. Explain the operation of n-type semiconductor . (4M OCT-NOV 2011)
8.Explain hole current

Chapter-5
Semiconductor diodes
Introduction
This property is used in and application called rectifier.
Rectifier is a circuit used to convert alternating current to direct current .
Ideal diode
Ideal diode is a two terminal device having the symbol and characteristics as shown in
fig
One important parameter for the diode is the resistance at the point or region of
operation
Forward resistance
Forward resistance can be defined using ohm s law as
Rf = Vf /If
Where Vf is the forward voltage across the diode
I f
is the forward current through the diode.
Vf is zero for an ideal diode
If may be any positive value
Rf = Vf /If =0
The ideal diode, therefore is a short circuit in the region of conductor
„
Reverse resistance
Reverse resistance can be defined using ohm s law
Rr = Vr /Ir
where Vr is the reverse voltage across the diode
Ir is the reverse current through the diode.
Vr is any reverse potential
Ir is zero
so Rr very large number infinity
The ideal diode, therefore is an open circuit in the region of non conduction (i d =0)
P-N Junction
When a p-type semiconductor is suitable joined to n-type semiconductor the contact
surface is called p-n junction .
p-n junction is the basic control element for semiconductor devices.
At the p-n junction there is a tendency for the free electrons from the n-type to diffuse
over to the p-side and holes from the n-side.
Initially both p and n materials are electrically neutral .

After the diffusion process, a positive char ge is build up on n-side of the junction
and negative charge on the p-side of the junction.
This situation prevents further diffusion. Positive charge on n-side repels holes from
crossing over from p-type to n-type. Likewise, negative charge on p-side repels free
electrons to enter from n-type to p-type. This setup a barrier against further movement
of holes and free electrons. This is called potential barrier or junction barrier.
This is of the order of 0.1 to 0.3V. This potential barrier gives rise to an electric field .
Majority carriers (holes in p-type and electrons in n-type) are prevented from crossing
the barrier.
The region near the p-n junction that lacks carriers is called the depletion region . It is
the region of uncovered positive and negative ions.
Biasing of p-n junction or voltage-ampere characteristic of p-n junction
The performance of a diode can be studied with the help of diode characteristics;
This can be studied with three conditions. They are
(i) Zero bias (no applied bias)
(ii) Forward bias
(iii) Reverse
(i) Zero bias (no applied bias)

The minority carriers in the n-type material (holes) that are within the depletion
region (close to the junction) will pass directly into the p-type material due to greater
attraction for the layer of negative ions in the depletion region near p-type material.
Similar is the case with minority carriers in the p-type material (electrons).
The majority carriers in the n-type material must overcome the attractive forces of
layer of positive ions in the n-type material and negative ions in the p-type material in
order to move into the neutral region o f p-type material.
A small number of majority carriers gain enough ener gy to pass through the depletion
region into the p-type material. Similar is the case with majority carriers in the p-type
material.
So the net flow of charge in either direction is zero when there is no bias (no voltage
applied across the junction.)
(ii) Forward bias

A forward bias condition is established by applying the positive terminal to the p-type
material and negative terminal to the n-type material.
The positive and negative char ges set up an electric field, this is a barrier to free
electrons in n-region. There is potential difference across the depletion layer and is
called barrier potential (Vo)
The external dc voltage applied is in such a direction that it cancels the potential
barrier. This permits current flow. The width of depletion the region is reduced .
There is a heavy flow of majority carriers across the junction.
Initially a small potential barrier exists at the p-n junction. When forward potential is
applied as shown in fig and electric field is created such that is completely eliminates
the potential barrier. Then the junction resistance becomes zero. So this allows current
to flow in the circuit. This is called forward current (I f ).
Initially, current increases very slowly and the curve is non-linear. This is the portion
OA of the curve. This is because the external voltage is utilized in overcoming the
potential barrier. Once the external voltage exceeds the potential barrier voltage, the
p-n junction starts conduction and current rises very sharply with increase in external
voltage, this is the portion AB of the curve, now the curve is almost linear.
(iii) Reverse bias

A reverse bias condition is established by applying the positive terminal to n-type

material and negative terminal to p-type material.
The external dc voltage applied is in such a direction that potential barrier is

increased. Reverse voltage establishes an electric field which acts in the same
direction as the field due to potential barrier. This prevents the flow of charge carriers
across the junction.
The number of uncovered positive ions in the depletion region of the n-type material
will increase due to the large number of free electrons drawn to the positive potential
of the applied voltage.
For similar reasons, the number of uncovered negative ions will increase in the p-type
material. So the depletion region is widened. Effectively, majority car rier flow is
reduced to zero. But however, the number of minority carriers entering the depletion
region will not change. So a small current of the order of micro-amperes flows in the
circuit. This is called the reverse saturation current.
The term Saturation is used because it reaches its maximum value quickly and does
not change significantly with increase in reverse bias potential. This current is very
small until breakdown voltage Vz is reached.
The applied reverse voltage Vz called zener voltage is sufficient to break down to
existing co-valent bonds, creating a large number of minority carriers. As a result,
there is a sudden increase in the reverse curr ent and a sudden fall in resistance of the
barrier (depletion) region. With a large flow of reverse current large amount of heat is
dissipated. This may damage the junction permanently.
Knee voltage
It is the forward voltage at which the current through the junction starts to
increase rapidly.When a diode is forward biased, it conducts current very slowly
until the potential barrier is over come it is 0.7v for silicon and 0.3v for germanium.
This is the knee voltage. Once the applied forward voltage exceeds the knee voltage,
current starts increasing rapidly.
The potential barrier voltage is also known as Turn-on voltage.
Break down voltage

The maximum reverse bias voltage that can be applied to a p-n diode is limited by
breakdown. Breakdown is characterized by the rapid increase of the current under reverse
bias. The corresponding applied voltage is ref erred to as the breakdown voltage.
or
It is the minimum reverse voltage at which p-n junction breaks down with sudden rise
in reverse current. This is called break down voltage
Avalanche breakdown and zener breakdown

A process that occurs in a diode when high voltage causes free electrons to travel at
high speeds, colliding with other electrons and knocking them out of their orbits. The result is
a rapidly increasing amount of free electrons.
or
At higher reverse voltage, the junction may break down with sudden rise in reverse
current. Even at room temperature, hole-electron pairs are produced in the depletion
layer.
At large reverse voltage, these electrons acquire high enough velocities to dislodge
valence electrons from semiconductor atoms. The newly liber ated electrons free other
valence electrons and an avalanche of electrons is created. This is called avalanche
breakdown
Resistance of crystal diode

Resistance of diode can be
1. Forward resistance
2. Reverse resistance
Resistance can either be
1. Dc or static resistance
2. Ac or dynamic resistance
Dc or static resistance
It is the ratio of direct voltage across the diode to the resulting direct current
OA is the forward voltage and OB is the forward current at an operating point P

Dc forward resistance R f =OA/OB
Ac or dynamic resistance
It is the ratio of change in forward voltage across the diode to the resulting change in
forward current.
Ac forward resistance= V F / I F
If P is the operating point, then

Ac forward resistance = V F / I F
=oc-oa/of-od
R f
=ac/df
It is very small and it range between 1 and 25w
Peak inverse voltage (PIV)

The maximum reverse voltage that a diode can withstand without destroyingthe
junction is called peak inverse voltage of the diode
Application of diode
Important applications of a diode are
1. As a switch
2. As a rectifier
3. As a logic gate
1. Diode as a switch
A diode conduct current easily when forward biased and practically no current flows
when it is reverse biased. This behaves like a switch which is „on during forward bias and
„off during reverse bias. So it behaves like a closed switch in for ward bias and an open
switch in reverse bias
2. Diode as a rectifier
Rectification means by changing alternating current to direct current. a circuit that
perform rectification is called a rectifier
During the positive half cycle of ac input voltage, the diode is forward biased and
conducts current in the circuit.
During the negative half cycle of input ac voltage, the diode is reverse biased so it
does not conduct current. So outputs consist of only positive half cycle of input ac
voltage. So the diode can be used as a rectifier.
3. Diode as a logic gate

The diode switch characteristics can be used in a logic gate
Answer the following questions
1. What is p-n junction diode? With schematic diagram explain the formation of p-n junction.
(3M.NOV-DEC 2009)
2. Explain the terms. (4M.NOV-DEC 2009)
a. Knee voltage
b. PIV and
c. static and dynamic resistance related to diode.
3. Explain the action of diode under un-biased condition. (3M DEC 2010)
4. Explain the action of diode under forward and r everse biased condition. (3M DEC 2010)
5. Explain the action of diode under forward biased condition (3M OCT-NOV 2011)

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Digital Electronics Number Systems Guide

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DIGITAL ELECTRONICS

Number a quantity or value expressed by a word or a symbol is called Number

a. Positional number system

b. Non positional number system

Eg: Roman number system.

Positional number system

1. Decimal number system

Decimal number system

It is also called as Hindu Arabic numerals

Binary number system

Bit is an abbreviation for a binary digi t

…..24 2 3 2 2 2 1 2 0 . 2 -1 2 -2 2-3 ……….

Terms used in binary number syst em

Octal number system

The symbols used in this system are 0,1,2,3,4,5,6,7

Hexa decimal number system

The symbols used in this system are 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

1. Binary number system

Decimal to binary conversion

2. Octal number system

Decimal to octal conversion

Octal to decimal conversion

3. Hexa decimal number system

Decimal to Hexa decimal conversion

Octal to Hexa decimal

1. Binary number system

Decimal to binary conversion

Eg: Convert 28.3125 (10) ---- (?)2

Binary to decimal conversion

1. Determine the positional value of each digit

64 32 16 8 4 2 1 0.5 0.25 0.125 0.0625

=1x23 +1x22 +1x21 +1x20 +0x2-1 +1x2-2 +1x2-3

Octal number system

Decimal to octal conversion

Eg: Convert 549.1325 (10) ----- (?)(8)

Octal to decimal conversion

1. Determine the positional value of each digit

4096 512 64 8 1 0.125 0.0156 0.00195

Eg: Convert 763.375 (8) ---------- (?)(10)

7x82 +6x81 +3x80 +3x8-1 +7x8-2 +5x8-3

Octal to binary conversion

1. Convert each digit of the octal number to a 3 digit binar y number

Eg: 4632.51(8) -------- (?)2

Binary to octal conversion

Eg:01111.1101011 (2) ->(?)8

5. 01111.1101011(2) = 17.654 (8)

Hexa decimal number system

Decimal to Hexa decimal conversion

Eg:Convert 512.625 (10) ----- (?)16

Hexa decimal to decimal conversion

1. Determine the positional value of each digit

164 163 162 161 160 16-1 16-2 16-3

Eg: 36F.ABC(16) ------ (?)10

Hexa decimal to binary conversion

Decimal Hex binary

Eg: 10A4.FACE(16) ------ (?)2

Binary to Hexa decimal conversion

Eg: 11100.01(2) =(?)16

Octal to Hexa decimal

1. convert each digit of the Octal number to a 3 digit binary number

Hexa decimal to Octal

Complements of binary numbers

The 1 s complement of a binary number is obtained by changing each 0 to 1 and 1 to