A Low Noise Amplifier Simultaneously Achieving

Input Impedance and Minimum Noise Matching

Bum-Kyum Kim, Donggu Im, Jaeyoung Choi, Kwyro Lee

Department of EE, Korea Advanced Institute of Science and Technology, Korea

Abstract — A CMOS complementary capacitive loaded

LNA with inductively source degeneration is implemented for Load
900MHz application using a 0.18-m CMOS process. In order
to achieve simultaneous input impedance and minimum noise OUT
matching, the capacitive loading technique is proposed. Owing
to the capacitive loading technique, the noise figure (NF) of DC block
the proposed LNA can be perfectly close to NFmin while M2
maintaining the source impedance matching by reducing the DC block
source degeneration inductor and gate inductor contrast to M1
conventional cascode LNA with inductively source IN Lg
degeneration. The measurements demonstrate that the LNA
has a power gain of 12 dB, a NF of 1 dB, an IIP3 of +7.7 dBm, Cgs1
and an input P1-dB of -5 dBm at 900 MHz while drawing 9 Ls
mA from a 1.8 V supply voltage.
Index Terms — noise matching, input impedance matching,
simultaneous matching, low noise amplifier, capacitive load, Fig. 1. Conventional cascode LNA with the inductive source
complementary degeneration.

I. INTRODUCTION simultaneously achieving input impedance and minimum

noise matching seems to be a straightforward and a cost-
CMOS has become promising technology for radio
effective solution for future RF transceivers.
transceiver implementation for various wireless
In this paper, the LNA simultaneously achieving input
communication systems due to the technology scaling,
impedance and minimum noise matching is proposed. In
higher level of integration capability, and lower cost.
Section II, the conventional LNA topologies for
Nevertheless, the external off-chip components such as low
simultaneous input and noise matching are reviewed and
noise amplifier (LNA) and power amplifier (PA) using
their limitations are discussed. Section III describes newly
compound semiconductor technologies are still used in a
proposed design technique simultaneously achieving input
commercial market because of high performances.
impedance and minimum noise matching. The complete
In a typical radio receiver, the low noise amplifier (LNA)
LNA is presented and its RF characteristics including the
is one of the key components, as it tends to dominate the
gain, NF, and input impedance matching are discussed in
sensitivity of the receiver. In order to replace the external
detail. The measurement results are given in Section IV and
off-chip LNAs with CMOS LNAs, the noise figure (NF)
conclusions are discussed in Section V.
less than 1 dB is required with lower power consumption.
Also, in order to overcome distortion problem such as
desensitization, gain compression, inter-modulation, and II. CONVENTIONAL LNA TOPOLOGIES FOR SIMULTANEOUS
cross-modulation, the LNA should have high linearity. INPUT IMPEDANCE AND NOISE MATCHING
Generally, the LNA design involves many tradeoffs
Figure 1 shows the conventional cascode LNA with the
between NF, gain, linearity, impedance matching, and
inductive source degeneration. The quality factor Qin of the
power dissipation. Among these tradeoffs, to achieve
series resonating input matching circuit is defined as a ratio
simultaneous input matching and minimum noise at any
of imaginary impedance to real impedance. When the input
given amount of power dissipation is most important factor
impedance is well matched to the source impedance, Qin
in terms of high sensitivity. In combination with the
and NF of the cascode LNA with the inductive source
linearization methods such as multiple gated transistor
degeneration are given as
(MGTR) technique and complementary CMOS parallel
push-pull (CCPP) technique in [1] and [2], the LNA

978-1-4244-8292-4/11/$26.00 ©2011 IEEE

 0 ( Ls  Lg ) 1 (1)
Qin  
Rs 0Cgs1Rs Load

     1    OUT
F 1   0    1   2c  Qin 
 T   Qin 5 5 Zx
  5  DC block
Cgd1 CL
R vd
R (2) M2
 Lg  2Ls DC block
Rs Qin Rs vg
M1
IN
Lg
1
where Rs is a source impedance, c is a correlation gm2
Cgs1
coefficient between induced gate noise and drain noise, Zy Ls
Zin Zg
 is a induced gate noise coefficient,  is a drain noise
coefficient, ωo is a resonant frequency, and RLg and RLs
denote parasitic series resistance of Lg and Ls respectively. Fig. 2. Capacitive loaded LNA with the inductive source
From (2), the optimum value of Qin minimizing the NF of degeneration.
the LNA can be found because the gate noise and channel Lg Zx Zy
noise of the input transistor have the opposite dependence IN
on Qin. Namely, as the Qin of the input matching circuit is CL 1 gm1
increased from zero, the NF will tend to improve in Cgd1 (1+ ) Cgs1
Cgd1 gm1 gm2
accordance with the expression of (2) but the impedance at
the gate of the input transistor increases simultaneously, Zin Zg
and hence the gate current noise including the thermal Fig. 3. Small signal equivalent circuit of capacitive loaded
noise by RLg will begin to dominate at some point [3][4]. LNA with the inductive source degeneration at the input.
As shown in Fig. 1, in order to control the Qin of the
increasing the value of Ls and for reducing the Lg for the
input matching circuit, the capacitor Cgs1 is connected
smaller RLg.
between gate and source of input transistor. The Cgs1 is a
sum of intrinsic gate-to-source capacitance(Cgs1.intrinsic) and
III. PROPOSED LNA FOR SIMULTANEOUS INPUT
extra added capacitance(Cgs1.ext). Considering the cascode
IMPEDANCE AND NOISE MATCHING
LNA with the inductive source degeneration generally has
a higher Qin than optimum value of Qin for minimum NF, it A. The effect of capacitive loading
is desirable to lower the Qin of the input matching circuit by
Figure 2 shows the capacitive loaded LNA with the
the Cgs1.ext. Hence the NF of the LNA can be close to NFmin,
inductive source degeneration. This capacitive loading
which is defined by the characteristic of the device and DC
method is commonly used for achieving wide-band input
bias condition of input transistor and quality factor of
matching[5]. But in this paper, it is focused on minimizing
inductor Lg and Ls. On the other hand, for input impedance
NF by sizing Cgs1, Cgd1, and CL properly. The Cgs1 is a sum
matching, we should satisfy the following condition
of Cgs1.intrinsic and Cgs1.ext. The Cgd1 is also a sum of
g m1Ls 1 Cgd1.intrinsic and Cgd1.ext. The CL is not DC block capacitor.
Z in  RLg   j0 ( Ls  Lg ) 
Cgs1 j0Cgs1 (3)
Note that the CL is a load capacitor. It is reasonable that
the LNA of Fig. 2 is equivalent to that of Fig. 1 if the load
g L
 RLg  m1 s capacitor CL is very large.
Cgs1 . In order to estimate the effect of the load capacitor CL on
From (3), we know that the larger Cgs1 decreases the real the input impedance of the LNA, it is assumed that Ls is
part of the input impedance. It is for the price of achieving zero and 1/gm2 is enough small. The impedance Zg seen in
minimum NF. In order to achieve both input impedance the gate of input transistor is calculated as a parallel
and minimum noise matching, the Ls should be increased. impedance of Zx and Zy. The Zx is the equivalent
However, this approach degrades the NFmin of the LNA due impedance seen through gate-to-drain capacitance Cgd1 by
to poor quality factor of the source inductor (Ls) in the miller effect and the Zy is the equivalent impedance seen
bulk-CMOS process. Moreover, considering fully through Cgs1. Using the Kirchoff’s current law / Kirchoff’s
integrated LNA using on-chip Lg and Ls, it is important to voltage law (KCL/KVL), the voltage gain from gate to
decrease the value of Lg because the dominant noise drain of the input transistor, Zx, and Zy are derived as
contribution of the LNA with inductive source vd g m1
Av   (4)
degeneration comes from transistor M1 and RLg of Lg. sCL g m 2
vg (Cgs1Ls s 2  g m1Ls s  1)
Therefore, we propose a new design technique for
generating real part of the input impedance without sCL  g m 2
 1 1
Zx  900MHz 50j
CL=50pF
sCgd 1 1  Av [resonant CL=5pF
(5) frequency] CL=1pF
CL g m 2

Cgd 1 ( sCL g m 2  g m1 ( sCL  g m 2 ))
1 3GHz
 g  CL 1
  j0Cgd 1 (1  m1 ) 
 g m2  Cgd 1 g m1 50
100MHz
Larger real part
1 (6)
impedance of Zin
Zy 
j0Cgs1 .

From (5) and (6), the impedance Zg and real part of the
input impedance Zin are expressed as -50j

Fig. 4. Simulated S11 traces of the capacitive loaded LNA

C 1 1 (7) according to the variation of CL. (Ls = 1nH, gm = 50 mS,
Zg  Zx Z y  L
Cgd 1 g m1 j0  Cgs1  Cgd 1 (1  g m1 / g m 2 )  Continuously swept with the frequency range from 100MHz to
3GHz)
real ( Z in )  real ( j0 Lg  Z g )
(8) Ls.p
Cgd 1 g m1 Cgs1.p


CL  Cgs1  Cgd 1 (1  g m1 / g m 2 )  0 .
2

RBias
Note that the (4)-(8) are valid only for the resonance DC block
frequency( 0 ) range of the input matching network shown IN OUT
Cgd1 CL
in Fig. 3. The (8) indicates that the real term for source Lg
impedance matching can be made without the source 50 Ω
RLoad Ω
degeneration inductor. This means that the capacitive Cgs1.n
loading technique is very useful for increasing the real part Ls.n
of the input impedance without increasing the value of Ls in
the cascode LNA with inductive source degeneration in Fig.
1. As shown in Fig. 4, as the CL decreases from 50 pF to 1 Fig. 5. Complementary capacitive loaded LNA with
pF with constant Ls, the real part of the input impedance is inductively source degeneration.
larger. This result agrees with the results of (8). In the case The two equations, (10) and (11), are under such condition
of the NF of the capacitive loaded LNA, it is derived as that simultaneous minimum NF and input impedance
R 1  g m1 matching. But in case of the conventional LNA of Fig. 1,
F  1  Lg  RLg is derived as
Rs (0Cgd 1 ) 2  g m12 Rs 1
R
(9) RLg . NF min  s  2QLg  4
 
(12)
  Cgs1Rs0    1  0 2 LsCgd 1  
2 2
QLg .
   Cgd 1  The last term in (10), (1+gm1/gm2)-1, is not seen in (12). The
where   1  2 c ,  2c
5 5 5 Cgs1 5 . RLg on the minimum NF condition in the proposed
capacitive loaded LNA is reduced by (1+gm1/gm2) times
From (9), CL doesn’t affect the NF of the LNA. Namely, the than that of the conventional LNA of Fig. 1. This is owing
NFmin and NF of the LNA is not function of CL. The other to the capacitive loading effect by extra added capacitor
advantage is that Lg in Fig. 2 is more reduced compared to Cgd1.ext. From (11), sum of Cgs1 and Cgd1(1+gm1/gm2) keeps
Lg in Fig. 1 on the input impedance matching condition. It constant for the minimum NF.
means that RLg of Lg in Fig. 2 can be reduced. The RLg, Cgs1, In conclusion, from (8)-(11), the NF can be perfectly
and Cgd1 of capacitive loaded LNA are derived as close to NFmin while maintaining the source impedance
matching contrast to the conventional cascode LNA of Fig.
Rs 1
 1 
RLg . NF min   2QLg  4   (10) 1.
QLg  1  g m1 / g m 2  B. Complementary capacitive loaded LNA with
1
inductively source degeneration
 g m1  1  1  4
 g m1 
Cgs1  Cgd 1 (1  )    1  
 g m 2  NF min 0 Rs  2QLg   g m2 
. Figure 5 shows complete complementary capacitive
loaded LNA with inductively source degeneration. The
(11)
 sim.
15 NF 10
12dB S21
10 S11
S21 8
5
NF

S11, S21 [dB]

6

NF [dB]
0
S11
-5
4

-10
2
Fig. 6. Chip photograph of the complete LNA. -15 1dB
-18dB
fundamental operation of the complete LNA is identical to -20 0
0.5 1.0 1.5
that of Fig. 2. The complementary version saves the current 900MHz
Frequency (GHz)
consumption for achieving large transconductance as a
result of reusing current. In addition, since the second- Fig. 7. Simulated and measured power gain (S21), S11, and NF
order distortion currents (IM2 currents) generated by of the complete LNA: simulation(dash), measurement(line).
PMOS and NMOS are out of phase, there is no IM2 current Table I: Calculation Simulation Measurement
flowing to the output. Hence the “even harmonic mixing”
Technology 0.18 um CMOS
is alleviated and the overall linearity is improved. The
analytical expressions for the power gain and NF of the DC power 16.2 mW (1.8 V, 9 mA)
complete LNA are derived as Frequency 900 MHz
S21 15 dB 13.5 dB 12 dB
R  sLg  g m. p g m. n 
Gain  s    RLoad (13) NF 0.4 dB 0.75 dB 1 dB
Rs  1  sLs. p g m. p 1  sLs.n g m.n  IIP3  +8.1 dBm +7.7 dBm
Input P1dB  -4.5 dBm -5.1 dBm
2Cgs1 g m Ls Rs s 2  sLg  Rs 
2
sLg  3Rs
 V. CONCLUSION
RLg2 g m s  3g m Ls Rs  Lg  s  3g m Ls Rs  Lg  1  sLs g m 
F 1  2 The new approach for simultaneously achieving input
Rs Rs Rs  sLg  g m 
  impedance and minimum noise matching is proposed. The
Rs  1  sLs g m  proposed complementary capacitive loaded LNA with
(14) inductively source degeneration shows comparable
where gm is the sum of gm.p and gm.n. At the resonant performances compared to commercial external LNA.
frequency of 900 MHz, Ls with 1.2 nH and Lg with 10 nH
ACKNOWLEDGEMENT
are chosen for lower noise. The gm.p and gm.n are about 50
mS and the Cgs1.p + Cgs1.n is set equal to 1 pF, and Cgd1 is set This work was supported by the National Research
equal to 100 fF. Foundation of Korea (NRF) grant funded by the Korea
government (MEST). This work was also supported by the
IV. MEASUREMENT RESULT IC Design Education Center (IDEC).
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