A B C D E

ZZZ

PCB
Part Number = DAZ0FQ00100

ZZZ
1 1

64M512@

X76244BOL01
Part Number = X76244BOL01

ZZZ

64M1G@

X76244BOL03
Part Number = X76244BOL03

ZZZ

128M1G@
Compal Confidential
X76244BOL05
Part Number = X76244BOL05

ZZZ

128M2G@
2 2

PEW76 Schematics Document

X76244BOL06
Part Number = X76244BOL06

AMD Danube
Champlain Processor with RS880M/SB820/Madison VGA

3
2010-06-07 3

LA5911P REV: 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 1 of 55
A B C D E
 A B C D E

Danube
Compal Confidential VRAM 1GB
64M16 x 8 AMD S1G4 Processor
Model Name : NEW75/85/95 Memory BUS(DDR3) 204pin DDRIII-SO-DIMM X2
page 19, 20 uPGA-638 Package Dual Channel BANK 0, 1, 2, 3 page 8,9
DDR3 Champlain page 4,5,6,7 1.5V DDRIII 800~1333MHz
1
ATI M97 1

Madisan/Park Hyper Transport Link

uFCBGA-962 PCI-Express x 16 16 x 16
Page 14,15,16,17,18,21,22

Gen2 Thermal Sensor Clock Generator

ATI RS880M
ADM1032 ICS9LPRS488
page 6 page 23
LVDS uFCBGA-528
page 24

page 10,11,12,13 page 36,37 page 27 page 37 page 36 page 36 page 36

CRT
page 26
A link Express2 USB CMOS Bluetooth Mini 3G/GPS Card
Gen1 conn Camera Conn card WWAN Reader
HDMI Conn. X3 <Option>
(WL)X1 <Option>
page 25 USB port 0,1,2 USB port 5 USB port 12 USB port 8 USB port 9 USB port 6
2
ATI SB820M 3.3V 48MHz USB
2

3.3V 24.576MHz/48Mhz HD Audio

LAN(GbE) uFCBGA-605
MINI Card 1 Broadcom
WLAN BCM57780 page 27,28,29,30,31 S-ATA Gen2
page 36 page 34
GPP1 GPP0 HDA Codec
ALC272X
page 42
RJ45
page 35 LPC BUS SATA HDD CDROM
Conn. page 32 Conn.
page 32
port 0 port 1 Audio AMP
page 43
LED ENE KB926
3
page 40 Fan Control page 38 3
page 44
Phone Jack x2
page 43
RTC CKT.
page 26
Touch Pad Int.KBD
Extend Card/B page 39 page 39

LID SW / MEDIA/B 1. USB X2 EC I/O Buffer BIOS

page 39 2. Cardreader page 38 page 39
JM385
Power On/Off CKT.
page 41

DC/DC Interface CKT.

4 4
page 45

Power Circuit
page 46,47,48,49,50,51
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
52,53,54
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 2 of 55
A B C D E
 5 4 3 2 1

AMD
VGA
D ATI D

Madison/Park

VGA_CLKP/N
100MHz

MEM_MA_CLK1_P/N
MEM_MA_CLK7_P/N CLK_SBSRC_BCLK/#

C
A_SODIMM
1066MHz
AMD AMD 100MHz AMD C

SB NB_DISP_CLKP/N NB
MEM_MB_CLK1_P/N S1G4 CPU_HT_CLKP/N
MEM_MB_CLK7_P/N
CPU SOCKET 200MHz
SB820M 100MHz RS880M
B_SODIMM
1066MHz Internal CLK GEN
NB_HT_CLKP/N
100MHz

32.768KHz 25MHz

GPP_CLK3P
100MHz
GPP_CLK1P/N
B B
100MHz

GbE LAN
WLAN
Broadcom
Mini PCI Socket
B57780

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/10 Deciphered Date 2010/03/12 Title
SCHEMATIC, MB A5911
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401827 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, September 14, 2010 Sheet 3 of 55
5 4 3 2 1
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE_0 Core voltage for CPU (0.7-1.2V) ON OFF OFF
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V) ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+CPU_CORE_NB Voltage for On-die Northbridge of CPU(0.8-1.1V)ON OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF Board ID / SKU ID Table for AD channel
+1.1VS 1.1V switched power rail for NB VDDC & VGA ON OFF OFF Vcc 3.3V +/- 5%
+1.2V_HT 1.2V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.5VS 1.5V power rail for PCIE Card ON OFF OFF 0 0 0 V 0 V 0 V
+1.8V 1.8V power rail for CPU VDDIO and DDR ON ON OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+1.8VS 1.8V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+2.5VS 2.5V for CPU_VDDA ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VALW 3.3V always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3V_LAN 3.3V power rail for LAN ON ON ON 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+3VS 3.3V switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VALW 5V always on power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+5VS 5V switched power rail ON OFF OFF
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON BTO Option Table
BOARD ID Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BTO Item BOM Structure
Board ID PCB Revision
External PCI Devices 0
Device IDSEL# REQ#/GNT# Interrupts 1 No USB Patch
2 Capilano w/ USB patch
3
4
5
6
7 Add USB patch

--For SSID define

EC SM Bus1 address EC SM Bus2 address Project ID Table --For TSI thermal math
3 3

Device Address HEX Device Address HEX

Board ID PCB Revision
0 NEW75/85/95
Smart Battery 0001 011X b 16H ADI ADM1032 (CPU) 1001 100X b 98H
1 PEW76/86/96
GMT G781-1 (GPU) 1001 101X b 9AH
2 PEW56
SB-Temp Sensor 98H
3
4
SB820 SB820 5
6
SM Bus 0 address SM Bus 1 address 7
Device Address HEX Device Address PowerXpress SKU(Madison): 3G@/BT@/UMA@/ VGA@/SG@/EXT@/EXTPW@/VB@/MAD@
Clock Generator 1101 001Xb D2
PowerXpress SKU(Park): 3G@/BT@/UMA@/ VGA@/SG@/EXT@/EXTPW@/VB@/PARK@
(SILEGO SLG8SP626)
EXT CLKGEN
DIS ONLY:(Park) 3G@/BT@/DISO@/ VGA@/EXT@/EXTPW@/PARK@
DDR DIMM1 1001 000Xb 90 UMA only SKU: 3G@/BT@/UMA@/ UMAO@/EXT@/VB@
DDR DIMM2 1001 010Xb 94 BOM Config
Mini card
PowerXpress SKU(Madison):3G@/BT@/UMA@/VGA@/SG@/INT@/VB@/MAD@
4 INT CLKGEN PowerXpress SKU(Park): 3G@/BT@/UMA@/VGA@/SG@/INT@/VB@/PARK@ 4

DIS ONLY(PARK): 3G@/BT@/DISO@/VGA@/INT@/PARK@

UMA only SKU: 3G@/BT@/UMA@/UMAO@/INT@/VB@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 4 of 55
A B C D E
 5 4 3 2 1

AMD CPU S1G4

+CPU_CORE
BATTERY BATT+ PU5 PU15 +CPU_CORE 0.7~1.3V VDD CORE 36A
12.6V CHARGER ISL6265IRZ-T +CPU_CORE_NB
+CPU_CORE_NB 0.8~1.2V VDDNB 4A
ISL6261AHAZ-T
2.5V VDDA 250mA
PU16
APL5508-25DC +2.5VS 1.5V VDDIO 3A
+1.05VS
PU12 +1.05VS 1.05V VDDR 1.5A
AC ADAPTOR VIN APL5915 +1.1VS 1.1V VLDT 1.5A
19V 90W

D D

RAM DDRIII SODIMMX2

PU7 +1.5V
B+ RT8209BGQW 1.5V VDD_MEM 4A
+0.75VS
+1.5V 0.75V VTT_MEM 0.5A PU10
APL5913

NorthBridge AMD RS880M

1.0~1.1V VDDC 1.0V-1.1V 7.6A

PU8 +NB_CORE
RT8209BGQW +1.1VS VDDHTRX+HT 0.68A
1.1V_S0 VDDPCIE 1.1A
VDDHTTX 0.68A
PLLs 0.23A

VDDA18 0.64A
1.8V_S0 VDDG18 0.005A
VDDLT18 0.22A
PLLs 0.1A

VDDG33 0.06A
PU6 +1.1VALW +1.1VALW 3.3V_S0 AVDD 0.125A
RT8209BGQW U36 VDDLT33 0A
SI4800BDY
No Use VDD18_MEM 1.8V 0.005A
+1.1VS VDD_MEM 1.8V 0.23A
C +1.5V +1.5VS C
PU19 U35
TSP51117RGYR SI4800BDY

VGA ATI Madison / Park

PU17 +GPU_CORE +VDDCI
APW7138NITRL 0.85~1.1V VDDC 29 A
VDDCI 4 A

+1VSG PCIE_VDDC 2 A
PU10 1.0V DP[F:A]_VDD10 230 mA VRAM 1GB
+1.8VS APL5913 DPLL_VDDC 125 mA
SPV10 100 mA 64Mx16 (K4B1G1646E) * 8
PU14 PU11
APL5913 MP2121DQ +1.5VS
1.5V VDDR1 TBD A 1.5V 2.4 A

PCIE_PVDD 40 mA
+1.8VSP2 +1.8VSP1 PCIE_VDDR 400 mA
TSVDD 5 mA
+3VALW VDDR4 TBD mA
VDD_CT 17 mA
DP[F:A]_PVDD 20 mA
+INVPWR_B+ PU4 1.8V DP[F:A]_VDD18 330 mA
SN0806081 RHBR AVDD 70 mA
VDD1DI 45 mA
+5VALW U37 +3VS A2VDDQ 1.5 mA
SI1800BDY VDD2DI 50 mA
DPLL_PVDD 75 mA
MPV18 150 mA
SPV18 50 mA
B LCD panel B
Delay +3VS_DELAY 3.3V VDDR3 60 mA
15.6" A2VDD 130 mA
U34
SI4800BDY +5VS
B+ 300mA
+3.3 350mA SouthBridge AMD SB820M

VDDCR_11 1.1V 0.5A

VDDAN_11_PCIE 1A
1.1V_S0 VDDAN_11_SATA 0.8A
VDDAN_11_CLK 0.4A

FAN Control +1.1VALW VDDCR_11_S 113mA

VDDAN_11_USB_S 200mA
APL5607 1.1V_S5 VDDCR_11_USB_S 197mA
VDDPL_11_SYS_S
+5VS 500mA
VDDIO_33_PCIGP 0.020A
3.3V_S0 VDDPL_33_PCIE 0.030A
VDDPL_33_SATA 0.020A
VDDPL_33_SYS

VDDIO_33_S
+3VALW VDDPL_33_USB_S
U25/U40 VDDAN_33_USB_S 0.2A
TPS2061DRG4 +USB_VCCA 3.3V_S5 VDDAN_33_S
VDDXL_33_S
+USB_VCCB
VDDIO_AZ_S

VDDCR_11_GBE_S
A Audio AMP Audio Codec Realtek EC LAN VDDRF_GBE_S A
USB X3 SATA ICS9LPRS488B Mini Card No Use VDDIO_33_GBE_S
TPA6017A2 ALC272 RTS5159 ENE KB926 Atheros AR8114 RTC VDDIO_GBE_S
VDDIO_18_FC
+5V Bettary
Dual+1 +5V 25mA +5V 3A +5V 45mA +3.3VALW 30mA +3.3VALW 201mA +3.3V 400mA +1.5VS 500mA
+3.3VS 300mA +3.3VS 3mA +3.3VS 1A 2.5~3.6V VDDBT_RTC_G
2.5A +3.3V +3.3VS 25mA +1.1V +3.3VALW 330mA BAT

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/3/8 Deciphered Date 2010/03/12 Title
SCHEMATIC, MB A5911
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401827 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, September 14, 2010 Sheet 5 of 55
5 4 3 2 1
 A B C D E

1 1

+1.1VS
VLDT CAP.
250 mil

2 2 1 1 1 1
C1 C2 C3 C4 C5 C6
H_CADIP[0..15] H_CADOP[0..15] 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
<12> H_CADIP[0..15] H_CADOP[0..15] <12>
10U_0805_10V4Z 10U_0805_10V4Z
H_CADIN[0..15] H_CADON[0..15] 1 1 2 2 2 2
<12> H_CADIN[0..15] H_CADON[0..15] <12>

Near CPU Socket

+1.1VS +1.1VS
JCPU1A
C7
2
TBD 2
D1 VLDT_A0 HT LINK VLDT_B0 AE2 2 1
D2 VLDT_A1 VLDT_B1 AE3
D3 AE4 10U_0805_10V4Z
VLDT_A2 VLDT_B2
D4 VLDT_A3 VLDT_B3 AE5

H_CADIP0 E3 AD1 H_CADOP0

H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
H_CADIP7 N3 T1 H_CADOP7
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
H_CADIP8 E5 AD4 H_CADOP8
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
H_CADIP9 F3 AD5 H_CADOP9
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5
H_CADIP10 G5 AB4 H_CADOP10
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP13 L5 V4 H_CADOP13
3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 L0_CADIN_L14 L0_CADOUT_L14 U5
H_CADIP15 N5 T4 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3

<12> H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 <12>

<12> H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 <12>
<12> H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 <12>
<12> H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 <12>

<12> H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 <12>

<12> H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 <12>
<12> H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 <12>
<12> H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 <12>

FOX_PZ6382A-284S-41F_Champlian
CONN@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 6 of 55
A B C D E
 A B C D E

Processor DDR3 Memory Interface

JCPU1C
<11> DDRB_SDQ[63..0]
MEM:DATA
DDRA_SDQ[63..0] <10>
DDRB_SDQ0 C11 G12 DDRA_SDQ0
1 +1.5V DDRB_SDQ1 MB_DATA0 MA_DATA0 DDRA_SDQ1 1
A11 MB_DATA1 MA_DATA1 F12
DDRB_SDQ2 A14 H14 DDRA_SDQ2
DDRB_SDQ3 MB_DATA2 MA_DATA2 DDRA_SDQ3
B14 MB_DATA3 MA_DATA3 G14
2

DDRB_SDQ4 G11 H11 DDRA_SDQ4

R1 DDRB_SDQ5 MB_DATA4 MA_DATA4 DDRA_SDQ5
E11 MB_DATA5 MA_DATA5 H12
1K_0402_1% DDRB_SDQ6 D12 C13 DDRA_SDQ6
DDRB_SDQ7 MB_DATA6 MA_DATA6 DDRA_SDQ7
A13 MB_DATA7 MA_DATA7 E13
DDRB_SDQ8 A15 H15 DDRA_SDQ8
1

MEM_VREF DDRB_SDQ9 MB_DATA8 MA_DATA8 DDRA_SDQ9

A16 MB_DATA9 MA_DATA9 E15
1000P_0402_50V7K
0.01U_0402_25V7K

DDRB_SDQ10 A19 E17 DDRA_SDQ10

MB_DATA10 MA_DATA10
2

1 1 DDRB_SDQ11 A20 H17 DDRA_SDQ11

R2 DDRB_SDQ12 MB_DATA11 MA_DATA11 DDRA_SDQ12
C14 MB_DATA12 MA_DATA12 E14
C9

C8

1K_0402_1% DDRB_SDQ13 D14 F14 DDRA_SDQ13

DDRB_SDQ14 MB_DATA13 MA_DATA13 DDRA_SDQ14
C18 MB_DATA14 MA_DATA14 C17
2 2 DDRB_SDQ15 DDRA_SDQ15
D18 G17
1

DDRB_SDQ16 MB_DATA15 MA_DATA15 DDRA_SDQ16

D20 MB_DATA16 MA_DATA16 G18
DDRB_SDQ17 A21 C19 DDRA_SDQ17
DDRB_SDQ18 MB_DATA17 MA_DATA17 DDRA_SDQ18
D24 MB_DATA18 MA_DATA18 D22
DDRB_SDQ19 C25 E20 DDRA_SDQ19
DDRB_SDQ20 MB_DATA19 MA_DATA19 DDRA_SDQ20
B20 MB_DATA20 MA_DATA20 E18
DDRB_SDQ21 C20 F18 DDRA_SDQ21
DDRB_SDQ22 MB_DATA21 MA_DATA21 DDRA_SDQ22
B24 MB_DATA22 MA_DATA22 B22
DDRB_SDQ23 C24 C23 DDRA_SDQ23
DDRB_SDQ24 MB_DATA23 MA_DATA23 DDRA_SDQ24
E23 MB_DATA24 MA_DATA24 F20
DDRB_SDQ25 E24 F22 DDRA_SDQ25
DDRB_SDQ26 MB_DATA25 MA_DATA25 DDRA_SDQ26
G25 MB_DATA26 MA_DATA26 H24
DDRB_SDQ27 G26 J19 DDRA_SDQ27
DDRB_SDQ28 MB_DATA27 MA_DATA27 DDRA_SDQ28
C26 MB_DATA28 MA_DATA28 E21
DDRB_SDQ29 D26 E22 DDRA_SDQ29
DDRB_SDQ30 MB_DATA29 MA_DATA29 DDRA_SDQ30
G23 MB_DATA30 MA_DATA30 H20
+1.5V +CPU_VDDR +CPU_VDDR DDRB_SDQ31 G24 H22 DDRA_SDQ31
JCPU1B DDRB_SDQ32 MB_DATA31 MA_DATA31 DDRA_SDQ32
AA24 MB_DATA32 MA_DATA32 Y24
2 Place them VDDR: DDR3 under 1033MHz DDRB_SDQ33 DDRA_SDQ33 2
1.5A AA23 MB_DATA33 MA_DATA33 AB24
2

close to CPU D10 W10 set to 0.9V to save power DDRB_SDQ34 AD24 AB22 DDRA_SDQ34
R368 VDDR1 MEM:CMD/CTRL/CLK
VDDR5 DDRB_SDQ35 MB_DATA34 MA_DATA34 DDRA_SDQ35
within 1" C10 VDDR2 VDDR6 AC10 AE24 MB_DATA35 MA_DATA35 AA21
B10 AB10 DDRB_SDQ36 AA26 W22 DDRA_SDQ36
0_0402_5% VDDR3 VDDR7 DDRB_SDQ37 MB_DATA36 MA_DATA36 DDRA_SDQ37
AD10 VDDR4 VDDR8 AA10 AA25 MB_DATA37 MA_DATA37 W21
R4 39.2_0402_1% A10 DDRB_SDQ38 AD26 Y22 DDRA_SDQ38
1

MEMZP AF10 VDDR9 DDRB_SDQ39 MB_DATA38 MA_DATA38 DDRA_SDQ39

1 2 MEMZP AE25 MB_DATA39 MA_DATA39 AA22
1 2 MEMZN AE10 Y10 VTT_SENSE DDRB_SDQ40 AC22 Y20 DDRA_SDQ40
MEMZN VDDR_SENSE PAD T1 MB_DATA40 MA_DATA40
2 R5 39.2_0402_1% DDRB_SDQ41 AD22 AA20 DDRA_SDQ41
C588 MEM_MA_RST# MEM_VREF DDRB_SDQ42 MB_DATA41 MA_DATA41 DDRA_SDQ42
<10> MEM_MA_RST# H16 MA_RESET_L MEMVREF W17 AE20 MB_DATA42 MA_DATA42 AA18
DDRB_SDQ43 AF20 AB18 DDRA_SDQ43
10U_0805_10V4Z DDRA_ODT0 MEM_MB_RST# DDRB_SDQ44 MB_DATA43 MA_DATA43 DDRA_SDQ44
<10> DDRA_ODT0 T19 MA0_ODT0 MB_RESET_L B18 MEM_MB_RST# <11> AF24 MB_DATA44 MA_DATA44 AB21
@ 1 DDRA_ODT1 V22 DDRB_SDQ45 AF23 AD21 DDRA_SDQ45
<10> DDRA_ODT1 MA0_ODT1 MB_DATA45 MA_DATA45
U21 W26 DDRB_ODT0 DDRB_SDQ46 AC20 AD19 DDRA_SDQ46
MA1_ODT0 MB0_ODT0 DDRB_ODT0 <11> MB_DATA46 MA_DATA46
V19 W23 DDRB_ODT1 DDRB_SDQ47 AD20 Y18 DDRA_SDQ47
MA1_ODT1 MB0_ODT1 DDRB_ODT1 <11> MB_DATA47 MA_DATA47
Y26 DDRB_SDQ48 AD18 AD17 DDRA_SDQ48
DDRA_SCS0# MB1_ODT0 DDRB_SDQ49 MB_DATA48 MA_DATA48 DDRA_SDQ49
<10> DDRA_SCS0# T20 MA0_CS_L0 AE18 MB_DATA49 MA_DATA49 W16
DDRA_SCS1# U19 V26 DDRB_SCS0# DDRB_SDQ50 AC14 W14 DDRA_SDQ50
<10> DDRA_SCS1# MA0_CS_L1 MB0_CS_L0 DDRB_SCS0# <11> MB_DATA50 MA_DATA50
U20 W25 DDRB_SCS1# DDRB_SDQ51 AD14 Y14 DDRA_SDQ51
MA1_CS_L0 MB0_CS_L1 DDRB_SCS1# <11> MB_DATA51 MA_DATA51
V20 U22 DDRB_SDQ52 AF19 Y17 DDRA_SDQ52
MA1_CS_L1 MB1_CS_L0 DDRB_SDQ53 MB_DATA52 MA_DATA52 DDRA_SDQ53
AC18 MB_DATA53 MA_DATA53 AB17
DDRA_CKE0 J22 J25 DDRB_CKE0 DDRB_SDQ54 AF16 AB15 DDRA_SDQ54
<10> DDRA_CKE0 MA_CKE0 MB_CKE0 DDRB_CKE0 <11> MB_DATA54 MA_DATA54
DDRA_CKE1 J20 H26 DDRB_CKE1 DDRB_SDQ55 AF15 AD15 DDRA_SDQ55
<10> DDRA_CKE1 MA_CKE1 MB_CKE1 DDRB_CKE1 <11> MB_DATA55 MA_DATA55
DDRB_SDQ56 AF13 AB13 DDRA_SDQ56
DDRA_CLK0 DDRB_CLK0 DDRB_SDQ57 MB_DATA56 MA_DATA56 DDRA_SDQ57
<10> DDRA_CLK0 N19 MA_CLK_H5 MB_CLK_H5 P22 DDRB_CLK0 <11> AC12 MB_DATA57 MA_DATA57 AD13
DDRA_CLK0# N20 R22 DDRB_CLK0# DDRB_SDQ58 AB11 Y12 DDRA_SDQ58
<10> DDRA_CLK0# MA_CLK_L5 MB_CLK_L5 DDRB_CLK0# <11> MB_DATA58 MA_DATA58
E16 A17 DDRB_SDQ59 Y11 W11 DDRA_SDQ59
MA_CLK_H1 MB_CLK_H1 DDRB_SDQ60 MB_DATA59 MA_DATA59 DDRA_SDQ60
F16 MA_CLK_L1 MB_CLK_L1 A18 AE14 MB_DATA60 MA_DATA60 AB14
Y16 AF18 DDRB_SDQ61 AF14 AA14 DDRA_SDQ61
MA_CLK_H7 MB_CLK_H7 DDRB_SDQ62 MB_DATA61 MA_DATA61 DDRA_SDQ62
AA16 MA_CLK_L7 MB_CLK_L7 AF17 AF11 MB_DATA62 MA_DATA62 AB12
DDRA_CLK1 P19 R26 DDRB_CLK1 DDRB_SDQ63 AD11 AA12 DDRA_SDQ63
<10> DDRA_CLK1 MA_CLK_H4 MB_CLK_H4 DDRB_CLK1 <11> MB_DATA63 MA_DATA63
DDRA_CLK1# P20 R25 DDRB_CLK1#
3 <10> DDRA_CLK1# MA_CLK_L4 MB_CLK_L4 DDRB_CLK1# <11> <11> DDRB_SDM[7..0] DDRA_SDM[7..0] <10> 3
DDRB_SDM0 A12 E12 DDRA_SDM0
<10> DDRA_SMA[15..0] DDRB_SMA[15..0] <11> MB_DM0 MA_DM0
DDRA_SMA0 N21 P24 DDRB_SMA0 DDRB_SDM1 B16 C15 DDRA_SDM1
DDRA_SMA1 MA_ADD0 MB_ADD0 DDRB_SMA1 DDRB_SDM2 MB_DM1 MA_DM1 DDRA_SDM2
M20 MA_ADD1 MB_ADD1 N24 A22 MB_DM2 MA_DM2 E19
DDRA_SMA2 N22 P26 DDRB_SMA2 DDRB_SDM3 E25 F24 DDRA_SDM3
DDRA_SMA3 MA_ADD2 MB_ADD2 DDRB_SMA3 DDRB_SDM4 MB_DM3 MA_DM3 DDRA_SDM4
M19 MA_ADD3 MB_ADD3 N23 AB26 MB_DM4 MA_DM4 AC24
DDRA_SMA4 M22 N26 DDRB_SMA4 DDRB_SDM5 AE22 Y19 DDRA_SDM5
DDRA_SMA5 MA_ADD4 MB_ADD4 DDRB_SMA5 DDRB_SDM6 MB_DM5 MA_DM5 DDRA_SDM6
L20 MA_ADD5 MB_ADD5 L23 AC16 MB_DM6 MA_DM6 AB16
DDRA_SMA6 M24 N25 DDRB_SMA6 DDRB_SDM7 AD12 Y13 DDRA_SDM7
DDRA_SMA7 MA_ADD6 MB_ADD6 DDRB_SMA7 MB_DM7 MA_DM7
L21 MA_ADD7 MB_ADD7 L24
DDRA_SMA8 L19 M26 DDRB_SMA8 DDRB_SDQS0 C12 G13 DDRA_SDQS0
MA_ADD8 MB_ADD8 <11> DDRB_SDQS0 MB_DQS_H0 MA_DQS_H0 DDRA_SDQS0 <10>
DDRA_SMA9 K22 K26 DDRB_SMA9 DDRB_SDQS0# B12 H13 DDRA_SDQS0#
MA_ADD9 MB_ADD9 <11> DDRB_SDQS0# MB_DQS_L0 MA_DQS_L0 DDRA_SDQS0# <10>
DDRA_SMA10 R21 T26 DDRB_SMA10 DDRB_SDQS1 D16 G16 DDRA_SDQS1
MA_ADD10 MB_ADD10 <11> DDRB_SDQS1 MB_DQS_H1 MA_DQS_H1 DDRA_SDQS1 <10>
DDRA_SMA11 L22 L26 DDRB_SMA11 DDRB_SDQS1# C16 G15 DDRA_SDQS1#
MA_ADD11 MB_ADD11 <11> DDRB_SDQS1# MB_DQS_L1 MA_DQS_L1 DDRA_SDQS1# <10>
DDRA_SMA12 K20 L25 DDRB_SMA12 DDRB_SDQS2 A24 C22 DDRA_SDQS2
MA_ADD12 MB_ADD12 <11> DDRB_SDQS2 MB_DQS_H2 MA_DQS_H2 DDRA_SDQS2 <10>
DDRA_SMA13 V24 W24 DDRB_SMA13 DDRB_SDQS2# A23 C21 DDRA_SDQS2#
MA_ADD13 MB_ADD13 <11> DDRB_SDQS2# MB_DQS_L2 MA_DQS_L2 DDRA_SDQS2# <10>
DDRA_SMA14 K24 J23 DDRB_SMA14 DDRB_SDQS3 F26 G22 DDRA_SDQS3
MA_ADD14 MB_ADD14 <11> DDRB_SDQS3 MB_DQS_H3 MA_DQS_H3 DDRA_SDQS3 <10>
DDRA_SMA15 K19 J24 DDRB_SMA15 DDRB_SDQS3# E26 G21 DDRA_SDQS3#
MA_ADD15 MB_ADD15 <11> DDRB_SDQS3# MB_DQS_L3 MA_DQS_L3 DDRA_SDQS3# <10>
DDRB_SDQS4 AC25 AD23 DDRA_SDQS4
<11> DDRB_SDQS4 MB_DQS_H4 MA_DQS_H4 DDRA_SDQS4 <10>
DDRA_SBS0# R20 R24 DDRB_SBS0# DDRB_SDQS4# AC26 AC23 DDRA_SDQS4#
<10> DDRA_SBS0# MA_BANK0 MB_BANK0 DDRB_SBS0# <11> <11> DDRB_SDQS4# MB_DQS_L4 MA_DQS_L4 DDRA_SDQS4# <10>
DDRA_SBS1# R23 U26 DDRB_SBS1# DDRB_SDQS5 AF21 AB19 DDRA_SDQS5
<10> DDRA_SBS1# MA_BANK1 MB_BANK1 DDRB_SBS1# <11> <11> DDRB_SDQS5 MB_DQS_H5 MA_DQS_H5 DDRA_SDQS5 <10>
DDRA_SBS2# J21 J26 DDRB_SBS2# DDRB_SDQS5# AF22 AB20 DDRA_SDQS5#
<10> DDRA_SBS2# MA_BANK2 MB_BANK2 DDRB_SBS2# <11> <11> DDRB_SDQS5# MB_DQS_L5 MA_DQS_L5 DDRA_SDQS5# <10>
DDRB_SDQS6 AE16 Y15 DDRA_SDQS6
<11> DDRB_SDQS6 MB_DQS_H6 MA_DQS_H6 DDRA_SDQS6 <10>
DDRA_SRAS# R19 U25 DDRB_SRAS# DDRB_SDQS6# AD16 W15 DDRA_SDQS6#
<10> DDRA_SRAS# MA_RAS_L MB_RAS_L DDRB_SRAS# <11> <11> DDRB_SDQS6# MB_DQS_L6 MA_DQS_L6 DDRA_SDQS6# <10>
DDRA_SCAS# T22 U24 DDRB_SCAS# DDRB_SDQS7 AF12 W12 DDRA_SDQS7
<10> DDRA_SCAS# MA_CAS_L MB_CAS_L DDRB_SCAS# <11> <11> DDRB_SDQS7 MB_DQS_H7 MA_DQS_H7 DDRA_SDQS7 <10>
DDRA_SWE# T24 U23 DDRB_SWE# DDRB_SDQS7# AE12 W13 DDRA_SDQS7#
<10> DDRA_SWE# MA_WE_L MB_WE_L DDRB_SWE# <11> <11> DDRB_SDQS7# MB_DQS_L7 MA_DQS_L7 DDRA_SDQS7# <10>

FOX_PZ6382A-284S-41F_Champlian FOX_PZ6382A-284S-41F_Champlian
CONN@ CONN@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 7 of 55
A B C D E
 A B C D E

Champlain: C1E
C1E: LDT_REQ# no connect
+2.5VDDA
CLMC: LDT_REQ# connect to NB +1.5V
L1 VDDA=0.25A
+2.5VS 1 2 3300P_0402_50V7K

1 FBMA-L11-201209-221LMA30T_0805 1 1 1 LDT_RES# / MEMHOT#

1
+ no support in S1g4
C11 4.7U_0805_10V4Z C12 C13 C14 R6

2
change to SGA00002N80 150U_B_6.3VM_R40M 0.22U_0603_16V4Z 10K_0402_5%
2 2 2 R7
2

2 2
1K_0402_5%
JCPU1D

B
1 1

1
Q1

E
F8 M11 CPU_THERMTRIP#_R 3 1 1 2
VDDA1 VSS H_THERMTRIP# <27>

C
F9 W18 R8 0_0402_5%
VDDA2 RSVD11 MMBT3904_NL_SOT23-3
1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC 1 2
<22> CLK_CPU_BCLK CLKIN_H SVC CPU_SVC <52> MAINPWON <44,45,49>
C16 CPU_CLKIN_SC_N A8 A4 CPU_SVD R9 @ 0_0402_5%
CLKIN_L SVD CPU_SVD <52>

1
LDT_RST# B7 +1.5V 1 2
R10 H_PWRGD RESET_L R11 300_0402_5%
A7 PWROK
169_0402_1% LDT_STOP# F10 AF6 CPU_THERMTRIP#_R
LDTSTOP_L THERMTRIP_L H_PROCHOT#
C6 AC7

2
T2 PAD LDTREQ_L PROCHOT_L
<22> CLK_CPU_BCLK# 1 2 MEMHOT_L AA8 PAD T3
C15 3900P_0402_50V7K +1.5V 1 2 CPU_SIC AF4 H_PROCHOT# 1 2
SIC H_PROCHOT_R# <26>
+1.5V R12 1 2 1K_0402_5% CPU_SID AF5 R13 0_0402_5%
R14 1K_0402_5% SID THERMDC_CPU
AE6 ALERT_L THERMDC W7
+1.5VS THERMDA_CPU
THERMDA W8 PROCHOT:
R15 1 2 44.2_0402_1% CPU_HTREF0 R6 HT_REF0
+1.1VS R16 1 2 44.2_0402_1% CPU_HTREF1 P6 Input: For HTC Function
HT_REF1
2

R17 CPU_VDD0_FB_H
Output: Over Temperature Condition
<52> CPU_VDD0_FB_H F6 VDD0_FB_H VDDIO_FB_H W9
300_0402_5% <52> CPU_VDD0_FB_L CPU_VDD0_FB_L E6 Y9
VDD0_FB_L VDDIO_FB_L

<52> CPU_VDD1_FB_H CPU_VDD1_FB_H Y6 H6 CPU_VDDNB_FB_H

CPU_VDDNB_FB_H <52>
1

LDT_RST# CPU_VDD1_FB_L AB6 VDD1_FB_H VDDNB_FB_H CPU_VDDNB_FB_L

<26> LDT_RST# <52> CPU_VDD1_FB_L VDD1_FB_L VDDNB_FB_L G6 CPU_VDDNB_FB_L <52>
+1.5VS CPU_DBRDY G10
1 DBRDY
C17 CPU_TMS AA9 E10 CPU_DBREQ#
0.01U_0402_25V4Z CPU_TCK TMS DBREQ_L
AC9 TCK
2

@ CPU_TRST# AD9 AE9 CPU_TDO

2 R18 CPU_TDI TRST_L TDO
AF9 TDI
300_0402_5% +1.5V
2 CPU_TEST23 2
AD7 TEST23 TEST28_H J7
H8
1

LDT_STOP# CPU_TEST18 TEST28_L CPU_SVC

H10 1 2
+1.5VS <13,26> LDT_STOP# CPU_TEST19 G9
TEST18
D7 CPU_TEST17 R19 1K_0402_5%
TEST19 TEST17 PAD T5
1 E7 CPU_TEST16 CPU_SVD 1 2
TEST16 PAD T6
C18 CPU_TEST25H E9 F7 CPU_TEST15 R20 1K_0402_5%
TEST25_H TEST15 PAD T7
2

0.01U_0402_25V4Z CPU_TEST25L E8 C7 CPU_TEST14

TEST25_L TEST14 PAD T8
R21 @
2 CPU_TEST21 +1.5V
300_0402_5% AB8 TEST21 TEST7 C3
CPU_TEST20 AF7 K8
CPU_TEST24 TEST20 TEST10 CPU_TEST25H
AE7 1 2
1

H_PWRGD CPU_TEST22 TEST24 R22 510_0402_5%

<26> H_PWRGD AE8 TEST22 TEST8 C4
CPU_TEST12 AC8 1 2
CPU_TEST27 TEST12 R23 @ 510_0402_5%
1 AF8 TEST27
C19 C9 CPU_TEST29_H_FBCLKOUT_P +1.5V
0.01U_0402_25V4Z TEST29_H CPU_TEST29_L_FBCLKOUT_N
1 2 C2 TEST9 TEST29_L C8 2 1
@ R24 0_0402_5% AA6 R25 80.6_0402_1% CPU_TEST25L 1 2
2 TEST6 R26 @ 510_0402_5%
A3 RSVD1 RSVD10 H18 1 2
A5 H19 R27 510_0402_5%
RSVD2 RSVD9
B3 RSVD3 RSVD8 AA7
+3VS B5 D5
RSVD4 RSVD7
C1 RSVD5 RSVD6 C5
+1.5V
0.1U_0402_16V4Z

1 FOX_PZ6382A-284S-41F_Champlian
CONN@
C20 CPU_TEST27 1 2
R28 1K_0402_5%
2 U1 @
1 8 EC_SMB_CK2 EC_SMB_CK2 <16,36>
VDD SCLK
3 THERMDA_CPU EC_SMB_DA2 3
2 D+ SDATA 7 EC_SMB_DA2 <16,36> For SCAN connect use
THERMDC_CPU 3 6 CPU_TEST12 1 2
D- ALERT# R29 1K_0402_5%
1 2
4 5 CPU_TEST18 1 2
C21 THERM# GND R30 1K_0402_5%
100P_0402_50V8J CPU_TEST19 1 2
@ ADM1032ARMZ_MSOP8 R31 1K_0402_5%
+1.5V CPU_TEST20 1 2
Address 1001 100X b R32 1K_0402_5%
CPU_TEST21 1 2
R33 1K_0402_5%

220_0402_5% R36

220_0402_5% R37

220_0402_5% R38

300_0402_5% R39

300_0402_5% R40
CPU_TEST22 1 2
R34 1K_0402_5%
1

2
CPU internal thermal sensor CPU_TEST24 1 2
R35 1K_0402_5%
CPU_TEST23 1 2
1 2 FDV301N, the Vgs is: R265 1K_0402_5%
JP2
min = 0.65V
2

1
C22 0.1U_0402_16V4Z
Typ = 0.85V @ @ @ @ 1 2
3 4
R41 R42 Max = 1.5V 5 6
+3VS 2 1 2 1 CPU_DBREQ# 1 R43 2
CPU_DBRDY 7 8 @ 0_0402_5%
31.6K_0402_1% 30K_0402_1% CPU_TCK
9 10
CPU_TMS 11 12 +3VS
CPU_TDI 13 14
15 16
2.09V for Gate CPU_TRST#
17 18
2

5
G

Q2 CPU_TDO U2
@ 19 20 LDT_RST#
2

P
CPU_SID 3 EC_SMB_DA SB_SID 21 22 HDT_RST# B
1 1 2 SB_SID <27> T0 SB 23 24 4 Y
R44 0_0402_5%
S

26 A 1 SB_PWRGD <13,27,36>

G
4 EC_SMB_DA2 4
1 2 TO EC
BSH111 1N_SOT23-3 R45 0_0402_5% NC7SZ08P5X_NL_SC70-5

3
CONN@ SAMTEC_ASP-68200-07
2
G

Q3
@
CPU_SIC 3 EC_SMB_CK SB_SIC T0 SB
1 1
R46
2
0_0402_5%
SB_SIC <27> Security Classification Compal Secret Data Compal Electronics, Inc.
S

1 2 EC_SMB_CK2 TO EC 2008/10/06 2010/03/12 Title

BSH111 1N_SOT23-3 R47 0_0402_5%
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 8 of 55
A B C D E
 A B C D E

JCPU1F

VDD(+CPU_CORE) decoupling. +CPU_CORE JCPU1E +CPU_CORE

AA4
AA11
VSS1
VSS2
VSS66
VSS67
J6
J8
36A AA13 VSS3 VSS68 J10
G4 VDD0_1 VDD1_1 P8 AA15 VSS4 VSS69 J12
H2 VDD0_2 VDD1_2 P10 AA17 VSS5 VSS70 J14
+CPU_CORE J9 R4 AA19 J16
VDD0_3 VDD1_3 VSS6 VSS71
J11 VDD0_4 VDD1_4 R7 AB2 VSS7 VSS72 J18
J13 VDD0_5 VDD1_5 R9 AB7 VSS8 VSS73 K2
J15 VDD0_6 VDD1_6 R11 AB9 VSS9 VSS74 K7
1 1 1 1 1 K6 VDD0_7 VDD1_7 T2 AB23 VSS10 VSS75 K9
K10 VDD0_8 VDD1_8 T6 AB25 VSS11 VSS76 K11
+ C23 + C24 + C25 + C26 + C27 K12 T8 AC11 K13
1 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M VDD0_9 VDD1_9 VSS12 VSS77 1
K14 VDD0_10 VDD1_10 T10 AC13 VSS13 VSS78 K15
@ L4 T12 AC15 K17
2 2 2 2 2 VDD0_11 VDD1_11 VSS14 VSS79
L7 VDD0_12 VDD1_12 T14 AC17 VSS15 VSS80 L6
L9 VDD0_13 VDD1_13 U7 AC19 VSS16 VSS81 L8
L11 U9 AC21 L10
Near CPU Socket L13
VDD0_14
VDD0_15
VDD1_14
VDD1_15 U11 AD6
VSS17
VSS18
VSS82
VSS83 L12
L15 VDD0_16 VDD1_16 U13 AD8 VSS19 VSS84 L14
M2 VDD0_17 VDD1_17 U15 AD25 VSS20 VSS85 L16
M6 VDD0_18 VDD1_18 V6 AE11 VSS21 VSS86 L18
M8 VDD0_19 VDD1_19 V8 AE13 VSS22 VSS87 M7
+CPU_CORE M10 V10 AE15 M9
+CPU_CORE VDD0_20 VDD1_20 VSS23 VSS88
N7 VDD0_21 VDD1_21 V12 AE17 VSS24 VSS89 AC6
N9 VDD0_22 VDD1_22 V14 AE19 VSS25 VSS90 M17
+CPU_CORE_NB N11 W4 AE21 N4
VDD0_23 VDD1_23 VSS26 VSS91
1
C28
1
C29
1
C30
1
C35
4A VDD1_24 Y2 AE23 VSS27 VSS92 N8
1 1 1 1 K16 VDDNB_1 VDD1_25 AC4 B4 VSS28 VSS93 N10
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C31 C32 C33 C34 M16 AD2 +1.5V B6 N16
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VDDNB_2 VDD1_26 VSS29 VSS94
2 2 2 2
P16 VDDNB_3 TBD B8 VSS30 VSS95 N18
T16 VDDNB_4 VDDIO27 Y25 B9 VSS31 VSS96 P2
2 2 2 2 +1.5V V16 VDDNB_5 VDDIO26 V25 B11 VSS32 VSS97 P7
VDDIO25 V23 B13 VSS33 VSS98 P9
+CPU_CORE H25 V21 B15 P11
+CPU_CORE VDDIO1 VDDIO24 VSS34 VSS99
J17 VDDIO2 VDDIO23 V18 B17 VSS35 VSS100 P17
K18 VDDIO3 VDDIO22 U17 B19 VSS36 VSS101 R8
K21 VDDIO4 VDDIO21 T25 B21 VSS37 VSS102 R10
1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23 B23 VSS38 VSS103 R16
C36 C37 C38 C39 C40 C41 K25 T21 B25 R18
0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J VDDIO6 VDDIO19 VSS39 VSS104
L17 VDDIO7 VDDIO18 T18 D6 VSS40 VSS105 T7
M18 VDDIO8 VDDIO17 R17 D8 VSS41 VSS106 T9
2 2 2 2 2 2
M21 VDDIO9 VDDIO16 P25 D9 VSS42 VSS107 T11
M23 P23 D11 T13
Under CPU Socket M25
VDDIO10
VDDIO11
VDDIO15
VDDIO14 P21 D13
VSS43
VSS44
VSS108
VSS109 T15
2 2
N17 VDDIO12 VDDIO13 P18 D15 VSS45 VSS110 T17
D17 VSS46 VSS111 U4
D19 VSS47 VSS112 U6
FOX_PZ6382A-284S-41F_Champlian D21 U8
Athlon 64 S1 CONN@ VSS48 VSS113
D23 U10
VDDIO decoupling. Processor Socket D25
E4
VSS49
VSS50
VSS51
VSS114
VSS115
VSS116
U12
U14
F2 U16

+1.5V
+CPU_CORE_NB decoupling. F11
F13
VSS52
VSS53
VSS54
VSS117
VSS118
VSS119
U18
V2
F15 VSS55 VSS120 V7
F17 VSS56 VSS121 V9
+CPU_CORE_NB F19 V11
VSS57 VSS122
F21 VSS58 VSS123 V13
1 1 1 1 1 1 F23 VSS59 VSS124 V15
C44 C45 C46 C47 C48 C50 1 1 1 F25 V17
22U_0805_6.3V6M 22U_0805_6.3V6M C42 C43 C49 VSS60 VSS125
H7 VSS61 VSS126 W6
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M H9 Y21
2 2 2 2 2 2 VSS62 VSS127
H21 VSS63 VSS128 Y23
2 2 2
H23 VSS64 VSS129 N6
J4 VSS65
FOX_PZ6382A-284S-41F_Champlian
Under CPU Socket Athlon 64 S1 CONN@
Processor Socket

Between CPU Socket and DIMM

+1.5V +CPU_VDDR
3 3
Near Power Supply
1
C51
1
C52
1
C53
1
C54
1
C354
1
C355
VDDR decoupling. 1 1
C55
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z + C56 22U_0805_6.3V6M
change to SGA00002N80 150U_B_6.3VM_R40M
2 2 2 2 2 2 2
2

180PF Qt'y follow the distance between

+1.5V +1.5V CPU socket and DIMM0. <2.5inch> +CPU_VDDR

1 1 2 2 1 1
C64 C65 C68 C69 1 1 1 1 1 1 1 1
0.01U_0402_25V4Z 0.01U_0402_25V4Z C66 C67 180P_0402_50V8J 180P_0402_50V8J C57 C58 C59 C60 C61 C62 C63 C70
0.1U_0402_16V7K 0.1U_0402_16V7K 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J
2 2 1 1 2 2
2 2 2 2 2 2 2 2

+1.5V
Near CPU Socket Right side.
+CPU_VDDR
1
1 1 1 1
+ C75
C71 C72 C73 C74 330U_X_2VM_R6M 1 1 1 1 1 1 1 1
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z C76 C77 C78 C79 C80 C81 C82 C83
2 2 2 2 2 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2 2 2
4 4

Near CPU Socket Left side.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 9 of 55
A B C D E
 A B C D E

+VREF_DQ +1.5V +1.5V

JDIMM1
1 VREF_DQ VSS1 2
3 4 DDRA_SDQ4
DDRA_SDQ0 VSS2 DQ4 DDRA_SDQ5
5 DQ0 DQ5 6
DDRA_SDQ1 7 8
DQ1 VSS3 DDRA_SDQS0#
9 VSS4 DQS#0 10 DDRA_SDQS0# <7>
DDRA_SDM0 11 12 DDRA_SDQS0
DM0 DQS0 DDRA_SDQS0 <7> DDRA_SDQ[0..63]
13 VSS5 VSS6 14 DDRA_SDQ[0..63] <7>
DDRA_SDQ2 15 16 DDRA_SDQ6
DDRA_SDQ3 DQ2 DQ6 DDRA_SDQ7 DDRA_SDM[0..7]
17 DQ3 DQ7 18 DDRA_SDM[0..7] <7>
19 VSS7 VSS8 20
1 DDRA_SDQ8 DDRA_SDQ12 1
21 DQ8 DQ12 22
DDRA_SDQ9 23 24 DDRA_SDQ13
DQ9 DQ13 DDRA_SMA[0..15]
25 VSS9 VSS10 26 DDRA_SMA[0..15] <7>
DDRA_SDQS1# 27 28 DDRA_SDM1
<7> DDRA_SDQS1# DQS#1 DM1
DDRA_SDQS1 29 30 MEM_MA_RST#
<7> DDRA_SDQS1 DQS1 RESET# MEM_MA_RST# <7>
31 VSS11 VSS12 32
DDRA_SDQ10 33 34 DDRA_SDQ14
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDRA_SDQ16 39 40 DDRA_SDQ20
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDRA_SDQS2# 45 46 DDRA_SDM2
<7> DDRA_SDQS2# DQS#2 DM2
DDRA_SDQS2 47 48
<7> DDRA_SDQS2 DQS2 VSS17
49 50 DDRA_SDQ22
DDRA_SDQ18 VSS18 DQ22 DDRA_SDQ23
51 DQ18 DQ23 52
DDRA_SDQ19 53 54
DQ19 VSS19 DDRA_SDQ28
55 VSS20 DQ28 56
DDRA_SDQ24 57 58 DDRA_SDQ29 +VREF_CA +1.5V
DDRA_SDQ25 DQ24 DQ29 +VREF_DQ +1.5V
59 DQ25 VSS21 60
61 62 DDRA_SDQS3#
VSS22 DQS#3 DDRA_SDQS3# <7>

2
DDRA_SDM3 63 64 DDRA_SDQS3
DM3 DQS3 DDRA_SDQS3 <7>

2
65 66 R310
DDRA_SDQ26 VSS23 VSS24 DDRA_SDQ30 R48 1K_0402_1%
67 DQ26 DQ30 68
DDRA_SDQ27 69 70 DDRA_SDQ31 1K_0402_1%
DQ27 DQ31
71 72

1
VSS25 VSS26 +VREF_CA

1
+VREF_DQ

1000P_0402_50V7K
0.01U_0402_25V7K
0.01U_0402_25V7K

4.7U_0805_10V4Z
DDRA_CKE0 73 74 DDRA_CKE1
<7> DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 <7>

1000P_0402_50V7K
4.7U_0805_10V4Z
75 VDD1 VDD2 76 1 2 1

2
77 78 DDRA_SMA15 1 2 1 C235 C351 C680
NC1 A15

2
2 DDRA_SBS2# DDRA_SMA14 C84 C85 C10 @ R315 2
<7> DDRA_SBS2# 79 BA2 A14 80
81 82 @ R49 1K_0402_1%
DDRA_SMA12 VDD3 VDD4 DDRA_SMA11 1K_0402_1% 2 1 2
83 A12/BC# A11 84
DDRA_SMA9 DDRA_SMA7 2 1 2
85 86

1
A9 A7
87 88

1
DDRA_SMA8 VDD5 VDD6 DDRA_SMA6
89 A8 A6 90
DDRA_SMA5 91 92 DDRA_SMA4
A5 A4
93 VDD7 VDD8 94
DDRA_SMA3 95 96 DDRA_SMA2
DDRA_SMA1 A3 A2 DDRA_SMA0
97 A1 A0 98
99 VDD9 VDD10 100
DDRA_CLK0 101 102 DDRA_CLK1
<7> DDRA_CLK0 CK0 CK1 DDRA_CLK1 <7>
DDRA_CLK0# 103 104 DDRA_CLK1#
<7> DDRA_CLK0# CK0# CK1# DDRA_CLK1# <7>
105 VDD11 VDD12 106
DDRA_SMA10 107 108 DDRA_SBS1#
A10/AP BA1 DDRA_SBS1# <7>
DDRA_SBS0# 109 110 DDRA_SRAS#
<7> DDRA_SBS0# BA0 RAS# DDRA_SRAS# <7>
111 VDD13 VDD14 112
DDRA_SWE# 113 114 DDRA_SCS0#
<7> DDRA_SWE# WE# S0# DDRA_SCS0# <7>
DDRA_SCAS# 115 116 DDRA_ODT0
<7> DDRA_SCAS# CAS# ODT0 DDRA_ODT0 <7>
117 VDD15 VDD16 118
DDRA_SMA13 119 120 DDRA_ODT1
A13 ODT1 DDRA_ODT1 <7>
DDRA_SCS1# 121 122
<7> DDRA_SCS1# S1# NC2
123 VDD17 VDD18 124
125 NCTEST VREF_CA 126 +VREF_CA
127 VSS27 VSS28 128
DDRA_SDQ32 129 130 DDRA_SDQ36
DDRA_SDQ33 DQ32 DQ36 DDRA_SDQ37
131 DQ33 DQ37 132 1
133 134 C89
DDRA_SDQS4# VSS29 VSS30 DDRA_SDM4
<7> DDRA_SDQS4# 135 DQS#4 DM4 136
DDRA_SDQS4 137 138 1000P_0402_50V7K +1.5V
<7> DDRA_SDQS4 DQS4 VSS31 2
139 140 DDRA_SDQ38
DDRA_SDQ34 VSS32 DQ38 DDRA_SDQ39 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
141 DQ34 DQ39 142
3 DDRA_SDQ35 3
143 DQ35 VSS33 144 2 2 2 2 2 2 2 2 2 2
145 146 DDRA_SDQ44
DDRA_SDQ40 VSS34 DQ44 DDRA_SDQ45 C87 C643 C88 C644 C640 C645 C641 C646 C642 C647
147 DQ40 DQ45 148
DDRA_SDQ41 149 150
DQ41 VSS35 DDRA_SDQS5# 1 1 1 1 1 1 1 1 1 1
151 VSS36 DQS#5 152 DDRA_SDQS5# <7>
DDRA_SDM5 153 154 DDRA_SDQS5 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DM5 DQS5 DDRA_SDQS5 <7>
155 VSS37 VSS38 156
DDRA_SDQ42 157 158 DDRA_SDQ46
DDRA_SDQ43 DQ42 DQ46 DDRA_SDQ47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDRA_SDQ48 163 164 DDRA_SDQ52
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53 +0.75VS
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDRA_SDQS6# 169 170 DDRA_SDM6 0.1U_0402_16V4Z
<7> DDRA_SDQS6# DQS#6 DM6
DDRA_SDQS6 171 172 2 2 1
<7> DDRA_SDQS6 DQS6 VSS43
173 174 DDRA_SDQ54
DDRA_SDQ50 VSS44 DQ54 DDRA_SDQ55 C665 C664 C961
175 DQ50 DQ55 176
DDRA_SDQ51 177 178
DQ51 VSS45 DDRA_SDQ60 1 1 2
179 VSS46 DQ60 180
DDRA_SDQ56 181 182 DDRA_SDQ61 0.1U_0402_16V4Z 4.7U_0603_6.3V6K Place near DIMM1
DDRA_SDQ57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDRA_SDQS7#
VSS48 DQS#7 DDRA_SDQS7# <7>
DDRA_SDM7 187 188 DDRA_SDQS7
DM7 DQS7 DDRA_SDQS7 <7>
189 VSS49 VSS50 190
DDRA_SDQ58 191 192 DDRA_SDQ62
DDRA_SDQ59 DQ58 DQ62 DDRA_SDQ63
193 DQ59 DQ63 194
R50 10K_0402_5% 195 196
VSS51 VSS52
1 2 197 SA0 EVENT# 198 PAD T9
+3VS 199 VDDSPD SDA 200 SB_SMDAT0 <11,22,27,34>
201 SA1 SCL 202 SB_SMCLK0 <11,22,27,34>
203 VTT1 VTT2 204 +0.75VS
1

4 R51 4
205 G1 G2 206
+3VS
10K_0402_5% FOX_AS0A626-U8SN-7F
CONN@
2

1 1
C90 C91

2.2U_0603_6.3V4Z 0.1U_0402_16V4Z Security Classification Compal Secret Data Compal Electronics, Inc.
2 2
2008/10/06 2010/03/12 Title
DIMM_A STD H:8mm Issued Date Deciphered Date
SCHEMATIC, MB A5911
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
<Address: 00> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 10 of 55
A B C D E
 A B C D E

+VREF_DQ +1.5V +1.5V

JDIMM2
1 VREF_DQ VSS1 2
3 4 DDRB_SDQ4
DDRB_SDQ0 VSS2 DQ4 DDRB_SDQ5
5 DQ0 DQ5 6
DDRB_SDQ1 7 8
DQ1 VSS3 DDRB_SDQS0#
9 VSS4 DQS#0 10 DDRB_SDQS0# <7>
DDRB_SDM0 11 12 DDRB_SDQS0
DM0 DQS0 DDRB_SDQS0 <7> DDRB_SDQ[0..63]
13 VSS5 VSS6 14 DDRB_SDQ[0..63] <7>
DDRB_SDQ2 15 16 DDRB_SDQ6
DDRB_SDQ3 DQ2 DQ6 DDRB_SDQ7 DDRB_SDM[0..7]
17 DQ3 DQ7 18 DDRB_SDM[0..7] <7>
19 VSS7 VSS8 20
1 DDRB_SDQ8 DDRB_SDQ12 1
21 DQ8 DQ12 22
DDRB_SDQ9 23 24 DDRB_SDQ13
DQ9 DQ13 DDRB_SMA[0..15]
25 VSS9 VSS10 26 DDRB_SMA[0..15] <7>
DDRB_SDQS1# 27 28 DDRB_SDM1
<7> DDRB_SDQS1# DQS#1 DM1
DDRB_SDQS1 29 30 MEM_MB_RST#
<7> DDRB_SDQS1 DQS1 RESET# MEM_MB_RST# <7>
31 VSS11 VSS12 32
DDRB_SDQ10 33 34 DDRB_SDQ14
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDRB_SDQ16 39 40 DDRB_SDQ20
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDRB_SDQS2# 45 46 DDRB_SDM2
<7> DDRB_SDQS2# DQS#2 DM2
DDRB_SDQS2 47 48
<7> DDRB_SDQS2 DQS2 VSS17
49 50 DDRB_SDQ22
DDRB_SDQ18 VSS18 DQ22 DDRB_SDQ23
51 DQ18 DQ23 52
DDRB_SDQ19 53 54
DQ19 VSS19 DDRB_SDQ28
55 VSS20 DQ28 56
DDRB_SDQ24 57 58 DDRB_SDQ29
DDRB_SDQ25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDRB_SDQS3#
VSS22 DQS#3 DDRB_SDQS3# <7>
DDRB_SDM3 63 64 DDRB_SDQS3
DM3 DQS3 DDRB_SDQS3 <7>
65 VSS23 VSS24 66
DDRB_SDQ26 67 68 DDRB_SDQ30
DDRB_SDQ27 DQ26 DQ30 DDRB_SDQ31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

DDRB_CKE0 73 74 DDRB_CKE1
<7> DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 <7>
75 VDD1 VDD2 76
77 78 DDRB_SMA15
2 DDRB_SBS2# NC1 A15 DDRB_SMA14 2
<7> DDRB_SBS2# 79 BA2 A14 80
81 VDD3 VDD4 82
DDRB_SMA12 83 84 DDRB_SMA11
DDRB_SMA9 A12/BC# A11 DDRB_SMA7
85 A9 A7 86
87 VDD5 VDD6 88
DDRB_SMA8 89 90 DDRB_SMA6 +VREF_DQ +VREF_CA
DDRB_SMA5 A8 A6 DDRB_SMA4
91 A5 A4 92
93 VDD7 VDD8 94
DDRB_SMA3 95 96 DDRB_SMA2 +VREF_DQ +VREF_CA
DDRB_SMA1 A3 A2 DDRB_SMA0
97 A1 A0 98

1000P_0402_50V7K

1000P_0402_50V7K
99 VDD9 VDD10 100

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.7U_0805_10V4Z

4.7U_0805_10V4Z
DDRB_CLK0 101 102 DDRB_CLK1
<7> DDRB_CLK0 CK0 CK1 DDRB_CLK1 <7>
DDRB_CLK0# 103 104 DDRB_CLK1# 1 1 1 1 1 1
<7> DDRB_CLK0# CK0# CK1# DDRB_CLK1# <7>
105 106 C92 C93 C682 C352 C353 C683
DDRB_SMA10 VDD11 VDD12 DDRB_SBS1#
107 A10/AP BA1 108 DDRB_SBS1# <7>
DDRB_SBS0# 109 110 DDRB_SRAS#
<7> DDRB_SBS0# BA0 RAS# DDRB_SRAS# <7> 2 2 2 2 2 2
111 VDD13 VDD14 112
DDRB_SWE# 113 114 DDRB_SCS0#
<7> DDRB_SWE# WE# S0# DDRB_SCS0# <7>
DDRB_SCAS# 115 116 DDRB_ODT0
<7> DDRB_SCAS# CAS# ODT0 DDRB_ODT0 <7>
117 VDD15 VDD16 118
DDRB_SMA13 119 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 <7>
DDRB_SCS1# 121 122
<7> DDRB_SCS1# S1# NC2
123 VDD17 VDD18 124
125 NCTEST VREF_CA 126 +VREF_CA
127 VSS27 VSS28 128
DDRB_SDQ32 129 130 DDRB_SDQ36
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37
131 DQ33 DQ37 132 1
133 134 C94
DDRB_SDQS4# VSS29 VSS30 DDRB_SDM4 1000P_0402_50V7K
<7> DDRB_SDQS4# 135 DQS#4 DM4 136
DDRB_SDQS4 137 138
<7> DDRB_SDQS4 DQS4 VSS31 2
139 140 DDRB_SDQ38
DDRB_SDQ34 VSS32 DQ38 DDRB_SDQ39
141 DQ34 DQ39 142
3 DDRB_SDQ35 3
143 DQ35 VSS33 144
145 146 DDRB_SDQ44
DDRB_SDQ40 VSS34 DQ44 DDRB_SDQ45
147 DQ40 DQ45 148
DDRB_SDQ41 149 150
DQ41 VSS35 DDRB_SDQS5#
151 VSS36 DQS#5 152 DDRB_SDQS5# <7>
DDRB_SDM5 153 154 DDRB_SDQS5 +1.5V
DM5 DQS5 DDRB_SDQS5 <7>
155 VSS37 VSS38 156
DDRB_SDQ42 157 158 DDRB_SDQ46 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47
159 DQ43 DQ47 160 2 2 2 2 2 2 2 2 2 2
161 VSS39 VSS40 162
DDRB_SDQ48 163 164 DDRB_SDQ52 C677 C670 C666 C671 C667 C672 C668 C673 C669 C674
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
165 DQ49 DQ53 166
1 1 1 1 1 1 1 1 1 1
167 VSS41 VSS42 168
DDRB_SDQS6# 169 170 DDRB_SDM6 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<7> DDRB_SDQS6# DQS#6 DM6
DDRB_SDQS6 171 172
<7> DDRB_SDQS6 DQS6 VSS43
173 174 DDRB_SDQ54
DDRB_SDQ50 VSS44 DQ54 DDRB_SDQ55
175 DQ50 DQ55 176
DDRB_SDQ51 177 178
DQ51 VSS45 DDRB_SDQ60
179 VSS46 DQ60 180
DDRB_SDQ56 181 182 DDRB_SDQ61 +0.75VS
DDRB_SDQ57 DQ56 DQ61 +1.5V
183 DQ57 VSS47 184
185 186 DDRB_SDQS7# 0.1U_0402_16V4Z
VSS48 DQS#7 DDRB_SDQS7# <7>
DDRB_SDM7 187 188 DDRB_SDQS7 2 2 1 1
DM7 DQS7 DDRB_SDQS7 <7>
189 VSS49 VSS50 190
DDRB_SDQ58 191 192 DDRB_SDQ62 C676 C675 C925 + C86
DDRB_SDQ59 DQ58 DQ62 DDRB_SDQ63 @ 330U_X_2VM_R6M
193 DQ59 DQ63 194
R52 10K_0402_5% 1 1 2
195 VSS51 VSS52 196
0.1U_0402_16V4Z 4.7U_0603_6.3V6K 2
1 2 197 SA0 EVENT# 198 PAD T10
+3VS 199 VDDSPD SDA 200 SB_SMDAT0 <10,22,27,34>
201 SA1 SCL 202 SB_SMCLK0 <10,22,27,34> Place near DIMM2
203 VTT1 VTT2 204 +0.75VS
1

4 R53 4
205 G1 G2 206

10K_0402_5% FOX_AS0A626-U4SN-7F
CONN@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

DIMM_B STD H:4mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
<Address: 01> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 11 of 55
A B C D E
 A B C D E

PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15]
<15> PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15] <15>
PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15]
<15> PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15] <15>

U3B
PCIE_GTX_C_MRX_P0 D4 A5 PCIE_MTX_GRX_P0 C95 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_GTX_C_MRX_N0 GFX_RX0P GFX_TX0P PCIE_MTX_GRX_N0 C96 PCIE_MTX_C_GRX_N0
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 1 2VGA@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_P1 A3 A4 PCIE_MTX_GRX_P1 C97 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
PCIE_GTX_C_MRX_N1 GFX_RX1P GFX_TX1P PCIE_MTX_GRX_N1 C98
B3 GFX_RX1N GFX_TX1N B4 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
1 PCIE_GTX_C_MRX_P2 PCIE_MTX_GRX_P2 C99 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2 1
C2 GFX_RX2P GFX_TX2P C3 2VGA@
PCIE_GTX_C_MRX_N2 C1 B2 PCIE_MTX_GRX_N2 C100 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_GTX_C_MRX_P3 GFX_RX2N GFX_TX2N PCIE_MTX_GRX_P3 C101 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
E5 GFX_RX3P GFX_TX3P D1 2VGA@
PCIE_GTX_C_MRX_N3 F5 D2 PCIE_MTX_GRX_N3 C102 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
PCIE_GTX_C_MRX_P4 GFX_RX3N GFX_TX3N PCIE_MTX_GRX_P4 C103 1
G5 GFX_RX4P GFX_TX4P E2 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
PCIE_GTX_C_MRX_N4 G6 E1 PCIE_MTX_GRX_N4 C104 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
PCIE_GTX_C_MRX_P5 GFX_RX4N GFX_TX4N PCIE_MTX_GRX_P5 C105 1
H5 GFX_RX5P GFX_TX5P F4 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
PCIE_GTX_C_MRX_N5 H6 F3 PCIE_MTX_GRX_N5 C106 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
PCIE_GTX_C_MRX_P6 GFX_RX5N GFX_TX5N PCIE_MTX_GRX_P6 C107 1
J6 GFX_RX6P GFX_TX6P F1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_GTX_C_MRX_N6 J5 F2 PCIE_MTX_GRX_N6 C108 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
PCIE_GTX_C_MRX_P7 GFX_RX6N GFX_TX6N PCIE_MTX_GRX_P7 C109 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
J7 GFX_RX7P GFX_TX7P H4 2VGA@
PCIE_GTX_C_MRX_N7 J8 H3 PCIE_MTX_GRX_N7 C110 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
PCIE_GTX_C_MRX_P8 GFX_RX7N GFX_TX7N PCIE_MTX_GRX_P8 C111 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
L5 GFX_RX8P GFX_TX8P H1 2VGA@
PCIE_GTX_C_MRX_N8 L6 H2 PCIE_MTX_GRX_N8 C112 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
PCIE_GTX_C_MRX_P9 GFX_RX8N GFX_TX8N PCIE_MTX_GRX_P9 C113 1
M8 GFX_RX9P GFX_TX9P J2 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
PCIE_GTX_C_MRX_N9 L8 J1 PCIE_MTX_GRX_N9 C114 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
GFX_RX9N GFX_TX9N

PCIE I/F GFX

PCIE_GTX_C_MRX_P10 P7 K4 PCIE_MTX_GRX_P10 C115 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
PCIE_GTX_C_MRX_N10 GFX_RX10P GFX_TX10P PCIE_MTX_GRX_N10 C116 1 PCIE_MTX_C_GRX_N10
M7 GFX_RX10N GFX_TX10N K3 2VGA@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_P11 P5 K1 PCIE_MTX_GRX_P11 C117 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
PCIE_GTX_C_MRX_N11 GFX_RX11P GFX_TX11P PCIE_MTX_GRX_N11 C118 1
M5 GFX_RX11N GFX_TX11N K2 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
PCIE_GTX_C_MRX_P12 R8 M4 PCIE_MTX_GRX_P12 C119 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
PCIE_GTX_C_MRX_N12 GFX_RX12P GFX_TX12P PCIE_MTX_GRX_N12 C120 1
P8 GFX_RX12N GFX_TX12N M3 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PCIE_GTX_C_MRX_P13 R6 M1 PCIE_MTX_GRX_P13 C121 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
PCIE_GTX_C_MRX_N13 GFX_RX13P GFX_TX13P PCIE_MTX_GRX_N13 C122 1
R5 GFX_RX13N GFX_TX13N M2 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
PCIE_GTX_C_MRX_P14 P4 N2 PCIE_MTX_GRX_P14 C123 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
PCIE_GTX_C_MRX_N14 GFX_RX14P GFX_TX14P PCIE_MTX_GRX_N14 C124 1 PCIE_MTX_C_GRX_N14
P3 GFX_RX14N GFX_TX14N N1 2VGA@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_P15 T4 P1 PCIE_MTX_GRX_P15 C125 1 2VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
PCIE_GTX_C_MRX_N15 GFX_RX15P GFX_TX15P PCIE_MTX_GRX_N15 C126 1 PCIE_MTX_C_GRX_N15
T3 GFX_RX15N GFX_TX15N P2 2VGA@ 0.1U_0402_16V7K

<32> PCIE_PTX_C_IRX_P0 1 2 GPP0P AE3 GPP_RX0P GPP_TX0P AC1 PCIE_ITX_PRX_P0 C127 1 2 0.1U_0402_16V7K
PCIE_ITX_C_PRX_P0 <32>
<32> PCIE_PTX_C_IRX_N0 2 GPP0N AD4
R54 1 0_0402_5%
GPP_RX0N GPP_TX0N AC2 PCIE_ITX_PRX_N0 C128 1 2 0.1U_0402_16V7K
PCIE_ITX_C_PRX_N0 <32>GLAN
R55 0_0402_5% AE2 AB4 PCIE_ITX_PRX_P1 C129 1 2 0.1U_0402_16V7K
2 <34> PCIE_PTX_C_IRX_P1 GPP_RX1P GPP_TX1P PCIE_ITX_C_PRX_P1 <34> 2
PCIE_ITX_PRX_N1 C130 0.1U_0402_16V7K
<34> PCIE_PTX_C_IRX_N1 AD3 GPP_RX1N GPP_TX1N AB3 1 2 PCIE_ITX_C_PRX_N1 <34>WLAN
AD1 GPP_RX2P GPP_TX2P AA2

PCIE_PTX_C_IRX_P0 1 @
AD2
PCIE_PTX_C_IRX_P3V5 GPP_RX2N PCIE I/F GPP GPP_TX2N AA1
PCIE_ITX_PRX_P3 C131 1@ 0.1U_0402_16V7K PCIE_ITX_C_PRX_P0
2
PCIE_PTX_C_IRX_N0 1R56 @ 0_0402_5% PCIE_PTX_C_IRX_N3 GPP_RX3P GPP_TX3P Y1
PCIE_ITX_PRX_N3 C132 @1
2 Reserve for LAN debug
2 W6 GPP_RX3N GPP_TX3N Y2 2 0.1U_0402_16V7K PCIE_ITX_C_PRX_N0
R57 0_0402_5% U5 Y4
GPP_RX4P GPP_TX4P H_CADOP[0..15] H_CADIP[0..15]
R56,R57 close to R54,R55 U6 GPP_RX4N GPP_TX4N Y3 C131,C132 close to C127,C128 <6> H_CADOP[0..15] H_CADIP[0..15] <6>
U8 GPP_RX5P GPP_TX5P V1
U7 V2 H_CADON[0..15] H_CADIN[0..15]
GPP_RX5N GPP_TX5N <6> H_CADON[0..15] H_CADIN[0..15] <6>

<26> SB_RX0P AA8 AD7 SB_TX0P_C C133 1 2 0.1U_0402_16V7K

SB_RX0P SB_TX0P SB_TX0P <26>
<26> SB_RX0N Y8 AE7 SB_TX0N_C C134 1 2 0.1U_0402_16V7K
SB_RX0N SB_TX0N SB_TX0N <26>
<26> SB_RX1P AA7 AE6 SB_TX1P_C C135 1 2 0.1U_0402_16V7K
SB_RX1P SB_TX1P SB_TX1P <26>
<26> SB_RX1N Y7 AD6 SB_TX1N_C C136 1 2 0.1U_0402_16V7K U3A
SB_RX1N SB_TX1N SB_TX1N <26>
<26> SB_RX2P AA5 PCIE I/F SB AB6 SB_TX2P_C C137 1 2 0.1U_0402_16V7K H_CADOP0 Y25 D24 H_CADIP0
SB_RX2P SB_TX2P SB_TX2P <26> HT_RXCAD0P HT_TXCAD0P
<26> SB_RX2N AA6 AC6 SB_TX2N_C C138 1 2 0.1U_0402_16V7K H_CADON0 Y24 PART 1 OF 6 D25 H_CADIN0
SB_RX2N SB_TX2N SB_TX2N <26> HT_RXCAD0N HT_TXCAD0N
<26> SB_RX3P W5 AD5 SB_TX3P_C C139 1 2 0.1U_0402_16V7K H_CADOP1 V22 E24 H_CADIP1
SB_RX3P SB_TX3P SB_TX3P <26> HT_RXCAD1P HT_TXCAD1P
<26> SB_RX3N Y5 AE5 SB_TX3N_C C140 1 2 0.1U_0402_16V7K H_CADON1 V23 E25 H_CADIN1
SB_RX3N SB_TX3N SB_TX3N <26> HT_RXCAD1N HT_TXCAD1N
H_CADOP2 V25 F24 H_CADIP2
R59 1.27K_0402_1% H_CADON2 HT_RXCAD2P HT_TXCAD2P H_CADIN2
PCE_CALRP(PCE_BCALRP) AC8 1 2 V24 HT_RXCAD2N HT_TXCAD2N F25
AB8 R58 1 2 2K_0402_1% +1.1VS H_CADOP3 U24 F23 H_CADIP3
PCE_CALRN(PCE_BCALRN) H_CADON3 HT_RXCAD3P HT_TXCAD3P H_CADIN3
U25 HT_RXCAD3N HT_TXCAD3N F22
RS780M_FCBGA528 H_CADOP4 T25 H23 H_CADIP4
H_CADON4 HT_RXCAD4P HT_TXCAD4P H_CADIN4
T24 HT_RXCAD4N HT_TXCAD4N H22

HYPER TRANSPORT CPU I/F

H_CADOP5 H_CADIP5
RS880 A11(SA000032710) H_CADON5
P22
P23
HT_RXCAD5P HT_TXCAD5P J25
J24 H_CADIN5
H_CADOP6 HT_RXCAD5N HT_TXCAD5N H_CADIP6
P25 HT_RXCAD6P HT_TXCAD6P K24
H_CADON6 P24 K25 H_CADIN6
H_CADOP7 HT_RXCAD6N HT_TXCAD6N H_CADIP7
N24 HT_RXCAD7P HT_TXCAD7P K23
H_CADON7 N25 K22 H_CADIN7
HT_RXCAD7N HT_TXCAD7N
H_CADOP8 AC24 F21 H_CADIP8
3 H_CADON8 HT_RXCAD8P HT_TXCAD8P H_CADIN8 3
AC25 HT_RXCAD8N HT_TXCAD8N G21
H_CADOP9 AB25 G20 H_CADIP9
H_CADON9 HT_RXCAD9P HT_TXCAD9P H_CADIN9
AB24 HT_RXCAD9N HT_TXCAD9N H21
H_CADOP10 AA24 J20 H_CADIP10
H_CADON10 HT_RXCAD10P HT_TXCAD10P H_CADIN10
AA25 HT_RXCAD10N HT_TXCAD10N J21
H_CADOP11 Y22 J18 H_CADIP11
H_CADON11 HT_RXCAD11P HT_TXCAD11P H_CADIN11
Y23 HT_RXCAD11N HT_TXCAD11N K17
H_CADOP12 W21 L19 H_CADIP12
H_CADON12 HT_RXCAD12P HT_TXCAD12P H_CADIN12
W20 HT_RXCAD12N HT_TXCAD12N J19
H_CADOP13 V21 M19 H_CADIP13
H_CADON13 HT_RXCAD13P HT_TXCAD13P H_CADIN13
V20 HT_RXCAD13N HT_TXCAD13N L18
H_CADOP14 U20 M21 H_CADIP14
H_CADON14 HT_RXCAD14P HT_TXCAD14P H_CADIN14
U21 HT_RXCAD14N HT_TXCAD14N P21
H_CADOP15 U19 P18 H_CADIP15
H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15
U18 HT_RXCAD15N HT_TXCAD15N M18

<6> H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 <6>

<6> H_CLKON0 T23 HT_RXCLK0N HT_TXCLK0N H25 H_CLKIN0 <6>
<6> H_CLKOP1 AB23 HT_RXCLK1P HT_TXCLK1P L21 H_CLKIP1 <6>
<6> H_CLKON1 AA22 HT_RXCLK1N HT_TXCLK1N L20 H_CLKIN1 <6>
H_CTLOP0 M22 M24 H_CTLIP0
<6> H_CTLOP0 HT_RXCTL0P HT_TXCTL0P H_CTLIP0 <6>
H_CTLON0 M23 M25 H_CTLIN0
<6> H_CTLON0 HT_RXCTL0N HT_TXCTL0N H_CTLIN0 <6>
H_CTLOP1 R21 P19 H_CTLIP1
<6> H_CTLOP1 HT_RXCTL1P HT_TXCTL1P H_CTLIP1 <6>
H_CTLON1 R20 R18 H_CTLIN1
<6> H_CTLON1 HT_RXCTL1N HT_TXCTL1N H_CTLIN1 <6>
1 R60 2 HT_RXCALP C23 B24 HT_TXCALP 1 R61 2
HT_RXCALN HT_RXCALP HT_TXCALP HT_TXCALN
A24 HT_RXCALN HT_TXCALN B25
301_0402_1%~D 301_0402_1%~D
0718 Place within 1" RS780M_FCBGA528 0718 Place within 1"
layout 1:2 layout 1:2
4 RS880 A11(SA000032710) 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 12 of 55
A B C D E
 A B C D E

+1.8VS +1.8VS +1.8VS

0.1U_0402_16V4Z +1.8VS

2
1 2
R417 R63 U4

5
+1.1VS +NB_PLLVDD @ C684 2.2K_0402_5% NC7SZ08P5X_NL_SC70-5

5
L2 300_0402_5% NB_PWRGD 2

P
B
1 2 2 4NB_PWRGD_R

P
1

1
+3VS B NB_LDTSTOP# Y
1 1 Y 4 <8,27,36> SB_PWRGD 1 A

G
FBMA-L11-160808-221LMT 0603 L3 1
<8,26> LDT_STOP# A

G
C141 C142 1 2 C679 C144 C143 U8 @

3
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z

+AVDD1
1 1 1

3
1 2 2 FBMA-L11-160808-221LMT 0603 NC7SZ08P5X_NL_SC70-5 1

2.2U_0603_6.3V4Z
2
22U_0805_6.3V6M 2 2
1 2
1U_0402_6.3V4Z R64 @ 0_0402_5%
+1.8VS
L4 AMD suggest Check if needed?
+1.8VS +NB_HTPVDD 1 2 +AVDDDI
L5 1

125mA
1 2 FBMA-L11-160808-221LMT 0603
1 1 C145
FBMA-L11-160808-221LMT 0603 0.1U_0402_16V4Z
C146 C147 2 U3C
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z F12 A22 GMCH_TXOUT0+ <23>
2 2 +1.8VS AVDD1(NC) TXOUT_L0P(NC)
20mA E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 GMCH_TXOUT0- <23>
F14 AVDDDI(NC) TXOUT_L1P(NC) A21 GMCH_TXOUT1+ <23>
L6 4mA G15 B21 GMCH_TXOUT1- <23>
+AVDDQ AVSSDI(NC) TXOUT_L1N(NC)
1 2 H15 AVDDQ(NC) TXOUT_L2P(NC) B20 GMCH_TXOUT2+ <23>
1 1 H14 AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A20 GMCH_TXOUT2- <23>
FBMA-L11-160808-221LMT 0603 A19
C148 C149 TXOUT_L3P(NC)
E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19
+1.8VS +VDDA18HTPLL 2.2U_0603_6.3V4Z 1U_0402_6.3V4Z

CRT/TVOUT
F17 Y(DFT_GPIO2)
L7 2 2
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18
1 2 TXOUT_U0N(NC) A18
1 1 GMCH_CRT_R G18 A17
<25> GMCH_CRT_R RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3)
FBMA-L11-160808-221LMT 0603 G17 B17 L8
C150 C151 GMCH_CRT_G REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) +VDDLTP18
<25> GMCH_CRT_G E18 GREEN(DFT_GPIO1) TXOUT_U2P(NC) D20 1 2 +1.8VS
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z F18 D21 1 1
2 2 GMCH_CRT_B GREENb(NC) TXOUT_U2N(NC) FBMA-L11-160808-221LMT 0603
<25> GMCH_CRT_B E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18
F19 D19 C152 C153
BLUEb(NC) TXOUT_U3N(NC) 1U_0402_6.3V4Z 2.2U_0603_6.3V4Z
GMCH_CRT_HSYNC 2 2
<14,25> GMCH_CRT_HSYNC A11 DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) B16 GMCH_TXCLK+ <23>
2 GMCH_CRT_VSYNC 2
<14,25> GMCH_CRT_VSYNC B11 DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) A16 GMCH_TXCLK- <23>
GMCH_CRT_CLK F8 D16
+1.8VS +VDDA18PCIEPLL <25> GMCH_CRT_CLK DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
GMCH_CRT_DATA E8 D17
<25> GMCH_CRT_DATA DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1)
L9
1 2 1 2 DAC_RSET G14 15mA L10
R65 715_0402_1% DAC_RSET(PWM_GPIO1) +VDDLTP18 +VDDLT18
FBMA-L11-160808-221LMT 0603
1 1
+NB_PLLVDD
65mA VDDLTP18(NC) A13 1 2
BLM18AG601SN1D_2P
+1.8VS
+NB_PLLVDD A12 PLLVDD(NC) VSSLTP18(NC) B13 1 1
C154 C155 +NB_HTPVDD +NB_HTPVDD 20mAD14 300mA C156
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z PLLVDD18(NC) +VDDLT18 0.1U_0402_16V4Z C157
B12 A15

LVTM
2 2 PLLVSS(NC) VDDLT18_1(NC) 4.7U_0805_10V4Z
20mA B15

PLL PWR
VDDLT18_2(NC) 2 2
+VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14
120mA VDDLT33_2(NC) B14
+VDDA18PCIEPLL D7 VDDA18PCIEPLL1
E7 VDDA18PCIEPLL2 VSSLT1(VSS) C14
R66 0_0402_5% D15
NB_RESET# VSSLT2(VSS)
<14,26,36> A_RST# 1 2 D8 SYSRESETb VSSLT3(VSS) C16
1 2 NB_PWRGD_R A10 C18
<27> NB_PWRGD POWERGOOD VSSLT4(VSS)
R67 0_0402_5% NB_LDTSTOP# C10 C20
NB_ALLOW_LDTSTOP LDTSTOPb VSSLT5(VSS)
2 1 C12 E20

PM
+1.8VS ALLOW_LDTSTOP VSSLT6(VSS)
R68 300_0402_5% C22
VSSLT7(VSS)
<22> CLK_NBHT C25 HT_REFCLKP
<22> CLK_NB_14.318M 1EXT@ 2 <22> CLK_NBHT# C24 HT_REFCLKN
R536 0_0402_5%
1INT@ 2 NB_REFCLK_P E11
<26> NB_DISP_CLKP REFCLK_P/OSCIN(OSCIN)

CLOCKs
R456 1INT@ 0_0402_5%
2 NB_REFCLK_N F11 E9 GMCH_ENVDD <23>
<26> NB_DISP_CLKN REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP)
R439 0_0402_5% F7
CLK_NBGFX LVDS_BLON(PCE_RCALRP) VARY_ENBKL R71 1 @
+1.1VS 1 2 1 2 <22> CLK_NBGFX T2 GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) G12 2 0_0402_5% GMCH_ENBKL

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
R69 R70 CLK_NBGFX# T1
<22> CLK_NBGFX# GFX_REFCLKN

1
4.7K_0402_5% 4.7K_0402_5% R72 1 VB@ 2 0_0402_5% GMCH_INVT_PWM <23>
EXT@ EXT@ 2 INT@ 1 U1 GPP_REFCLKP
+3VS R504 2 INT@4.7K_0402_5%
1 U2 R76 1 VB@ 2 0_0402_5%
R506 4.7K_0402_5% GPP_REFCLKN
3 If support VB, pop VB@ and reserve R71 3
<22> CLK_SBLINK_BCLK V4

2
R77 GMCH_LCD_CLK GPPSB_REFCLKP(SB_REFCLKP)
1 2 4.7K_0402_5% <22> CLK_SBLINK_BCLK# V3 GPPSB_REFCLKN(SB_REFCLKN) R73 R74 R75
R78 1 2 4.7K_0402_5% GMCH_LCD_DATA <23> GMCH_LCD_CLK
GMCH_LCD_CLK B9 I2C_CLK
GMCH_LCD_DATA
R79 1 2 4.7K_0402_5% GMCH_CRT_CLK
<23,38> GMCH_LCD_DATA A9
B8
I2C_DATA MIS. TMDS_HPD(NC) D9
D10
<38> AUX0N DDC_DATA0/AUX0N(NC) HPD(NC)
A8 DDC_CLK0/AUX0P(NC)
R80 1 2 4.7K_0402_5% GMCH_CRT_DATA B7 D12 1 2 SUS_STAT# <27> To SB
DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) R81 0_0402_5%
1 2 A7 DDC_DATA1/AUX1N(NC)
R173 2 @ 1 4.7K_0402_5% AUX0N R82 2K_0402_5% AE8 SUS_STAT_R# <14>Strap pin
POWER_SEL THERMALDIODE_P
<48> POWER_SEL B10 STRP_DATA THERMALDIODE_N AD8

G11 RSVD TESTMODE D13 1 2

EMI R84
1 2 C8 1.8K_0402_5%
@ R86 @ C158
@C158 R85 150_0402_1% AUX_CAL(NC)
CLK_NB_14.318M 1 2 1 2 RS780M_FCBGA528
100_0402_5% 100P_0402_25V8K +3VS Wire-OR
RS880 POWER_SEL RS880 A11(SA000032710) +3VS 2 1
R106 4.7K_0402_5%

1
HIGH 0.95V
R149

1
+1.8VS D Q41 4.7K_0402_5%
LOW 1.1V GMCH_ENBKL 2 UMA@
1 2 GMCH_CRT_R G

2
1

R87 140_0402_1% S 2N7002_SOT23 ENBKL <36>

3
R90 1 2 GMCH_CRT_G

1
1K_0402_5% R88 150_0402_1% D Q63
R91 0_0402_5% 1 2 GMCH_CRT_B PD on chip side 2
1 2 NB_ALLOW_LDTSTOP R89 150_0402_1% G
<26> ALLOW_LDTSTOP
2

S 2N7002_SOT23

3
1
4 D 4
VGA_ENBKL 2 Q62
<16> VGA_ENBKL
G VGA@
S

3
2N7002_SOT23

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 13 of 55
A B C D E
 A B C D E

1.3A L11 0.1U_0402_16V4Z 1U_0402_6.3V4Z

+1.1VS 2 1 +VDDHT L28
U3F
1 2
FBMA-L11-201209-221LMA30T_0805 1 1 1 1 FBMA-L11-201209-221LMA30T_0805 A25 A2
VSSAHT1 VSSAPCIE1

600mA
L12 D23 PART 6/6 B1
C165 C166 C159 C167 VSSAHT2 VSSAPCIE2
1 2 +1.1VS E22 VSSAHT3 VSSAPCIE3 D3
FBMA-L11-201209-221LMA30T_0805 G22 D5
2 2 2 2 U3E VSSAHT4 VSSAPCIE4
4.7U_0805_10V4Z 0.1U_0402_16V4Z
2.5A +VDDA11PCIE C160
G24 VSSAHT5 VSSAPCIE5 E4
J17 VDDHT_1 VDDPCIE_1 A6 1 2 10U_0805_10V4Z G25 VSSAHT6 VSSAPCIE6 G1
1 C162 1
K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6 1 2 10U_0805_10V4Z H19 VSSAHT7 VSSAPCIE7 G2
L16 VDDHT_3 VDDPCIE_3 C6 J22 VSSAHT8 VSSAPCIE8 G4
L13 1U_0402_6.3V4Z M16 D6 L17 H7
0.1U_0402_16V4Z +VDDHTRX VDDHT_4 VDDPCIE_4 C163 VSSAHT9 VSSAPCIE9
2 1 P16 VDDHT_5 VDDPCIE_5 E6 1 2 4.7U_0805_10V4Z L22 VSSAHT10 VSSAPCIE10 J4
R16 VDDHT_6 VDDPCIE_6 F6 L24 VSSAHT11 VSSAPCIE11 R7
FBMA-L11-201209-221LMA30T_0805 1 1 1 1 T16 G7 C168 1 2 1U_0402_6.3V4Z L25 L1
VDDHT_7 VDDPCIE_7 C171 VSSAHT12 VSSAPCIE12
700mA VDDPCIE_8 H8 1 2 1U_0402_6.3V4Z M20 VSSAHT13 VSSAPCIE13 L2
C164 C169 C170 C161 H18 J9 N22 L4
VDDHTRX_1 VDDPCIE_9 VSSAHT14 VSSAPCIE14
G19 VDDHTRX_2 VDDPCIE_10 K9 1 2 P20 VSSAHT15 VSSAPCIE15 L7
2 2 2 2 C172
F20 VDDHTRX_3 VDDPCIE_11 M9 1 2 0.1U_0402_16V4Z R19 VSSAHT16 VSSAPCIE16 M6
4.7U_0805_10V4Z 0.1U_0402_16V4Z E21 L9 C173 0.1U_0402_16V4Z R22 N4
VDDHTRX_4 VDDPCIE_12 VSSAHT17 VSSAPCIE17
D22 VDDHTRX_5 VDDPCIE_13 P9 R24 VSSAHT18 VSSAPCIE18 P6
B23 VDDHTRX_6 VDDPCIE_14 R9 R25 VSSAHT19 VSSAPCIE19 R1
A23 VDDHTRX_7 VDDPCIE_15 T9 H20 VSSAHT20 VSSAPCIE20 R2
L14 680mA V9 U22 R4
10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX VDDPCIE_16 VSSAHT21 VSSAPCIE21
+1.1VS 2 1 AE25 VDDHTTX_1 VDDPCIE_17 U9 V19 VSSAHT22 VSSAPCIE22 V7

GROUND
AD24 VDDHTTX_2 W22 VSSAHT23 VSSAPCIE23 U4
FBMA-L11-201209-221LMA30T_0805 2 1 1 1 1 1 AC23 K12 W24 V8
@ VDDHTTX_3 VDDC_1 VSSAHT24 VSSAPCIE24
AB22 VDDHTTX_4 VDDC_2 J14 W25 VSSAHT25 VSSAPCIE25 V6
C261 C174 C175 C176 C177 C178 AA21 U16 Y21 W1
VDDHTTX_5 VDDC_3 VSSAHT26 VSSAPCIE26
Y20 VDDHTTX_6 VDDC_4 J11 AD25 VSSAHT27 VSSAPCIE27 W2
1 2 2 2 2 2 +NB_CORE
W19 VDDHTTX_7 VDDC_5 K15 VSSAPCIE28 W4

POWER
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z V18 M12 L12 W7
VDDHTTX_8 VDDC_6 VSS11 VSSAPCIE29
U17 VDDHTTX_9 VDDC_7 L14 10A M14 VSS12 VSSAPCIE30 W8
T17 VDDHTTX_10 VDDC_8 L11 N13 VSS13 VSSAPCIE31 Y6
R17 VDDHTTX_11 VDDC_9 M13 P12 VSS14 VSSAPCIE32 AA4
P17 VDDHTTX_12 VDDC_10 M15 P15 VSS15 VSSAPCIE33 AB5
M17 VDDHTTX_13 VDDC_11 N12 R11 VSS16 VSSAPCIE34 AB1

C189
C191

C182

C187

C193

C194

C180

C188

C183

C195

C184

C196
L15 700mA N14 1 R14 AB7
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE VDDC_12 VSS17 VSSAPCIE35
+1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11 1 1 1 1 1 1 1 1 1 1 1 T12 VSS18 VSSAPCIE36 AC3
FBMA-L11-201209-221LMA30T_0805 P10 P13 + U14 AC4
VDDA18PCIE_2 VDDC_14 VSS19 VSSAPCIE37
1 1 1 1 1 1 K10 VDDA18PCIE_3 VDDC_15 P14 U11 VSS20 VSSAPCIE38 AE1

330U_D2E_2.5VM
10U_0805_10V4Z

10U_0805_10V4Z
2 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M10 VDDA18PCIE_4 VDDC_16 R12 U15 VSS21 VSSAPCIE39 AE4
C181 C179 C192 C185 C190 C186 2 2 2 2 2 2 2 2 2 2 2 2
L10 VDDA18PCIE_5 VDDC_17 R15 V12 VSS22 VSSAPCIE40 AB2
4.7U_0805_10V4Z W9 T11 W11
2 2 2 2 2 2 VDDA18PCIE_6 VDDC_18 VSS23
H9 VDDA18PCIE_7 VDDC_19 T15 W15 VSS24
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T10 U12 AC12 AE14
VDDA18PCIE_8 VDDC_20 VSS25 VSS1
R10 VDDA18PCIE_9 VDDC_21 T14 AA14 VSS26 VSS2 D11
Y9 VDDA18PCIE_10 VDDC_22 J16 Y18 VSS27 VSS3 G8
AA9 VDDA18PCIE_11 23mA AB11 VSS28 VSS4 E14
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10 AB15 VSS29 VSS5 E15
AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11 AB17 VSS30 VSS6 J15
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11 AB19 VSS31 VSS7 J12
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10 AE20 VSS32 VSS8 K14
10mA VDD_MEM5(NC) AB10 AB21 VSS33 VSS9 M11
+1.8VS F9 VDD18_1 VDD_MEM6(NC) AC10 K11 VSS34 VSS10 L15
G9 VDD18_2 60mA RS780M_FCBGA528
AE11 VDD18_MEM1(NC) VDD33_1(NC) H11 +3VS
AD11 VDD18_MEM2(NC) VDD33_2(NC) H12
5mA RS780M_FCBGA528
1 1 RS880 A11(SA000032710)
1
C197 C198 C199
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
RS880 A11(SA000032710) 2 2
2

3 U3D 3
PAR 4 OF 6
Side port and Strap setting AB12
AE16
V11
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
AA18
AA20
AA19
AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
AA12 MEM_A4(NC) MEM_DQ4(NC) V17
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
Debug Mode AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15
AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
<13,25> GMCH_CRT_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO. (VSYNC) AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
R92 3K_0402_5% AD15 AD19
1 : Disable MEM_A9(NC) MEM_DQ9/DVO_D5(NC)

SBD_MEM/DVO_I/F
2 1 AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22
R93 @ 3K_0402_5% 0 : Enable AE13 AC18
MEM_A11(NC) MEM_DQ11/DVO_D7(NC)
AC14 MEM_A12(NC) MEM_DQ12(NC) AB20
Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
MEM_DQ14/DVO_D10(NC) AC22
DFT_GPIO1: LOAD_EEPROM_STRAPS AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
Load EEPROM Strap AE17 MEM_BA1(NC)
Selects Loading of STRAPS from EPROM AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
D1 @ W18
CH751H-40PT_SOD323-2
1 : Bypass the loading of EEPROM straps and use Hardware Default Values MEM_DQS0N/DVO_IDCKN(NC)
W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
2 1 0 : I2C Master can load strap values from EEPROM if connected, or use Y12 AE21
<13> SUS_STAT_R# A_RST# <13,26,36> MEM_CASb(NC) MEM_DQS1N(NC)
default values if not connected AD18 MEM_WEb(NC)
2 1 AB13 MEM_CSb(NC) MEM_DM0(NC) W17
R264 @ 3K_0402_5% AB18 AE19
MEM_CKE(NC) MEM_DM1/DVO_D8(NC)
V14 MEM_ODT(NC) 15mA
IOPLLVDD18(NC) AE23 +1.8VS
V15 MEM_CKP(NC) IOPLLVDD(NC) AE24 +1.1VS
Enable Side Port Memory W14 MEM_CKN(NC) 26mA
Enable Side Port Memory IOPLLVSS(NC) AD23
AE12 MEM_COMPP(NC)
4 RS880: HSYNC# 4
AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18
<13,25> GMCH_CRT_HSYNC 2 1 +3VS 0: Enable Register Readback of strap:
R94 3K_0402_5% RS780M_FCBGA528
@ 1 : Disable NB_CLKCFG:CLK_TOP_SPARE_D[1]
2
R95
1
3K_0402_5% RS880 A11(SA000032710)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 14 of 55
A B C D E
 5 4 3 2 1

PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15]
<12> PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15] <12>
PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15]
<12> PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15] <12>
add for VB support.
U5G R96
10K_0402_5%
1 2
LVDS CONTROL AK27
D
GFX PCIE LANE REVERSAL VARY_BL
DIGON AJ27
R97
VGA_PNL_PWM <23>
VGA_ENVDD <23>
D

1 2
10K_0402_5%
U5A
TXCLK_UP_DPF3P AK35
TXCLK_UN_DPF3N AL36

TXOUT_U0P_DPF2P AJ38
TXOUT_U0N_DPF2N AK37

PCIE_MTX_C_GRX_P15 AA38 Y33 PCIE_GTX_MRX_P15C200 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P15 AH35

PCIE_MTX_C_GRX_N15 Y37 PCIE_RX0P PCIE_TX0P PCIE_GTX_MRX_N15C201 0.1U_0402_16V7K PCIE_GTX_C_MRX_N15 TXOUT_U1P_DPF1P
PCIE_RX0N PCIE_TX0N Y32 1 2 TXOUT_U1N_DPF1N AJ36
VGA@
VGA@ AG38
PCIE_MTX_C_GRX_P14 PCIE_GTX_MRX_P14C202 1 0.1U_0402_16V7K PCIE_GTX_C_MRX_P14 TXOUT_U2P_DPF0P
Y35 PCIE_RX1P PCIE_TX1P W33 2 TXOUT_U2N_DPF0N AH37
PCIE_MTX_C_GRX_N14 W36 W32 PCIE_GTX_MRX_N14C203 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N14
PCIE_RX1N PCIE_TX1N
VGA@ TXOUT_U3P AF35
VGA@ TXOUT_U3N AG36
PCIE_MTX_C_GRX_P13 W38 U33 PCIE_GTX_MRX_P13C204 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P13
PCIE_MTX_C_GRX_N13 PCIE_RX2P PCIE_TX2P PCIE_GTX_MRX_N13C205 0.1U_0402_16V7K PCIE_GTX_C_MRX_N13
V37 PCIE_RX2N PCIE_TX2N U32 1 2
VGA@ LVTMDP
VGA@
PCIE_MTX_C_GRX_P12 V35 U30 PCIE_GTX_MRX_P12C206 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P12 AP34 VGA_TXCLK+
PCIE_RX3P PCIE_TX3P TXCLK_LP_DPE3P VGA_TXCLK+ <23>
PCIE_MTX_C_GRX_N12 U36 U29 PCIE_GTX_MRX_N12C207 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N12 AR34 VGA_TXCLK-
PCIE_RX3N PCIE_TX3N TXCLK_LN_DPE3N VGA_TXCLK- <23>
VGA@
VGA@ AW37 VGA_TXOUT0+
TXOUT_L0P_DPE2P VGA_TXOUT0+ <23>
PCIE_MTX_C_GRX_P11 U38 T33 PCIE_GTX_MRX_P11C208 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P11 AU35 VGA_TXOUT0-
PCIE_RX4P PCIE_TX4P TXOUT_L0N_DPE2N VGA_TXOUT0- <23>
PCIE_MTX_C_GRX_N11 T37 T32 PCIE_GTX_MRX_N11C209 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N11
PCIE_RX4N PCIE_TX4N

PCI EXPRESS INTERFACE

VGA@ AR37 VGA_TXOUT1+
TXOUT_L1P_DPE1P VGA_TXOUT1+ <23>
VGA@ AU39 VGA_TXOUT1-
TXOUT_L1N_DPE1N VGA_TXOUT1- <23>
PCIE_MTX_C_GRX_P10 T35 T30 PCIE_GTX_MRX_P10C210 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P10
C PCIE_MTX_C_GRX_N10 PCIE_RX5P PCIE_TX5P PCIE_GTX_MRX_N10C211 0.1U_0402_16V7K PCIE_GTX_C_MRX_N10 VGA_TXOUT2+ C
R36 PCIE_RX5N PCIE_TX5N T29 1 2 TXOUT_L2P_DPE0P AP35 VGA_TXOUT2+ <23>
VGA@ AR35 VGA_TXOUT2-
TXOUT_L2N_DPE0N VGA_TXOUT2- <23>
VGA@
PCIE_MTX_C_GRX_P9 R38 P33 PCIE_GTX_MRX_P9 C212 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P9 AN36
PCIE_MTX_C_GRX_N9 PCIE_RX6P PCIE_TX6P PCIE_GTX_MRX_N9 C213 0.1U_0402_16V7K PCIE_GTX_C_MRX_N9 TXOUT_L3P
P37 PCIE_RX6N PCIE_TX6N P32 1 2 TXOUT_L3N AP37
VGA@
VGA@
PCIE_MTX_C_GRX_P8 P35 P30 PCIE_GTX_MRX_P8 C214 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P8
PCIE_MTX_C_GRX_N8 PCIE_RX7P PCIE_TX7P PCIE_GTX_MRX_N8 C215 0.1U_0402_16V7K PCIE_GTX_C_MRX_N8
N36 PCIE_RX7N PCIE_TX7N P29 1 2
VGA@ 216-0729002 A12 M96_BGA962
VGA@ MAD@
PCIE_MTX_C_GRX_P7 N38 N33 PCIE_GTX_MRX_P7 C216 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P7
PCIE_MTX_C_GRX_N7 PCIE_RX8P PCIE_TX8P PCIE_GTX_MRX_N7 C217 0.1U_0402_16V7K PCIE_GTX_C_MRX_N7
M37 PCIE_RX8N PCIE_TX8N N32 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P6 M35 N30 PCIE_GTX_MRX_P6 C218 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P6
PCIE_MTX_C_GRX_N6 PCIE_RX9P PCIE_TX9P PCIE_GTX_MRX_N6 C219 0.1U_0402_16V7K PCIE_GTX_C_MRX_N6
L36 PCIE_RX9N PCIE_TX9N N29 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P5 L38 L33 PCIE_GTX_MRX_P5 C220 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P5
PCIE_MTX_C_GRX_N5 PCIE_RX10P PCIE_TX10P PCIE_GTX_MRX_N5 C221 0.1U_0402_16V7K PCIE_GTX_C_MRX_N5
K37 PCIE_RX10N PCIE_TX10N L32 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P4 K35 L30 PCIE_GTX_MRX_P4 C222 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P4 U5 PARK@
PCIE_MTX_C_GRX_N4 PCIE_RX11P PCIE_TX11P PCIE_GTX_MRX_N4 C223 0.1U_0402_16V7K PCIE_GTX_C_MRX_N4
J36 PCIE_RX11N PCIE_TX11N L29 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P3 J38 K33 PCIE_GTX_MRX_P3 C224 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P3
PCIE_MTX_C_GRX_N3 PCIE_RX12P PCIE_TX12P PCIE_GTX_MRX_N3 C225 0.1U_0402_16V7K PCIE_GTX_C_MRX_N3
H37 PCIE_RX12N PCIE_TX12N K32 1 2
VGA@ PARK XT-M2 A11

PCIE_MTX_C_GRX_P2 PCIE_GTX_MRX_P2 C226 1

VGA@
0.1U_0402_16V7K PCIE_GTX_C_MRX_P2
PARK A11 (SA00003MC10)
H35 PCIE_RX13P PCIE_TX13P J33 2
B PCIE_MTX_C_GRX_N2 PCIE_GTX_MRX_N2 C227 0.1U_0402_16V7K PCIE_GTX_C_MRX_N2 B
G36 PCIE_RX13N PCIE_TX13N J32 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P1 G38 K30 PCIE_GTX_MRX_P1 C228 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P1
PCIE_MTX_C_GRX_N1 PCIE_RX14P PCIE_TX14P PCIE_GTX_MRX_N1 C229 0.1U_0402_16V7K PCIE_GTX_C_MRX_N1
F37 PCIE_RX14N PCIE_TX14N K29 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P0 F35 H33 PCIE_GTX_MRX_P0 C230 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P0
PCIE_MTX_C_GRX_N0 PCIE_RX15P PCIE_TX15P PCIE_GTX_MRX_N0 C231 0.1U_0402_16V7K PCIE_GTX_C_MRX_N0
E37 PCIE_RX15N PCIE_TX15N H32 1 2
VGA@
VGA@ +3VSG

CLOCK
<22> CLK_PEG_VGA AB35 PCIE_REFCLKP

1
<22> CLK_PEG_VGA# AA36 PCIE_REFCLKN R491
10K_0402_5%
CALIBRATION D45 RB751V_SOD323 VGA@
For M96, AH16 is NC R98
AJ21 Y30 1 VGA@ 2 1.27K_0402_1%
<26,32,34> PLT_RST# 1 2

2
For Mahatten need PD NC#1 PCIE_CALRP VGA@
AK21 NC#2
2 1 AH16 Y29 R100 1 VGA@ 2 2K_0402_1% +1.0VSG VGA_RST#
R99 VGA@ 10K_0402_5% NC_PWRGOOD PCIE_CALRN

<26> PE_GPIO0 1 2
VGA_RST# AA30 PERSTB D44 RB751V_SOD323

1
SG@
216-0729002 A12 M96_BGA962 R492 Pop for PX verify
MAD@ 2.2K_0402_5%
MAD A12 (SA00003M300) @

2
+3VSG
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/7/14 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 15 of 55
5 4 3 2 1
 5 4 3 2 1

U5B
Strap Name Pin Straps description <all internal PD> Setting
External VGA Thermal Sensor
VIP Device Strap Enable indicates to the software driver
VIP_DEVICE_EN V2SYNC 0: Driver would ignore the value sampled on VHAD_0 during reset 0 AU24 +3VSG
TXCAP_DPA3P VGA_HDMI_TXC+ <24>
1: VHAD_0 to determine whether or not a VIP slave device TXCAM_DPA3N AV23 VGA_HDMI_TXC- <24>
VGA Disable determines TX0P_DPA2P AT25 VGA_HDMI_TXD0+ <24> 1

0.1U_0402_16V4Z
VGA_DIS GPIO9 0: VGA Controller capacity enabled 0 MUTI GFX AR24
DPA TX0M_DPA2N VGA_HDMI_TXD0- <24>
1: The device will not be recognized as the system’s VGA controller C232
AU26 VGA@
TX1P_DPA1P VGA_HDMI_TXD1+ <24> 2
Transmitter Power Saving Enable TX1M_DPA1N AV25 VGA_HDMI_TXD1- <24>
TX_PWRS_ENB GPIO0 0: 50% Tx output swing for mobile mode 1 U6 VGA@
1: full Tx output swing (Default setting for Desktop) AR8 AT27 1 8 VGA_SMB_CK2
DVPCNTL_MVP_0 TX2P_DPA0P VGA_HDMI_TXD2+ <24> VDD SCLK
AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26 VGA_HDMI_TXD2- <24>
PCI Express Transmitter De-emphasis Enable AP8 GPU_THERM_D+ 2 7 VGA_SMB_DA2
DVPCNTL_0 2200P_0402_50V7K D+ SDATA
TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode 1 NC on Park AW8 DVPCNTL_1 TXCBP_DPB3P AR30
1: Tx de-emphasis enabled (Defailt setting for desktop) AR3 AT29 VGA@ 1 2 3 6 2 1 THM_ALERT#
D DVPCNTL_2 TXCBM_DPB3N C233 D- ALERT# R597 D
AR1 DVPCLK
GPIO13,12,11 (config 2,1,0) : memory apertures VRAM_ID0 AU1 AV31 GPU_THERM_D- 4 5 0_0402_5%
VRAM_ID1 DVPDATA_0 TX3P_DPB2P THERM# GND
CONFIG[2] GPIO13 a) If BIOS_ROM_EN = 1, then Config[2:0] defines CONFIG[3:0] AU3 DVPDATA_1 TX3M_DPB2N AU30 VGA@ 1 2 +3VSG
CONFIG[1] GPIO12 VRAM_ID2 AW3 DPB R101 4.7K_0402_5%
the ROM type. 128 MB 000 VRAM_ID3 DVPDATA_2 ADM1032ARMZ-2REEL_MSOP8 VGA@
CONFIG[0] GPIO11 001 AP6 DVPDATA_3 TX4P_DPB1P AR32
b) If BIOS_ROM_EN = 0, then Config[2:0] defines 256 MB 001 * AW5 DVPDATA_4 TX4M_DPB1N AT31
the primary memory aperture size. 64 MB 010 AU5 DVPDATA_5 Address 1001 101X b
AR6 DVPDATA_6 TX5P_DPB0P AT33
BIOS_ROM_EN GPIO22 Enable external BIOS ROM device AW6 DVPDATA_7 TX5M_DPB0N AU32
0: Diable, 1: Enable 0 AU6 DVPDATA_8
AT7 AU14 +3VSG
DVPDATA_9 TXCCP_DPC3P
00: No audio function; 10: Audio for DisplayPort only; AV7 DVPDATA_10 TXCCM_DPC3N AV13
AUD[1] HSYNC 11 AN7 +3VSG
01: Audio for DisplayPort and HDMI if adapter is detected; DVPDATA_11
AUD(0) VSYNC AV9 DVPDATA_12 TX0P_DPC2P AT15
11: Audio for both DisplayPort and HDMI

2
AT9 DVPDATA_13 TX0M_DPC2N AR14
0= Advertises the PCI-E device as 2.5 GT/s capable at power-on AR10 R102 R103
DVPDATA_14 DPC 4.7K_0402_5% 4.7K_0402_5%
BIF_GEN2_EN GPIO2 1= Advertises the PCI-E device as 5.0 GT/s capable at power-on 0 AW10 DVPDATA_15 TX1P_DPC1P AU16

5
5.0 GT/s capability will be controlled by software AU10 AV15 VGA@ VGA@
DVPDATA_16 TX1M_DPC1N
AP10

1
DVPDATA_17 VGA_SMB_CK2 EC_SMB_CK2
H2SYNC Internal use only. THIS PAD HAS AN INTERNAL AV11 DVPDATA_18 TX2P_DPC0P AT17 4 3 EC_SMB_CK2 <8,36>
RESERVED GPIO8 PULL-DOWN AND MUST BE 0 V AT RESET. The AT11 DVPDATA_19 TX2M_DPC0N AR16
GPIO21 AR12 Q5B VGA@
pad may be left unconnected DVPDATA_20

2
NC on Park AW12 AU20 DMN66D0LDW-7_SOT363-6
DVPDATA_21 TXCDP_DPD3P
AU12 DVPDATA_22 TXCDM_DPD3N AT19
AP12 VGA_SMB_DA2 1 6 EC_SMB_DA2
+3VSG DVPDATA_23 EC_SMB_DA2 <8,36>
AT21 VGA@
TX3P_DPD2P Q5A DMN66D0LDW-7_SOT363-6
TX3M_DPD2N AR20
VGA@ R104 1 2 10K_0402_5% VGA_GPIO0
VGA@ R107 1 2 10K_0402_5% VGA_GPIO1 +3VSG DPD
@ R109 1 VGA_GPIO2 TX4P_DPD1P AU22 NC on Park
2 10K_0402_5% TX4M_DPD1N AV21
R105 1 VGA@ 2 4.7K_0402_5%
@ R110 1 2 10K_0402_5% VGA_AC_DET R108 1 VGA@ 2 4.7K_0402_5% I2C AT23
TX5P_DPD0P
TX5M_DPD0N AR22
@ R111 1 2 10K_0402_5% SOUT_GPIO8 VGA_LCD_CLK AK26
<23> VGA_LCD_CLK SCL
VGA_LCD_DAT AJ26 Not share via for other GND
<23> VGA_LCD_DAT SDA
@ R113 1 2 10K_0402_5% SIN_GPIO9
R AD39 VGA_CRT_R <25>
C VGA@ R115 1 2 10K_0402_5% VGA_GPIO11 GENERAL PURPOSE I/O AD37 C
@ R116 10K_0402_5% VGA_GPIO12 VGA_GPIO0 RB
1 2 AH20 GPIO_0
@ R117 1 2 10K_0402_5% VGA_GPIO13 VGA_GPIO1 AH18 AE36
GPIO_1 G VGA_CRT_G <25>
@ R118 1 2 3K_0402_5% ROMSE_GPIO22 VGA_GPIO2 AN16 AD35
@ R119 10K_0402_5% GENERICC GPIO_2 GB
1 2 AH23 GPIO_3_SMBDATA
CH751H-40PT_SOD323-2 AJ23 AF37
GPIO_4_SMBCLK B VGA_CRT_B <25>
ACIN_BUF 1 2 VGA_AC_DET AH17 AE38
D2 @ GPIO_5_AC_BATT DAC1 BB
Location AJ17 GPIO_6
VRAM_ID3 VRAM_ID2 VRAM_ID1 VRAM_ID0 VGA_ENBKL AK17 AC36
<13> VGA_ENBKL GPIO_7_BLON HSYNC VGA_CRT_HSYNC <25>
VRAM SOUT_GPIO8 AJ13 AC38
GPIO_8_ROMSO VSYNC VGA_CRT_VSYNC <25>
<vendor1> <pcs> 64MX16 <vendor2> <size> 2 1 SIN_GPIO9 AH15
R120 VGA@ GPIO_9_ROMSI
Park Samsung O 1 O O AJ16 GPIO_10_ROMSCK
<4 pcs> 10K_0402_5% VGA_GPIO11 AK16 AB34 R122 1 VGA@ 2 499_0402_1% L16
(XT) VGA_GPIO12 GPIO_11 RSET BLM18AG121SN1D_0603
Hynix 1 1 O O AL16 GPIO_12 70mA
<4 pcs> VGA_GPIO13 AM16 AD34 +AVDD 2 1 +1.8VSG
GPIO_13 AVDD

1U_0402_6.3V4Z

0.1U_0402_16V4Z

22U_0805_6.3V6M
AMD 1 1 1 O AM14 AE34 VGA@
<4 pcs> GPU_VID0 GPIO_14_HPD2 AVSSQ
<51> GPU_VID0
T11
AM13 GPIO_15_PWRCNTL_0 +VDD1DI
45mA
Hynix(128MbX16) 1 1 O 1 AK14 GPIO_16_SSIN VDD1DI AC33 1 1 1

C236

C237

C238
<4 pcs> THM_ALERT# AG30 AC34
GPIO_17_THERMAL_INT VSS1DI
AN14 GPIO_18_HPD3
AM17 GPIO_19_CTF
GPU_VID1 2 2 2
<51> GPU_VID1 AL13 GPIO_20_PWRCNTL_1 R2 AC30
Location AJ14 AC31 VGA@ VGA@ VGA@ L17 +3VALW Check If needed?
ROMSE_GPIO22 GPIO_21_BB_EN R2B BLM18AG121SN1D_0603
VRAM_ID3 VRAM_ID2 VRAM_ID1 VRAM_ID0 AK13 GPIO_22_ROMCSB

1U_0402_6.3V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M
VRAM T12 AN13 AD30 2 1 +1.8VSG
GPIO_23_CLKREQB G2

5
Madsion <vandor> <size> 64MX16 TRSTB AM23 AD31 VGA@ U7
T14 JTAG_TRSTB G2B ACIN
Samsung O O O O AN23 2

P
(Pro) JTAG_TDI B ACIN <36,37,42,43>
<8 pcs> TCK AK23 AF30 1 1 1 ACIN_BUF 4
JTAG_TCK B2 Y

C240

C239

C241
Hynix 1 O O O TMS AL24 AF31 1
JTAG_TMS B2B A

G
<8 pcs> T17 AM24 JTAG_TDO @ NC7SZ08P5X_NL_SC70-5
AMD 1 O 1 O AJ19

3
<8 pcs> GENERICA 2 2 2
AK19 GENERICB C AC32
Hynix(128MbX16) 1 O O 1 GENERICC AJ20 AD32 VGA@ VGA@ VGA@ L18
<8 pcs> GENERICC Y BLM18AG121SN1D_0603
AK20 GENERICD COMP AF32 1 2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M
AJ24 2 1 +1.8VSG R127 0_0402_5%
GENERICE_HPD4 DAC2 VGA@ VGA@
AH26 GENERICF
+1.8VSG Park NC pins AH24 AD29 H2SYNC
GENERICG H2SYNC V2SYNC
B V2SYNC AC29 1 1 1 B

C242

C243

C244
1

+3VSG
10K_0402_5%
R123

10K_0402_5%
R124

10K_0402_5%
R125

10K_0402_5%
R126

VGA_HDMI_DET AK24 50mA

<24,27> VGA_HDMI_DET HPD1
AG31 +VDD2DI
VDD2DI 2 2 2
VSS2DI AG32
@ @ @ @ VGA@ VGA@ VGA@ L19 V2SYNC @ R132 1 2 10K_0402_5%
+1.8VSG R133 1 VGA@ 2 499_0402_1% 130mA BLM18AG121SN1D_0603 H2SYNC @ R134 1 2 10K_0402_5%
2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M
VRAM_ID0 AG33 +A2VDD 2 1 +3VSG
VRAM_ID1 R135 A2VDD VGA_CRT_VSYNC
Internal PD 1 VGA@ 2 249_0402_1% 20mA VGA@ Strap VGA@ R136 1 2 10K_0402_5%
VRAM_ID2 AD33 +A2VDDQ VGA_CRT_HSYNC VGA@ R137 1 2 10K_0402_5%
VRAM_ID3 +VGA_VREF AH13 A2VDDQ
PD-Reset 1 2 VGA@ VREFG 1 1 1

C246

C247

C248
C245 0.1U_0402_16V4Z AF33
A2VSSQ
1

1
10K_0402_5%
R128

10K_0402_5%
R129

10K_0402_5%
R130

10K_0402_5%
R131

R140 VGA_HDMI_SCLK VGA@ R138 1 2 10K_0402_5%

+1.8VSG L20 715_0402_1% VGA_HDMI_SDATA VGA@ R139 1 2 10K_0402_5%
BLM18AG121SN1D_0603 2 2 2 VGA_CRT_CLK VGA@ R141 10K_0402_5%
R2SET AA29 1 2 1 2
@ @ @ @ 2 1 +DPLL_PVDD VGA@ VGA@ VGA@ VGA@ VGA_CRT_DATA VGA@ R142 1 2 10K_0402_5%
10U_0603_6.3V6M

VGA@ 1 1 1
2

C249

0.1U_0402_16V4Z
C250

1U_0402_6.3V4Z
C251

VGA_CRT_R VGA@ R143 1 2 150_0402_1%

DDC/AUX AM26 VGA_HDMI_SCLK VGA_CRT_G VGA@ R144 1 2 150_0402_1%
DDC1CLK VGA_HDMI_SCLK <24>
120mA PLL/CLOCK AN26 VGA_HDMI_SDATA HDMI VGA_CRT_B VGA@ R145 1 2 150_0402_1%
2 2 2 DDC1DATA VGA_HDMI_SDATA <24>
AM32 DPLL_PVDD
1VGAOPT@ 2 TRSTB VGA@ VGA@ VGA@ AN32 AM27
R147 10K_0402_5% +1.0VSG L21 DPLL_PVSS AUX1P BLM18AG121SN1D_0603
AUX1N AL27
BLM18AG121SN1D_0603 150mA VGA@ 2 1 +1.8VSG
+3VSG 1VGAOPT@ 2 TMS 2 1 +DPLL_VDDC AN31 AM19 1 1 1 L22 VGA@
DPLL_VDDC DDC2CLK
1U_0402_6.3V4Z

1U_0402_6.3V4Z
C254

0.1U_0402_16V4Z
C255

10U_0603_6.3V6M
C257
R420 10K_0402_5% VGA@ 1 1 1 AL19
DDC2DATA
10U_0603_6.3V6M
C252

0.1U_0402_16V4Z
C253

C256

VGA@
TCK 27MCLK AV33 AN20 VGA@
<22> 27M_NSSC XTALIN AUX2P 2 2 2
XTALOUT AU34 AM20
2 2 2 XTALOUT AUX2N
+3VSG 1VGAOPT@ 2 TESTEN VGA@ VGA@ VGA@ AL30
TESTEN <17> DDCCLK_AUX3P
R421 10K_0402_5% AM30
DDCDATA_AUX3N

DDCCLK_AUX4P AL29
For VGA boot unstable issue GPU_THERM_D+ AF29 DPLUS DDCDATA_AUX4N AM29 NC on Park
GPU_THERM_D- AG29 THERMAL

+1.8VSG L23
DMINUS
DDCCLK_AUX5P AN21 VGA_CRT_CLK
VGA_CRT_CLK <25>
FLASH ROM
AM21 VGA_CRT_DATA CRT
DDCDATA_AUX5N VGA_CRT_DATA <25>
A BLM18AG121SN1D_0603 20mA AK32
VGA@ 2 1 +TSVDD AJ32
TS_FDO
TSVDD DDC6CLK AJ30 A 1-Mbit serial EEPROM is A

XTALOUT 27MCLK VGA@ 1 1 1 AJ33 AJ31

TSVSS DDC6DATA
required on GDDR5 designs
10U_0603_6.3V6M
C258

1U_0402_6.3V4Z
C259

0.1U_0402_16V4Z
C260

1M_0603_5% R148
NC_DDCCLK_AUX7P AK30
2 2 2 NC_DDCDATA_AUX7N AK29 NC on Park DDR3 can be removed
Y1 VGA@ VGA@ VGA@ VGA@
2 1
216-0729002 A12 M96_BGA962
27MHZ_16PF_X5H027000FG1H MAD@
Security Classification Compal Secret Data Compal Electronics, Inc.
C262 C263 2009/7/14 2010/03/12 Title
VGA@ VGA@
Issued Date Deciphered Date
18P_0402_50V8J 18P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 16 of 55
5 4 3 2 1
 5 4 3 2 1

Park only support single channel

memory (channel B only)
U5C U5D

MAA[0..12] MAB[0..12]
MDA[0..63] MAA[0..12] <20> MDB[0..63] MAB[0..12] <21>
D <20> MDA[0..63] <21> MDB[0..63] D
MDA0 C37 G24 MAA0 MDB0 C5 P8 MAB0
MDA1 DQA_0 MAA_0 MAA1 MDB1 DQB_0 MAB_0 MAB1
C35 J23 C3 T9

MEMORY INTERFACE A

MEMORY INTERFACE B
MDA2 DQA_1 MAA_1 MAA2 MDB2 DQB_1 MAB_1 MAB2
A35 DQA_2 MAA_2 H24 E3 DQB_2 MAB_2 P9
MDA3 E34 J24 MAA3 MDB3 E1 N7 MAB3
MDA4 DQA_3 MAA_3 MAA4 MDB4 DQB_3 MAB_3 MAB4
G32 DQA_4 MAA_4 H26 F1 DQB_4 MAB_4 N8
MDA5 D33 J26 MAA5 MDB5 F3 N9 MAB5
MDA6 DQA_5 MAA_5 MAA6 MDB6 DQB_5 MAB_5 MAB6
F32 DQA_6 MAA_6 H21 F5 DQB_6 MAB_6 U9
MDA7 E32 G21 MAA7 MDB7 G4 U8 MAB7
MDA8 DQA_7 MAA_7 MAA8 MDB8 DQB_7 MAB_7 MAB8
D31 DQA_8 MAA_8 H19 H5 DQB_8 MAB_8 Y9
MDA9 F30 H20 MAA9 MDB9 H6 W9 MAB9
MDA10 DQA_9 MAA_9 MAA10 MDB10 DQB_9 MAB_9 MAB10
C30 DQA_10 MAA_10 L13 J4 DQB_10 MAB_10 AC8
MDA11 A30 G16 MAA11 MDB11 K6 AC9 MAB11
MDA12 DQA_11 MAA_11 MAA12 A_BA[0..2] MDB12 DQB_11 MAB_11 MAB12 B_BA[0..2]
F28 DQA_12 MAA_12 J16 A_BA[0..2] <20> K5 DQB_12 MAB_12 AA7 B_BA[0..2] <21>
MDA13 C28 H16 A_BA2 MDB13 L4 AA8 B_BA2
MDA14 DQA_13 MAA_13/BA2 A_BA0 MDB14 DQB_13 MAB_13/BA2 B_BA0
A28 DQA_14 MAA_14/BA0 J17 M6 DQB_14 MAB_14/BA0 Y8
MDA15 E28 H17 A_BA1 MDB15 M1 AA9 B_BA1
MDA16 DQA_15 MAA_15/BA1 DQMA#[0..7] MDB16 DQB_15 MAB_15/BA1 DQMB#[0..7]
D27 DQA_16 DQMA#[0..7] <20> M3 DQB_16 DQMB#[0..7] <21>
MDA17 F26 A32 DQMA#0 MDB17 M5 H3 DQMB#0
MDA18 DQA_17 DQMA_0 DQMA#1 MDB18 DQB_17 DQMB_0 DQMB#1
C26 DQA_18 DQMA_1 C32 N4 DQB_18 DQMB_1 H1
MDA19 A26 D23 DQMA#2 MDB19 P6 T3 DQMB#2
MDA20 DQA_19 DQMA_2 DQMA#3 MDB20 DQB_19 DQMB_2 DQMB#3
F24 DQA_20 DQMA_3 E22 P5 DQB_20 DQMB_3 T5
MDA21 C24 C14 DQMA#4 MDB21 R4 AE4 DQMB#4
MDA22 DQA_21 DQMA_4 DQMA#5 MDB22 DQB_21 DQMB_4 DQMB#5
A24 DQA_22 DQMA_5 A14 T6 DQB_22 DQMB_5 AF5
MDA23 E24 E10 DQMA#6 MDB23 T1 AK6 DQMB#6
MDA24 DQA_23 DQMA_6 DQMA#7 MDB24 DQB_23 DQMB_6 DQMB#7
C22 DQA_24 DQMA_7 D9 U4 DQB_24 DQMB_7 AK5
MDA25 A22 QSA[0..7] MDB25 V6 QSB[0..7]
DQA_25 QSA[0..7] <20> DQB_25 QSB[0..7] <21>
MDA26 F22 C34 QSA0 MDB26 V1 F6 QSB0
MDA27 DQA_26 QSA_0/RDQSA_0 QSA1 MDB27 DQB_26 QSB_0/RDQSB_0 QSB1
D21 DQA_27 QSA_1/RDQSA_1 D29 V3 DQB_27 QSB_1/RDQSB_1 K3
MDA28 A20 D25 QSA2 MDB28 Y6 P3 QSB2
MDA29 DQA_28 QSA_2/RDQSA_2 QSA3 MDB29 DQB_28 QSB_2/RDQSB_2 QSB3
F20 DQA_29 QSA_3/RDQSA_3 E20 Y1 DQB_29 QSB_3/RDQSB_3 V5
MDA30 D19 E16 QSA4 MDB30 Y3 AB5 QSB4
MDA31 DQA_30 QSA_4/RDQSA_4 QSA5 MDB31 DQB_30 QSB_4/RDQSB_4 QSB5
E18 DQA_31 QSA_5/RDQSA_5 E12 Y5 DQB_31 QSB_5/RDQSB_5 AH1
C MDA32 QSA6 MDB32 QSB6 C
C18 DQA_32 QSA_6/RDQSA_6 J10 AA4 DQB_32 QSB_6/RDQSB_6 AJ9
MDA33 A18 D7 QSA7 MDB33 AB6 AM5 QSB7
MDA34 DQA_33 QSA_7/RDQSA_7 QSA#[0..7] MDB34 DQB_33 QSB_7/RDQSB_7 QSB#[0..7]
F18 DQA_34 QSA#[0..7] <20> AB1 DQB_34 QSB#[0..7] <21>
MDA35 D17 A34 QSA#0 MDB35 AB3 G7 QSB#0
MDA36 DQA_35 QSA_0B/WDQSA_0 QSA#1 MDB36 DQB_35 QSB_0B/WDQSB_0 QSB#1
A16 DQA_36 QSA_1B/WDQSA_1 E30 AD6 DQB_36 QSB_1B/WDQSB_1 K1
MDA37 F16 E26 QSA#2 MDB37 AD1 P1 QSB#2
MDA38 DQA_37 QSA_2B/WDQSA_2 QSA#3 MDB38 DQB_37 QSB_2B/WDQSB_2 QSB#3
D15 DQA_38 QSA_3B/WDQSA_3 C20 AD3 DQB_38 QSB_3B/WDQSB_3 W4
MDA39 E14 C16 QSA#4 MDB39 AD5 AC4 QSB#4
MDA40 DQA_39 QSA_4B/WDQSA_4 QSA#5 MDB40 DQB_39 QSB_4B/WDQSB_4 QSB#5
F14 DQA_40 QSA_5B/WDQSA_5 C12 AF1 DQB_40 QSB_5B/WDQSB_5 AH3
MDA41 D13 J11 QSA#6 MDB41 AF3 AJ8 QSB#6
MDA42 DQA_41 QSA_6B/WDQSA_6 QSA#7 +1.5VSG MDB42 DQB_41 QSB_6B/WDQSB_6 QSB#7
F12 DQA_42 QSA_7B/WDQSA_7 F8 AF6 DQB_42 QSB_7B/WDQSB_7 AM3
MDA43 A12 MDB43 AG4
+1.5VSG MDA44 DQA_43 ODTA0 MDB44 DQB_43 ODTB0
D11 DQA_44 ODTA0 J21 ODTA0 <20> AH5 DQB_44 ODTB0 T7 ODTB0 <21>
MDA45 F10 G19 ODTA1 MDB45 AH6 W7 ODTB1
DQA_45 ODTA1 ODTA1 <20> DQB_45 ODTB1 ODTB1 <21>

1
MDA46 A10 MDB46 AJ4
MDA47 DQA_46 CLKA0 R151 MDB47 DQB_46 CLKB0
C10 DQA_47 CLKA0 H27 CLKA0 <20> AK3 DQB_47 CLKB0 L9 CLKB0 <21>
1

MDA48 G13 G27 CLKA0# VGA@ MDB48 AF8 L8 CLKB0#

DQA_48 CLKA0B CLKA0# <20> DQB_48 CLKB0B CLKB0# <21>
R152 MDA49 H13 40.2_0402_1% MDB49 AF9
VGA@ MDA50 DQA_49 CLKA1 MDB50 DQB_49 CLKB1
J13 J14 CLKA1 <20> AG8 AD8 CLKB1 <21>

2
40.2_0402_1% MDA51 DQA_50 CLKA1 CLKA1# MVREFDB MDB51 DQB_50 CLKB1 CLKB1#
H11 DQA_51 CLKA1B H14 CLKA1# <20> AG7 DQB_51 CLKB1B AD7 CLKB1# <21>
MDA52 G10 MDB52 AK9
2

DQA_52 DQB_52

0.1U_0402_16V4Z
MVREFDA MDA53 G8 K23 RASA0# MDB53 AL7 T10 RASB0#
DQA_53 RASA0B RASA0# <20> DQB_53 RASB0B RASB0# <21>
MDA54 K9 K19 RASA1# R153 1 MDB54 AM8 Y10 RASB1#
DQA_54 RASA1B RASA1# <20> DQB_54 RASB1B RASB1# <21>
1

1 MDA55 K10 VGA@ C265 MDB55 AM7

DQA_55 DQB_55
0.1U_0402_16V4Z

R154 C264 MDA56 G9 K20 CASA0# 100_0402_1% MDB56 AK1 W10 CASB0#
DQA_56 CASA0B CASA0# <20> DQB_56 CASB0B CASB0# <21>
VGA@ MDA57 A8 K17 CASA1# VGA@ MDB57 AL4 AA10 CASB1#
CASA1# <20> CASB1# <21>

2
100_0402_1% VGA@ MDA58 DQA_57 CASA1B 2 MDB58 DQB_57 CASB1B
C8 DQA_58 AM6 DQB_58
2 MDA59 CSA0#_0 MDB59 CSB0#_0
E8 K24 CSA0#_0 <20> AM1 P10 CSB0#_0 <21>
2

MDA60 DQA_59 CSA0B_0 MDB60 DQB_59 CSB0B_0

A6 DQA_60 CSA0B_1 K27 AN4 DQB_60 CSB0B_1 L10
MDA61 C6 MDB61 AP3
MDA62 DQA_61 CSA1#_0 MDB62 DQB_61 CSB1#_0
E6 DQA_62 CSA1B_0 M13 CSA1#_0 <20> AP1 DQB_62 CSB1B_0 AD10 CSB1#_0 <21>
MDA63 A5 K16 +1.5VSG MDB63 AP5 AC10
B DQA_63 CSA1B_1 DQB_63 CSB1B_1 B
+1.5VSG MVREFDA L18 K21 CKEA0 U10 CKEB0
+1.5VSG MVREFDA CKEA0 CKEA0 <20> CKEB0 CKEB0 <21>
MVREFSA L20 J20 CKEA1 MVREFDB Y12 AA11 CKEB1
MVREFSA CKEA1 CKEA1 <20> MVREFDB CKEB1 CKEB1 <21>

1
MVREFSB AA12
MVREFSB
1 VGA@ 2 L27 NC_MEM_CALRN0 WEA0B K26 WEA0#
WEA0# <20>
R156
WEB0B N10 WEB0#
WEB0# <21>
1

R155 1 VGA@ 2 240_0402_1% N12 L15 WEA1# VGA@ AB11 WEB1#

NC_MEM_CALRN1 WEA1B WEA1# <20> <16> TESTEN WEB1B WEB1# <21>
R157 R158 1 VGA@ 2 240_0402_1% AG12 40.2_0402_1%
VGA@ R159 240_0402_1% NC_MEM_CALRN2 GCORE_SEN R163
AF28 GCORE_SEN <51>

2
40.2_0402_1% RSVD#1 MVREFSB TESTEN
1 VGA@ 2 M12 MEM_CALRP1 RSVD#2 AG28 1 2 AD28 TESTEN
@ 4.7K_0402_5%
R160 1 VGA@ 2 240_0402_1% M27 AL31 R161 10K_0402_5% R166 VGA@ 1 2 +1.5VSG
2

NC_MEM_CALRP0 RSVD#3
1
MVREFSA R162 1 VGA@ 2 240_0402_1% AH12 1 TEST_MCLK AK10 51.1_0402_1%
NC_MEM_CALRP2 CLKTESTA

0.1U_0402_16V4Z
R164 240_0402_1% H23 R165 C267 TEST_YCLK AL10 AH11 1 2
RSVD#5 MAA13 <20> CLKTESTB DRAM_RST VRAM_RST# <20,21>
1

1 J19 VGA@
RSVD#6
0.1U_0402_16V4Z
C266

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R167 100_0402_1% VGA@

2
VGA@ 2
T8 MAB13 <21> 2 2 1 C270 R168
2

RSVD#9

C268 VGA@

C269 VGA@
100_0402_1% W8 VGA@ VGA@
2 VGA@ RSVD#11
2

216-0729002 A12 M96_BGA962 68P_0402_50V8J 10K_0402_5%

216-0729002 A12 M96_BGA962 1 1 MAD@ 2
M96 no support

1
MAD@

1
If use M96 upper resistor will
change to 100ohm for Modify for ATI suggestion
If use M96 upper resistor will In M97, Medison and Park, AF28 is R169 R170
change to 100ohm for FB_VDDC, AG28 is FB_VDDCI, AH29 is MVREFDA/B and MVREFSA/B VGA@ VGA@

2
MVREFDA/B and MVREFSA/B FB_GND. GCORE_SEN and FB_GND Mahatten upper resistor use 51.1_0402_1% 51.1_0402_1%

Mahatten upper resistor use 40.2ohm should route as differential pair Same 40.2ohm M96 Broadway
as VDDCI_SEN and FB_GND 4.7k Ohm 10k Ohm
R168 SD028470180 SD028100280
M96 use 4.7K to 0 Ohm 680 Ohm
A R166 SD028000080 SD028680080 A
PD directly. 4.7k Ohm
R163 SD028470180 DNI
1000 pF 68 pF
C270 SE074102K80 SE071680J80

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/7/14 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 17 of 55
5 4 3 2 1
 5 4 3 2 1

U5E
+1.5VSG
MEM I/O
1 2900mA

1U_0402_6.3V4Z
C275 VGA@

1U_0402_6.3V4Z
C271 VGA@

1U_0402_6.3V4Z
C276 VGA@

1U_0402_6.3V4Z
C277 VGA@

1U_0402_6.3V4Z
C278 VGA@

1U_0402_6.3V4Z
C279 VGA@

1U_0402_6.3V4Z
C280 VGA@

1U_0402_6.3V4Z
C281 VGA@
PCIE BLM18AG601SN1D_2P
C274 +
1 1 1 1 1 1 1 1
TBD AC7 400mA +PCIE_VDDR
VDDR1#1 PCIE_VDDR#1 AA31 2 1 +1.8VSG
VGA@ AD11 AA32
VDDR1#2 PCIE_VDDR#2

0.1U_0402_16V4Z
C282 VGA@

0.1U_0402_16V4Z
C283 VGA@

1U_0402_6.3V4Z
C284 VGA@

1U_0402_6.3V4Z
C285 VGA@

1U_0402_6.3V4Z
C286 VGA@

1U_0402_6.3V4Z
C287 VGA@

1U_0402_6.3V4Z
C288 VGA@

10U_0805_6.3V6M
C289 VGA@
330U_D2_2V_Y AF7 AA33 1 1 1 1 1 1 1 1 L24 VGA@
2 2 2 2 2 2 2 2 2 VDDR1#3 PCIE_VDDR#3
AG10 VDDR1#4 PCIE_VDDR#4 AA34
AJ7 VDDR1#5 PCIE_VDDR#5 V28
AK8 VDDR1#6 PCIE_VDDR#6 W29
2 2 2 2 2 2 2 2
AL9 VDDR1#7 PCIE_VDDR#7 W30
G11 VDDR1#8 PCIE_VDDR#8 Y31

1U_0402_6.3V4Z
C290VGA@

1U_0402_6.3V4Z
C291VGA@

1U_0402_6.3V4Z
C292VGA@

1U_0402_6.3V4Z
C293VGA@

1U_0402_6.3V4Z
C294VGA@

1U_0402_6.3V4Z
C295VGA@

1U_0402_6.3V4Z
C296VGA@

1U_0402_6.3V4Z
C297VGA@
1 1 1 1 1 1 1 1 G14 VDDR1#9
D D
G17 VDDR1#10 2A
G20 VDDR1#11 PCIE_VDDC#1 G30 +1.0VSG
G23 VDDR1#12 PCIE_VDDC#2 G31
2 2 2 2 2 2 2 2

1U_0402_6.3V4Z
C298 VGA@

1U_0402_6.3V4Z
C299 VGA@

1U_0402_6.3V4Z
C300 VGA@

1U_0402_6.3V4Z
C301 VGA@

1U_0402_6.3V4Z
C272 VGA@

1U_0402_6.3V4Z
C302 VGA@

1U_0402_6.3V4Z
C303 VGA@

10U_0805_6.3V6M
C304 VGA@
G26 VDDR1#13 PCIE_VDDC#3 H29 1 1 1 1 1 1 1 1
G29 VDDR1#14 PCIE_VDDC#4 H30
H10 VDDR1#15 PCIE_VDDC#5 J29
J7 VDDR1#16 PCIE_VDDC#6 J30
2 2 2 2 2 2 2 2
J9 VDDR1#17 PCIE_VDDC#7 L28

10U_0603_6.3V6M
C305 MAD@

10U_0603_6.3V6M
C306 VGA@

10U_0805_6.3V6M
C307 VGA@

10U_0805_6.3V6M
C308 VGA@

10U_0805_6.3V6M
C309 VGA@

1U_0402_6.3V4Z
C273 VGA@

1U_0402_6.3V4Z
C310 VGA@

1U_0402_6.3V4Z
C311 VGA@

1U_0402_6.3V4Z
C312 VGA@
1 1 1 1 1 1 1 1 1 K11 VDDR1#18 PCIE_VDDC#8 M28
K13 VDDR1#19 PCIE_VDDC#9 N28
K8 VDDR1#20 PCIE_VDDC#10 R28
L12 VDDR1#21 PCIE_VDDC#11 T28
2 2 2 2 2 2 2 2 2
L16 VDDR1#22 PCIE_VDDC#12 U28
L21 VDDR1#23
L23 VDDR1#24 34.6A
L26 VDDR1#25 VDDC#1 AA15 +VGA_CORE

1U_0402_6.3V4Z
C316 VGA@

1U_0402_6.3V4Z
C317 VGA@

1U_0402_6.3V4Z
C318 VGA@

1U_0402_6.3V4Z
C319 VGA@

1U_0402_6.3V4Z
C320 VGA@

1U_0402_6.3V4Z
C321 VGA@

1U_0402_6.3V4Z
C322 VGA@

1U_0402_6.3V4Z
C323 VGA@

1U_0402_6.3V4Z
C324 VGA@

1U_0402_6.3V4Z
C325 VGA@
2 1 L7 CORE AA17 1 1 1 1 1 1 1 1 1 1
+1.8VSG VDDR1#26 VDDC#2
L25 VGA@ 1 1 1 M11 AA20
VDDR1#27 VDDC#3

10U_0603_6.3V6M
C313 VGA@

1U_0402_6.3V4Z
C314 VGA@

0.1U_0402_16V4Z
C315 VGA@
BLM18AG121SN1D_0603 N11 AA22
VDDR1#28 VDDC#4
P7 VDDR1#29 VDDC#5 AA24
2 2 2 2 2 2 2 2 2 2
R11 VDDR1#30 VDDC#6 AA27
2 2 2
U11 VDDR1#31 VDDC#7 AB13
U7 VDDR1#32 VDDC#8 AB16
Y11 VDDR1#33 VDDC#9 AB18
Y7 VDDR1#34 VDDC#10 AB21

1U_0402_6.3V4Z
C326 VGA@

1U_0402_6.3V4Z
C327 VGA@

1U_0402_6.3V4Z
C328 VGA@

1U_0402_6.3V4Z
C329 VGA@

1U_0402_6.3V4Z
C330 VGA@

1U_0402_6.3V4Z
C331 VGA@

1U_0402_6.3V4Z
C332 VGA@

1U_0402_6.3V4Z
C333 VGA@

1U_0402_6.3V4Z
C334 VGA@

1U_0402_6.3V4Z
C335 VGA@
VDDC#11 AB23 1 1 1 1 1 1 1 1 1 1
+3VSG 2 1 VDDC#12 AB26
L26 VGA@ 1 1 1 AB28
VDDC#13

10U_0603_6.3V6M
C336 VGA@

1U_0402_6.3V4Z
C337 VGA@

0.1U_0402_16V4Z
C338 VGA@
BLM18AG121SN1D_0603 AC12
LEVEL VDDC#14 2 2 2 2 2 2 2 2 2 2
VDDC#15 AC15
TRANSLATION
2 2 2 136mA VDDC#16 AC17

POWER
+VDD_CT AF26 AC20
C VDD_CT#1 VDDC#17 C
AF27 VDD_CT#2 VDDC#18 AC22

10U_0805_6.3V6M
C341 VGA@

10U_0805_6.3V6M
C342 VGA@

10U_0805_6.3V6M
C343 VGA@

10U_0805_6.3V6M
C344 VGA@

10U_0805_6.3V6M
C345 VGA@

10U_0805_6.3V6M
C346 VGA@

10U_0805_6.3V6M
C339 VGA@
AG26 VDD_CT#3 VDDC#19 AC24 1 1 1 1 1 1 1 1 1 1
AG27 VDD_CT#4 VDDC#20 AC27
L27 VGA@ AD13 +
C340 + C347 + C693
VDDC#21 VGA@ VGA@ @
+1.8VSG 2 1 VDDC#22 AD16
I/O 2 2 2 2 2 2 2 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y
60mA VDDC#23 AD18
2 2 2

10U_0603_6.3V6M
C348 VGA@

1U_0402_6.3V4Z
C349 VGA@

0.1U_0402_16V4Z
C350 VGA@
BLM18AG601SN1D_2P 1 1 1 +VDDR3 AF23 AD21
VDDR3#1 VDDC#24
AF24 VDDR3#2 VDDC#25 AD23
AG23 VDDR3#3 VDDC#26 AD26 Reserve for PWR test
AG24 VDDR3#4 VDDC#27 AF17
2 2 2
VDDC#28 AF20

+VDDR4_5
170mA VDDC#29 AF22
AF13 VDDR5#1 VDDC#30 AG16
AF15 VDDR5#2 VDDC#31 AG18
AG13 VDDR5#3 VDDC#32 AG21
AG15 VDDR5#4 VDDC#33 AH22
VDDC#34 M16
170mA VDDC#35 M18
AD12 VDDR4#1 VDDC#36 M23
AF11 VDDR4#2 VDDC#37 M26
AF12 VDDR4#3 VDDC#38 N15
AG11 VDDR4#4 VDDC#39 N17
VDDC#40 N20
+1.8VSG 2 1 VDDC#41 N22
L31 VGA@ N24 VGA@
BLM18AG121SN1D_0603 MEM CLK VDDC#42
1 1 1 VDDC#43 N27 2 1 +VGA_CORE
10U_0603_6.3V6M
C356 VGA@

1U_0402_6.3V4Z
C357 VGA@

0.1U_0402_16V4Z
C358 VGA@

M20 R13 R569 0_0603_5%

VDDRHA VDDC#44
M21 VSSRHA VDDC#45 R16
2 2 2 VDDC#46 R18 BIF_VDDCI (T27,N27) need
VDDC#47 R21
BLM18AG121SN1D_0603 V12 R23 isolate VGA_CORE
VDDRHB VDDC#48
B
+1.8VSG 2
L32 VGA@
1 U12 VSSRHB VDDC#49 R26 *Confirm with AMD B
VDDC#50 T15
1 1 1 1 1 For M96 only, VDDC#51 T17
10U_0603_6.3V6M
C359 VGA@

1U_0402_6.3V4Z
C360 VGA@

0.1U_0402_16V4Z
C361 VGA@

1U_0402_6.3V4Z
C362 VGA@

0.1U_0402_16V4Z
C363 VGA@

Manhattan are NC pin VDDC#52 T20

VDDC#53 T22
PLL
MPV18 For 2 2 2 2 2 +PCIE_PVDD
68mA VDDC#54 T24
AB37 PCIE_PVDD VDDC#55 T27
Mahattan only U16
VDDC#56
+MPV_18
150mA H7 NC_MPV18#1 VDDC#57 U18 M97 and Mahattan VDDC and
H8 NC_MPV18#2 VDDC#58 U21
U23 VDDCI ball assignments are
VDDC#59
+SPV_18
50mA VDDC#60 U26 different from M96, If M96 is
AM10 NC_SPV18 VDDC#61 V15
V17 populated on this
+SPV10 VDDC#62
+1.0VSG 2
L34 VGA@
1 136mA AN9 SPV10 VDDC#63 V20 design,VDDC and VDDCI
VDDC#64 V22
shoudl be shorted.
10U_0603_6.3V6M
C366 VGA@

1U_0402_6.3V4Z
C364 VGA@

0.1U_0402_16V4Z
C365 VGA@

BLM18AG121SN1D_0603 1 1 1 AN10 V24

SPVSS VDDC#65
VDDC#66 V27
For M96 SPV10=+GPU_CORE VDDC#67 Y16

1U_0402_6.3V4Z
C367 VGA@

1U_0402_6.3V4Z
C368 VGA@

1U_0402_6.3V4Z
C369 VGA@

1U_0402_6.3V4Z
C370 VGA@

1U_0402_6.3V4Z
C371 VGA@

1U_0402_6.3V4Z
C372 VGA@

1U_0402_6.3V4Z
C373 VGA@

1U_0402_6.3V4Z
C374 VGA@

1U_0402_6.3V4Z
C375 VGA@

1U_0402_6.3V4Z
C376 VGA@
BLM18AG121SN1D_0603 Y18 1 1 1 1 1 1 1 1 1 1
2 1
For M97,Nahattan SPV10=+1.0VS 2 2 2 VDDC#68
Y21
+1.8VSG VDDC#69
L35 VGA@ BACK BIAS Y23
VDDC#70
1 1 1 32mA VDDC#71 Y26
2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
C377 VGA@

1U_0402_6.3V4Z
C378 VGA@

0.1U_0402_16V4Z
C379 VGA@

AA13 BBP#1 VDDC#72 Y28

Y13 BBP#2 VDDC#73 AH27
1 1 VDDC#74 AH28
2 2 2
1U_0402_6.3V4Z
C380 VGA@

0.1U_0402_16V4Z
C381 VGA@

5A +VDDCI
M15 2 1 +VGA_CORE
ISOLATED VDDCI#1 N13 FBMA-L11-201209-221LMA30T_0805
2 2 CORE I/O VDDCI#2

10U_0805_6.3V6M
C382 VGA@

10U_0805_6.3V6M
C383 VGA@

10U_0805_6.3V6M
C384 VGA@
R12 1 1 1 L96 VGA@
VDDCI#3
VDDCI#4 T12 2 1
FBMA-L11-201209-221LMA30T_0805
L97 VGA@
A 2 2 2 A
SPV18 For 216-0729002 A12 M96_BGA962
Mahattan only MAD@
Confirm ATI, for
Mahattan, it could be
connected to VGA_CORE

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/7/14 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 18 of 55
5 4 3 2 1
 5 4 3 2 1

L36 VGA@ L37 VGA@

U5F BLM18AG121SN1D_0603 BLM18AG121SN1D_0603
+1.8VSG 2 1 +DPC_VDD18 2 1 +1.8VSG
AB39 PCIE_VSS#1 GND#1 A3 For M96 are NC pins 1 1 1 1 1 1 For M96 are NC pins

10U_0603_6.3V6M
C385 VGA@

0.1U_0402_16V4Z
C386 VGA@

1U_0402_6.3V4Z
C387 VGA@

10U_0603_6.3V6M
C388 VGA@

0.1U_0402_16V4Z
C389 VGA@

1U_0402_6.3V4Z
C390 VGA@
E39 PCIE_VSS#2 GND#2 A37
F34 PCIE_VSS#3 GND#3 AA16
F39 PCIE_VSS#4 GND#4 AA18
2 2 2 2 2 2
G33 PCIE_VSS#5 GND#5 AA2
G34 PCIE_VSS#6 GND#6 AA21
H31 PCIE_VSS#7 GND#7 AA23
H34 PCIE_VSS#8 GND#8 AA26
H39 AA28 L39 VGA@
PCIE_VSS#9 GND#9 BLM18AG121SN1D_0603 L38 VGA@
J31 PCIE_VSS#10 GND#10 AA6
J34 AB12 +1.0VSG 2 1 +DPC_VDD10 BLM18AG121SN1D_0603
D PCIE_VSS#11 GND#11 D
K31 PCIE_VSS#12 GND#12 AB15 2 1 +1.0VSG
K34 PCIE_VSS#13 GND#13 AB17 1 1 1

10U_0603_6.3V6M
C391

0.1U_0402_16V4Z
C392

1U_0402_6.3V4Z
C393

0.1U_0402_16V4Z
C395

1U_0402_6.3V4Z
C396

10U_0603_6.3V6M
C397
K39 PCIE_VSS#14 GND#14 AB20
L31 PCIE_VSS#15 GND#15 AB22 1 1 1
L34 AB24 U5H
PCIE_VSS#16 GND#16 2 2 2
M34 PCIE_VSS#17 GND#17 AB27

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
DP C/D POWER DP A/B POWER
M39 PCIE_VSS#18 GND#18 AC11 130mA 130mA 2 2 2
N31 PCIE_VSS#19 GND#19 AC13
N34 PCIE_VSS#20 GND#20 AC16 AP20 NC_DPC_VDD18#1 NC_DPA_VDD18#1 AN24
P31 AC18 L40 VGA@ AP21 AP24 +DPA_VDD18
PCIE_VSS#21 GND#21 BLM18AG121SN1D_0603 NC_DPC_VDD18#2 NC_DPA_VDD18#2 L41 VGA@
P34 PCIE_VSS#22 GND#22 AC2
P39 AC21 +1.8VSG 2 1 1 1 1 200mA 200mA BLM18AG121SN1D_0603
PCIE_VSS#23 GND#23

10U_0603_6.3V6M

0.1U_0402_16V4Z

1U_0402_6.3V4Z
R34 PCIE_VSS#24 GND#24 AC23 2 1 +1.8VSG

C394 VGA@

C398 VGA@

C399 VGA@
T31 PCIE_VSS#25 GND#25 AC26 For M96 are NC pins AP13 DPC_VDD10#1 DPA_VDD10#1 AP31

0.1U_0402_16V4Z
C400

1U_0402_6.3V4Z
C401

10U_0603_6.3V6M
C402
T34 AC28 AT13 AP32 +DPA_VDD10 For M96 are NC pins
PCIE_VSS#26 GND#26 2 2 2 DPC_VDD10#2 DPA_VDD10#2
T39 PCIE_VSS#27 GND#27 AC6 1 1 1
U31 PCIE_VSS#28 GND#28 AD15
U34 PCIE_VSS#29 GND#29 AD17 AN17 DPC_VSSR#1 DPA_VSSR#1 AN27

VGA@

VGA@

VGA@
V34 PCIE_VSS#30 GND#30 AD20 AP16 DPC_VSSR#2 DPA_VSSR#2 AP27
L42 VGA@ 2 2 2
V39 PCIE_VSS#31 GND#31 AD22 AP17 DPC_VSSR#3 DPA_VSSR#3 AP28
W31 AD24 BLM18AG121SN1D_0603 AW14 AW24
PCIE_VSS#32 GND#32 DPC_VSSR#4 DPA_VSSR#4
W34 PCIE_VSS#33 GND#33 AD27 +1.0VSG 2 1 AW16 DPC_VSSR#5 DPA_VSSR#5 AW26
Y34 AD9 L43 VGA@
PCIE_VSS#34 GND#34 BLM18AG121SN1D_0603
Y39 PCIE_VSS#35 GND#35 AE2 1 1 1

10U_0603_6.3V6M
C403 VGA@

0.1U_0402_16V4Z
C404 VGA@

1U_0402_6.3V4Z
C405 VGA@
GND#36 AE6 130mA 130mA 2 1 +1.0VSG

0.1U_0402_16V4Z
C406

1U_0402_6.3V4Z
C407

10U_0603_6.3V6M
C408
GND#37 AF10 AP22 NC_DPD_VDD18#1 NC_DPB_VDD18#1 AP25
AF16 +DPD_VDD18 AP23 AP26 +DPB_VDD18 1 1 1
GND#38 2 2 2 NC_DPD_VDD18#2 NC_DPB_VDD18#2
GND#39 AF18
AF21 200mA 200mA
GND GND#40

VGA@

VGA@

VGA@
GND#41 AG17
+DPD_VDD10 2 2 2
F15 GND#101 GND#42 AG2 AP14 DPD_VDD10#1 DPB_VDD10#1 AN33
F17 AG20 AP15 AP33 +DPB_VDD10
C GND#102 GND#43 L45 VGA@ DPD_VDD10#2 DPB_VDD10#2 C
F19 GND#103 GND#44 AG22
F21 AG6 BLM18AG121SN1D_0603 L44 VGA@
GND#104 GND#45 BLM18AG121SN1D_0603
F23 GND#105 GND#46 AG9 +1.8VSG 2 1
F25 GND#106 GND#47 AH21 AN19 DPD_VSSR#1 DPB_VSSR#1 AN29 2 1 +1.8VSG

0.1U_0402_16V4Z
C412

1U_0402_6.3V4Z
C413

10U_0603_6.3V6M
C414
F27 AH29 FB_GND 1 1 1 AP18 AP29
GND#107 GND#48 DPD_VSSR#2 DPB_VSSR#2

10U_0603_6.3V6M
C409

0.1U_0402_16V4Z
C410

1U_0402_6.3V4Z
C411
F29 GND#108 GND#49 AJ10 AP19 DPD_VSSR#3 DPB_VSSR#3 AP30 1 1 1
1

F31 AJ11 VGA@ AW20 AW30

GND#109 GND#50 R174 DPD_VSSR#4 DPB_VSSR#4
F33 GND#110 GND#51 AJ2 AW22 DPD_VSSR#5 DPB_VSSR#5 AW32
2 2 2

VGA@

VGA@

VGA@
F7 GND#111 GND#52 AJ28 0_0402_5%
2 2 2

VGA@

VGA@

VGA@
F9 AJ6 R175 R176
GND#112 GND#53 150_0402_1% 150_0402_1%
G2 AK11
2

GND#113 GND#54
G6 GND#114 GND#55 AK31 2 1 AW18 DPCD_CALR DPAB_CALR AW28 1 2
H9 AK7 L46 VGA@
GND#115 GND#56 BLM18AG121SN1D_0603
J2 GND#116 GND#57 AL11 200mA 20mA
J27 GND#117 GND#58 AL14 DP E/F POWER DP PLL POWER 2 1 +1.8VSG

0.1U_0402_16V4Z
C415

1U_0402_6.3V4Z
C416

10U_0603_6.3V6M
C417
J6 AL17 For PX, leave NC when +DPE_VDD18 AH34 AU28 +DPA_PVDD
GND#118 GND#59 DPE_VDD18#1 DPA_PVDD
J8 AL2 AJ34 AV27 1 1 1
K14
GND#119 GND#60
AL20
SBIOS control PWR on/off DPE_VDD18#2 DPA_PVSS
GND#120 GND#61 @ L47 VGA@
K7 GND#121 GND#62 AL21 1 2 120mA 20mA

VGA@

VGA@

VGA@
L11 AL23 R402 0_0402_5% BLM18AG121SN1D_0603
GND#122 GND#63 +DPE_VDD10 +DPB_PVDD 2 2 2
L17 GND#123 GND#64 AL26 +1.0VSG 2 1 AL33 DPE_VDD10#1 DPB_PVDD AV29
L2 GND#124 GND#65 AL32 AM33 DPE_VDD10#2 DPB_PVSS AR28
L22 GND#125 GND#66 AL6 1 1 1
10U_0603_6.3V6M
C418 VGA@

0.1U_0402_16V4Z
C419 VGA@

1U_0402_6.3V4Z
C420 VGA@
L24 AL8 20mA L48 VGA@
GND#126 GND#67 BLM18AG121SN1D_0603
L6 GND#127 GND#68 AM11
M17 AM31 AN34 AU18 +DPC_PVDD 2 1 +1.8VSG
GND#128 GND#69 2 2 2 DPE_VSSR#1 DPC_PVDD

0.1U_0402_16V4Z
C421

1U_0402_6.3V4Z
C422

10U_0603_6.3V6M
C423
M22 GND#129 GND#70 AM9 AP39 DPE_VSSR#2 DPC_PVSS AV17
M24 GND#130 GND#71 AN11 AR39 DPE_VSSR#3 1 1 1
N16 GND#131 GND#72 AN2 Ball AW34 and AW35 AU37 DPE_VSSR#4 20mA
N18 AN30 1 @ 2 AW35
GND#132 GND#73 are GND ball in M96, DPE_VSSR#5

VGA@

VGA@

VGA@
N2 AN6 R177 0_0402_5% AV19 +DPD_PVDD
GND#133 GND#74 DPD_PVDD 2 2 2
N21 GND#134 GND#75 AN8 but have another ball DPD_PVSS AR18
B B
N23 GND#135 GND#76 AP11 name in Broadway, 200mA
N26 GND#136 GND#77 AP7
that is XO_IN and +DPF_VDD18
AF34 DPF_VDD18#1 20mA L49 VGA@
N6 GND#137 GND#78 AP9 AG34 DPF_VDD18#2
R15 AR5 X0_IN2. AM37 +DPE_PVDD BLM18AG121SN1D_0603
GND#138 GND#79 DPE_PVDD
R17 GND#139 GND#80 AW34 DPE_PVSS AN38 2 1 +1.8VSG

0.1U_0402_16V4Z
C424

1U_0402_6.3V4Z
C425

10U_0603_6.3V6M
C426
R2 GND#140 GND#81 B11 120mA
R20 GND#141 GND#82 B13 AK33 DPF_VDD10#1 20mA 1 1 1
1

R22 B15 +DPF_VDD10 AK34

GND#142 GND#83 @ R178 L50 VGA@ DPF_VDD10#2 +DPF_PVDD
R24 GND#143 GND#84 B17 NC_DPF_PVDD AL38

VGA@

VGA@

VGA@
R27 B19 0_0402_5% BLM18AG121SN1D_0603 AM35
GND#144 GND#85 NC_DPF_PVSS 2 2 2
R6 GND#145 GND#86 B21 +1.8VSG 2 1
T11 B23 AF39
2

GND#146 GND#87 DPF_VSSR#1

T13 GND#147 GND#88 B25 1 1 1 AH39 DPF_VSSR#2
10U_0603_6.3V6M
C427 VGA@

0.1U_0402_16V4Z
C428 VGA@

1U_0402_6.3V4Z
C429 VGA@

T16 GND#148 GND#89 B27 AK39 DPF_VSSR#3

T18 B29 AL34 L51 VGA@
GND#149 GND#90 DPF_VSSR#4 BLM18AG121SN1D_0603
T21 GND#150 GND#91 B31 AM34 DPF_VSSR#5
2 2 2
T23 GND#151 GND#92 B33 2 1 +1.8VSG

0.1U_0402_16V4Z
C430

1U_0402_6.3V4Z
C431

10U_0603_6.3V6M
C432
T26 GND#152 GND#93 B7
U15 B9 R179 1 1 1
GND#153 GND#94
U17 GND#154 GND#95 C1 2 1 AM39 DPEF_CALR
U2 C39 L52 VGA@
GND#155 GND#96 BLM18AG121SN1D_0603 150_0402_1%
U20 GND#156 GND#97 E35
2 2 2

VGA@

VGA@

VGA@
U22 E5 +1.0VSG 2 1 216-0729002 A12 M96_BGA962
GND#157 GND#98 MAD@
U24 GND#158 GND#99 F11
U27 GND#159 GND#100 F13 1 1 1
10U_0603_6.3V6M
C433 VGA@

0.1U_0402_16V4Z
C434 VGA@

1U_0402_6.3V4Z
C435 VGA@

U6 GND#160
V11 L53 VGA@
GND#161 BLM18AG121SN1D_0603
V16 GND#162 2 2 2
V18 GND#163 2 1 +1.8VSG

0.1U_0402_16V4Z
C436

1U_0402_6.3V4Z
C437

10U_0603_6.3V6M
C438
V21 GND#164
V23 GND#165 1 1 1 For M96 are NC pins
V26 GND#166
A A
W2 GND#167

VGA@

VGA@

VGA@
W6 GND#168 2 2 2
Y15 GND#169
Y17 GND#170
Y20 GND#171
Y22 GND#172 VSS_MECH#1 A39
Y24 GND#173 VSS_MECH#2 AW1
Y27 AW39
U13
GND#174 VSS_MECH#3 Security Classification Compal Secret Data Compal Electronics, Inc.
GND#175
V13 GND#176 Issued Date 2009/7/14 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
216-0729002 A12 M96_BGA962 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
MAD@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 19 of 55
5 4 3 2 1
 5 4 3 2 1

U9 U10 U11 U12

VREFCA_A1 M8 E3 MDA22 VREFCA_A2 M8 E3 MDA25 VREFCA_A3 M8 E3 MDA35 VREFCA_A4 M8 E3 MDA48

VREFDA_Q1 H1 VREFCA DQL0 MDA19 VREFDA_Q2 VREFCA DQL0 MDA30 VREFDA_Q3 VREFCA DQL0 MDA32 VREFDA_Q4 VREFCA DQL0 MDA51
VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 MDA21 F2 MDA24 F2 MDA38 F2 MDA55
MAA0 DQL2 MDA18 MAA0 DQL2 MDA29 MAA0 DQL2 MDA34 MAA0 DQL2 MDA54
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAA1 P7 H3 MDA23 MAA1 P7 H3 MDA26 MAA1 P7 H3 MDA37 MAA1 P7 H3 MDA50
MAA2 A1 DQL4 MDA16 MAA2 A1 DQL4 MDA31 MAA2 A1 DQL4 MDA36 MAA2 A1 DQL4 MDA52
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAA3 N2 G2 MDA20 MAA3 N2 G2 MDA27 MAA3 N2 G2 MDA39 MAA3 N2 G2 MDA49
MAA4 A3 DQL6 MDA17 MAA4 A3 DQL6 MDA28 MAA4 A3 DQL6 MDA33 MAA4 A3 DQL6 MDA53
P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAA5 P2 MAA5 P2 MAA5 P2 MAA5 P2
MAA6 A5 MAA6 A5 MAA6 A5 MAA6 A5
R8 A6 R8 A6 R8 A6 R8 A6
MAA7 R2 D7 MDA0 MAA7 R2 D7 MDA15 MAA7 R2 D7 MDA43 MAA7 R2 D7 MDA63
MAA8 A7 DQU0 MDA5 MAA8 A7 DQU0 MDA11 MAA8 A7 DQU0 MDA44 MAA8 A7 DQU0 MDA58
T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3
MAA9 R3 C8 MDA1 MAA9 R3 C8 MDA14 MAA9 R3 C8 MDA40 MAA9 R3 C8 MDA60
D MAA10 A9 DQU2 MDA7 MAA10 A9 DQU2 MDA10 MAA10 A9 DQU2 MDA45 MAA10 A9 DQU2 MDA59 D
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
MAA11 R7 A7 MDA3 MAA11 R7 A7 MDA13 MAA11 R7 A7 MDA42 MAA11 R7 A7 MDA61
MAA12 A11 DQU4 MDA4 MAA12 A11 DQU4 MDA9 MAA12 A11 DQU4 MDA46 MAA12 A11 DQU4 MDA56
N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2
MAA13 T3 B8 MDA2 MAA13 T3 B8 MDA12 MAA13 T3 B8 MDA41 MAA13 T3 B8 MDA62
A13 DQU6 MDA6 A13 DQU6 MDA8 A13 DQU6 MDA47 A13 DQU6 MDA57
T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3
M7 A15/BA3 M7 A15/BA3 M7 A15/BA3 M7 A15/BA3
+1.5VSG +1.5VSG +1.5VSG +1.5VSG

M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2

<17> A_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 A_BA1 N8 D9 A_BA1 N8 D9 A_BA1 N8 D9
<17> A_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 A_BA2 M3 G7 A_BA2 M3 G7 A_BA2 M3 G7
<17> A_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
MDA[0..63] N1 N1 N1 N1
<17> MDA[0..63] VDD VDD VDD VDD
CLKA0 J7 N9 CLKA0 J7 N9 CLKA1 J7 N9 CLKA1 J7 N9
CLKA0# CK VDD CLKA0# CK VDD CLKA1# CK VDD CLKA1# CK VDD
K7 CK VDD R1 K7 CK VDD R1 K7 CK VDD R1 K7 CK VDD R1
K9 R9 CKEA0 K9 R9 K9 R9 CKEA1 K9 R9
<17> CKEA0 CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG <17> CKEA1 CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG

ODTA0_1 K1 A1 ODTA0_1 K1 A1 ODTA1_1 K1 A1 ODTA1_1 K1 A1

<17> MAA[13..0] ODT/ODT0 VDDQ ODT/ODT0 VDDQ ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSA0#_0 L2 A8 L2 A8 CSA1#_0 L2 A8
<17> CSA0#_0 CS/CS0 VDDQ CS/CS0 VDDQ <17> CSA1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASA0# J3 C1 J3 C1 RASA1# J3 C1
<17> RASA0# RAS VDDQ RAS VDDQ <17> RASA1# RAS VDDQ RAS VDDQ
K3 C9 CASA0# K3 C9 K3 C9 CASA1# K3 C9
<17> CASA0# CAS VDDQ CAS VDDQ <17> CASA1# CAS VDDQ CAS VDDQ
L3 D2 WEA0# L3 D2 L3 D2 WEA1# L3 D2
<17> WEA0# WE VDDQ WE VDDQ <17> WEA1# WE VDDQ WE VDDQ
<17> DQMA#[7..0] VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA2 F3 H2 QSA3 F3 H2 QSA4 F3 H2 QSA6 F3 H2
QSA0 DQSL VDDQ QSA1 DQSL VDDQ QSA5 DQSL VDDQ QSA7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9

<17> QSA[7..0]
DQMA#2 E7 A9 DQMA#3 E7 A9 DQMA#4 E7 A9 DQMA#6 E7 A9
DQMA#0 DML VSS DQMA#1 DML VSS DQMA#5 DML VSS DQMA#7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
C C
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSA#2 G3 J2 QSA#3 G3 J2 QSA#4 G3 J2 QSA#6 G3 J2
<17> QSA#[7..0] DQSL VSS DQSL VSS DQSL VSS DQSL VSS
QSA#0 B7 J8 QSA#1 B7 J8 QSA#5 B7 J8 QSA#7 B7 J8
DQSU VSS DQSU VSS DQSU VSS DQSU VSS
VSS M1 VSS M1 VSS M1 VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9
<17,21> VRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
VSS T1 VSS T1 VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
R180 VGA@ L1 B9 R181 VGA@ L1 B9 R182 VGA@ L1 B9 R183 VGA@ L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8
E2 E2 E2 E2
2

2
VSSQ VSSQ VSSQ VSSQ
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9

96-BALL 96-BALL 96-BALL 96-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
+1.5VSG X76@ X76@ X76@ X76@
Pull high for Madison and Park... +1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG
+1.5VSG +1.5VSG
ODTA0_1
1

1
R184 R185 R186 R187 R188 R189
VGA@ VGA@ 4.99K_0402_1% VGA@ VGA@ VGA@ VGA@ VGA@ R191 R193
B ODTA0 2 VGA@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% VGA@ VGA@ B
<17> ODTA0 1 1 2
R192 0_0402_5% R190 56_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2

2
VREFCA_A1 VREFDA_Q1 VREFCA_A2 VREFDA_Q2 VREFCA_A3 VREFDA_Q3
VGA@ VGA@ 1 1 1 1 1 1 VREFCA_A4 VREFDA_Q4
1

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
ODTA1 2 1 1 2 1 1
<17> ODTA1

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
R194 0_0402_5% R195 56_0402_1% R196 C439 R197 C440 R198 C441 R199 C442 R200 C443 R201 C444
4.99K_0402_1% VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ R202 C445 R203 C446
ODTA1_1 VGA@ 2 4.99K_0402_1% VGA@ 2 4.99K_0402_1% 2 4.99K_0402_1% VGA@ 2 4.99K_0402_1% VGA@ 2 4.99K_0402_1% VGA@ 2 VGA@ VGA@
4.99K_0402_1% VGA@ 2 4.99K_0402_1% VGA@ 2
2

2
+1.5VSG +1.5VSG +1.5VSG +1.5VSG
1U_0402_6.3V6K
C447 VGA@

1U_0402_6.3V6K
C448 VGA@

1U_0402_6.3V6K
C449 VGA@

1U_0402_6.3V6K
C450 VGA@

1U_0402_6.3V6K
C451 VGA@

1U_0402_6.3V6K
C452 VGA@

1U_0402_6.3V6K
C453 VGA@

1U_0402_6.3V6K
C454 VGA@

1U_0402_6.3V6K
C455 VGA@

1U_0402_6.3V6K
C456 VGA@

1U_0402_6.3V6K
C457

1U_0402_6.3V6K
C458

1U_0402_6.3V6K
C459

1U_0402_6.3V6K
C460

1U_0402_6.3V6K
C461

1U_0402_6.3V6K
C462

1U_0402_6.3V6K
C463

1U_0402_6.3V6K
C464

1U_0402_6.3V6K
C465

1U_0402_6.3V6K
C466
R204 VGA@ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
56_0402_1%
<17> CLKA0 1 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
R205 VGA@
56_0402_1%
<17> CLKA0# 1 2
0.01U_0402_25V7K
C467 VGA@

1
+1.5VSG
+1.5VSG
2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C472 VGA@

C473 VGA@

C474 VGA@

C475 VGA@
R206 VGA@ 1 1 1 1 VRAM P/N :
C468 VGA@

C469 VGA@

C470 VGA@

C471 VGA@

A 56_0402_1% A

<17> CLKA1 1 2 Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)

2 2 2 2
R207 VGA@ 2 2 2 2 Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
56_0402_1%
<17> CLKA1# 1 2
0.01U_0402_25V7K
C476 VGA@

1
Security Classification Compal Secret Data Compal Electronics, Inc.
2 Issued Date 2009/7/14 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 20 of 55
5 4 3 2 1
 5 4 3 2 1

U13 U14 U15 U16

VREFCB_A1 M8 E3 MDB26 VREFCB_A2 M8 E3 MDB22 VREFCB_A3 M8 E3 MDB35 VREFCB_A4 M8 E3 MDB55

VREFDB_Q1 H1 VREFCA DQL0 MDB28 VREFDB_Q2 H1 VREFCA DQL0 MDB20 VREFDB_Q3 H1 VREFCA DQL0 MDB37 VREFDB_Q4 H1 VREFCA DQL0 MDB49
VREFDQ DQL1 F7 VREFDQ DQL1 F7 VREFDQ DQL1 F7 VREFDQ DQL1 F7
F2 MDB27 F2 MDB21 F2 MDB34 F2 MDB52
MAB0 DQL2 MDB31 MAB0 DQL2 MDB18 MAB0 DQL2 MDB39 MAB0 DQL2 MDB50
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAB1 P7 H3 MDB25 MAB1 P7 H3 MDB19 MAB1 P7 H3 MDB33 MAB1 P7 H3 MDB53
MAB2 A1 DQL4 MDB30 MAB2 A1 DQL4 MDB17 MAB2 A1 DQL4 MDB38 MAB2 A1 DQL4 MDB48
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAB3 N2 G2 MDB24 MAB3 N2 G2 MDB23 MAB3 N2 G2 MDB32 MAB3 N2 G2 MDB54
MAB4 A3 DQL6 MDB29 MAB4 A3 DQL6 MDB16 MAB4 A3 DQL6 MDB36 MAB4 A3 DQL6 MDB51
P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAB5 P2 MAB5 P2 MAB5 P2 MAB5 P2
MAB6 A5 MAB6 A5 MAB6 A5 MAB6 A5
R8 A6 R8 A6 R8 A6 R8 A6
MAB7 R2 D7 MDB15 MAB7 R2 D7 MDB1 MAB7 R2 D7 MDB44 MAB7 R2 D7 MDB56
MAB8 A7 DQU0 MDB10 MAB8 A7 DQU0 MDB6 MAB8 A7 DQU0 MDB43 MAB8 A7 DQU0 MDB59
T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3
MAB9 R3 C8 MDB12 MAB9 R3 C8 MDB0 MAB9 R3 C8 MDB47 MAB9 R3 C8 MDB63
D MAB10 A9 DQU2 MDB11 MAB10 A9 DQU2 MDB4 MAB10 A9 DQU2 MDB41 MAB10 A9 DQU2 MDB62 D
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
MAB11 R7 A7 MDB13 MAB11 R7 A7 MDB3 MAB11 R7 A7 MDB45 MAB11 R7 A7 MDB57
MAB12 A11 DQU4 MDB9 MAB12 A11 DQU4 MDB7 MAB12 A11 DQU4 MDB40 MAB12 A11 DQU4 MDB61
N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2
MAB13 T3 B8 MDB14 MAB13 T3 B8 MDB2 MAB13 T3 B8 MDB46 MAB13 T3 B8 MDB58
A13 DQU6 MDB8 A13 DQU6 MDB5 A13 DQU6 MDB42 A13 DQU6 MDB60
T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3
M7 A15/BA3 M7 A15/BA3 M7 A15/BA3 M7 A15/BA3
+1.5VSG +1.5VSG +1.5VSG +1.5VSG

M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2

<17> B_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 B_BA1 N8 D9 B_BA1 N8 D9 B_BA1 N8 D9
<17> B_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7 B_BA2 M3 G7 B_BA2 M3 G7
<17> B_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
MDB[0..63] K8 K8 K8 K8
<17> MDB[0..63] VDD VDD VDD VDD
VDD N1 VDD N1 VDD N1 VDD N1
CLKB0 J7 N9 CLKB0 J7 N9 CLKB1 J7 N9 CLKB1 J7 N9
CLKB0# CK VDD CLKB0# CK VDD CLKB1# CK VDD CLKB1# CK VDD
K7 CK VDD R1 K7 CK VDD R1 K7 CK VDD R1 K7 CK VDD R1
K9 R9 CKEB0 K9 R9 K9 R9 CKEB1 K9 R9
<17> CKEB0 CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG <17> CKEB1 CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG
<17> MAB[13..0]
ODTB0_1 K1 A1 ODTB0_1 K1 A1 ODTB1_1 K1 A1 ODTB1_1 K1 A1
ODT/ODT0 VDDQ CSB0#_0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ CSB1#_0 ODT/ODT0 VDDQ
<17> CSB0#_0 L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 <17> CSB1#_0 L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
J3 C1 RASB0# J3 C1 J3 C1 RASB1# J3 C1
<17> RASB0# RAS VDDQ RAS VDDQ <17> RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
<17> CASB0# CAS VDDQ CAS VDDQ <17> CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
<17> DQMB#[7..0] <17> WEB0# WE VDDQ WE VDDQ <17> WEB1# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSB3 F3 H2 QSB2 F3 H2 QSB4 F3 H2 QSB6 F3 H2
QSB1 DQSL VDDQ QSB0 DQSL VDDQ QSB5 DQSL VDDQ QSB7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
<17> QSB[7..0]
DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9
DQMB#1 DML VSS DQMB#0 DML VSS DQMB#5 DML VSS DQMB#7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
C C
VSS E1 VSS E1 VSS E1 VSS E1
<17> QSB#[7..0] VSS G8 VSS G8 VSS G8 VSS G8
QSB#3 G3 J2 QSB#2 G3 J2 QSB#4 G3 J2 QSB#6 G3 J2
QSB#1 DQSL VSS QSB#0 DQSL VSS QSB#5 DQSL VSS QSB#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 VSS M1 VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9
<17,20> VRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
VSS T1 VSS T1 VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
R208 L1 B9 R209 L1 B9 R210 L1 B9 R211 L1 B9
VGA@ NC/CS1 VSSQ VGA@ NC/CS1 VSSQ VGA@ NC/CS1 VSSQ VGA@ NC/CS1 VSSQ
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1
243_0402_1% L9 D8 243_0402_1% L9 D8 243_0402_1% L9 D8 243_0402_1% L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
2

2
VSSQ VSSQ VSSQ VSSQ
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9

96-BALL 96-BALL 96-BALL 96-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
Pull high for Madison and Park... X76@ X76@ X76@ X76@
+1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG
+1.5VSG +1.5VSG +1.5VSG +1.5VSG
1

1
ODTB0_1

1
R213 R214 R215
R221 VGA@ R212 VGA@ VGA@ VGA@ R216 R217 R218 R219
B VGA@ 56_0402_1% VGA@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% VGA@ VGA@ VGA@ VGA@ B
ODTB0 R220 1 2 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
<17> ODTB0
2

2
0_0402_5% VREFCB_A1 VREFDB_Q1 VREFCB_A2 VREFDB_Q2
R223 VGA@ 1 1 1 1 VREFCB_A3 VREFDB_Q3 VREFCB_A4 VREFDB_Q4
1

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
VGA@ 56_0402_1% 1 1 1 1

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
ODTB1 R222 1 2 C477 R225 C478 R226 C479 R227 C480
<17> ODTB1
0_0402_5% R224 VGA@ VGA@ VGA@ R228 C481 R229 C482 R230 C483 R231 C484
VGA@ VGA@ 2 4.99K_0402_1% VGA@ 2 4.99K_0402_1% VGA@ 2 4.99K_0402_1% VGA@ 2 VGA@ VGA@ VGA@ VGA@
ODTB1_1 4.99K_0402_1% 4.99K_0402_1% VGA@ 2 4.99K_0402_1% VGA@ 2 4.99K_0402_1% VGA@ 2 4.99K_0402_1% VGA@ 2
2

2
R232 VGA@
56_0402_1%
1 2 +1.5VSG +1.5VSG
<17> CLKB0
+1.5VSG +1.5VSG
R233 VGA@
56_0402_1%
1U_0402_6.3V6K
C486 VGA@

1U_0402_6.3V6K
C487 VGA@

1U_0402_6.3V6K
C488 VGA@

1U_0402_6.3V6K
C489 VGA@

1U_0402_6.3V6K
C490 VGA@

1U_0402_6.3V6K
C491 VGA@

1U_0402_6.3V6K
C492 VGA@

1U_0402_6.3V6K
C493 VGA@

1U_0402_6.3V6K
C494 VGA@

1U_0402_6.3V6K
C495 VGA@

<17> CLKB0# 1 2 1 1 1 1 1 1 1 1 1 1
0.01U_0402_25V7K
C485 VGA@

1U_0402_6.3V6K
C496 VGA@

1U_0402_6.3V6K
C497 VGA@

1U_0402_6.3V6K
C498 VGA@

1U_0402_6.3V6K
C499 VGA@

1U_0402_6.3V6K
C500 VGA@

1U_0402_6.3V6K
C501 VGA@

1U_0402_6.3V6K
C502 VGA@

1U_0402_6.3V6K
C503 VGA@

1U_0402_6.3V6K
C504 VGA@

1U_0402_6.3V6K
C505 VGA@
1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2

R234 VGA@
56_0402_1% +1.5VSG
1 2 +1.5VSG
<17> CLKB1
R235 VGA@
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
56_0402_1% 1 1 1 1
C511 VGA@

C512 VGA@

C513 VGA@

C514 VGA@
<17> CLKB1# 1 2 1 1 1 1
0.01U_0402_25V7K
C506 VGA@

10U_0603_6.3V6M
C507 VGA@

10U_0603_6.3V6M
C508 VGA@

10U_0603_6.3V6M
C509 VGA@

10U_0603_6.3V6M
C510 VGA@

A A
1
2 2 2 2
2 2 2 2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/7/14 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 21 of 55
5 4 3 2 1
 5 4 3 2 1

+VDDCLK_IO +3VS_CLK
UMAO@ L54 L55
+1.1VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FBMA-L11-201209-221LMA30T_0805 C515 C516 C517 C518 C519 C520 C521 FBMA-L11-201209-221LMA30T_0805 C522 C523 C524 C525 C526 C527 C528 C529 C530 C531 C532

D EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ 22U_0805_6.3V6M EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ EXT@ 1U_0402_6.3V4Z D
2 2 2 2 2 2 2 2 EXT@ 2 2 2 2 2 2 2 2 2 2 EXT@
22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1U CLOSE PIN 69

EXT@ L56
+3VS 1 2 +3VS_CLKVDDA

FBMA-L11-201209-221LMA30T_0805 +3VS_CLK
1 1 U17
C533 C534

1
22U_0805_6.3V6M 0.1U_0402_16V4Z
EXT@
2 2
EXT@ ICS 9LPRS488 R236
49 VDDA SMBCLK 1 SB_SMCLK0 <10,11,27,34> 8.2K_0402_5%
48 2 EXT@
GNDA SMBDAT SB_SMDAT0 <10,11,27,34>

2
+3VS_CLK 62 41 SRC_SLOW SRC_SLOW
EXT@ VDDREF SB_SRC_SLOW#
66 GNDREF 1 INT@ 2 CPU_HT_CLKP <26>
2 1 R429 1 INT@ 0_0402_5%
2 CPU_HT_CLKN <26>

1
C535 0.1U_0402_16V4Z R430 0_0402_5%
+VDDCLK_IO 12 56 CPUCK 1 EXT@ 2 R237
VDDSRC_IO CPUKG0T_LPRS CLK_CPU_BCLK <8>
18 55 CPUCK# R539 1 EXT@ 0_0402_5%
2 CPU @ 8.2K_0402_5%
VDDSRC_IO CPUKG0C_LPRS CLK_CPU_BCLK# <8>
28 R538 0_0402_5%
VDDATIG_IO
37

2
VDDSB_SRC_IO
53 VDDCPU_IO HTT0T_LPRS / 66 M 60 CLK_NBHT <13>
+3VS_CLK HTT0C_LPRS / 66 M 59 CLK_NBHT# <13> NB HT
C C
+3VS_CLK 3 VDDDOT 1 INT@ 2 NB_HT_CLKP <26>
17 40 R432 1 INT@ 0_0402_5%
2 NB_HT_CLKN <26>
VDDSRC SB_SRC0T_LPRS R431 0_0402_5%
29 VDDATIG SB_SRC0C_LPRS 39
+3VS_CLK
R238 8.2K_0402_5%

R239 8.2K_0402_5%

38 VDDSB_SRC
44 VDDSATA
2

54 VDDCPU SB_SRC1T_LPRS 35
L57 61 34
VDDHTT SB_SRC1C_LPRS
1 2 69 VDD48
BLM18AG601SN1D_2P

2
EXT@ 33 CLK_NBGFX <13>
1

ATIG0T_LPRS R240 R241

ATIG0C_LPRS 32 CLK_NBGFX# <13> NB GFX 8.2K_0402_5% 8.2K_0402_5%
LAN 24 ATIG1 1 EXT@ 2 @ EXT@
<27,32> LAN_CLKREQ# CLKREQ0 # CLK_PEG_VGA <15>
31 ATIG1# R534 1 EXT@ 0_0402_5%
2 CLK_PEG_VGA# <15>

1
ATIG1T_LPRS R535 0_0402_5%
Mini Card1 <27,34> MINI1_CLKREQ# 51 CLKREQ1# ATIG1C_LPRS 30 VGA
1 INT@ 2 VGA_CLKP <26> SEL_SATA
50 R438 1 INT@ 0_0402_5%
2 VGA_CLKN <26>
CLKREQ2# R437 0_0402_5% 27M_SEL
ATIG2T_LPRS 26

2
43 CLKREQ3# ATIG2C_LPRS 25 1 INT@ 2 GPP_CLK1P <26>
R436 1 INT@ 0_0402_5%
2 GPP_CLK1N <26> R242
42 R433 0_0402_5% 8.2K_0402_5%
CLKREQ4# EXT@
SRC0T_LPRS 23 CLK_PCIE_LAN <32>
22 CLK_PCIE_LAN# <32> GLAN

1
SRC0C_LPRS

27M_SEL 63 21
REF2/SEL_27 SRC1T_LPRS CLK_PCIE_MINI1 <34>
1 2 SRC1C_LPRS 20 CLK_PCIE_MINI1# <34> MiniCard_1
R243 90.9_0402_1% SEL_SATA 64
EXT@ REF1/SEL_SATA CLK_XTAL_OUT
1 INT@ 2 GPP_CLK3P <26>
1 2 CLK_14.318M 65 16 R435 1 INT@ 0_0402_5%
2 GPP_CLK3N <26>
<13> CLK_NB_14.318M R244 158_0402_1% REF0/SEL_HTT66 SRC2T_LPRS R434 0_0402_5% CLK_XTAL_IN
SRC2C_LPRS 15
B B

EXT@
71 48MHz_0 SRC3T_LPRS 14 Change Y2 to
SRC3C_LPRS 13
2 1 CLK_48M 70 TXC-SJ100009R00
<27> CLK_48M_USB R246 33_0402_5% 48MHz_1 Y2 EXT@ <20ppm / 20pF>
SRC4T_LPRS 10 CLK_SBLINK_BCLK <13> 2 1

CLK_XTAL_IN SRC4C_LPRS 9 CLK_SBLINK_BCLK# <13> NB A LINK 14.318MHZ_16PF_7A14300083

67 X1
2 2
CLK_XTAL_OUT 68 8 C536 C537
X2 SRC5T_LPRS
SRC5C_LPRS 7
27P_0402_50V8J 27P_0402_50V8J
1 1
EXT@ EXT@
6 GNDDOT SRC6T/SATAT_LPRS 46 CLK_SBSRC_BCLK <26>
11 GNDSRC SRC6C/SATAC_LPRS 45 CLK_SBSRC_BCLK# <26> SB RCLK Routing the trace at least 10mil
19 GNDSRC
27 GNDATIG
36 GNDSB_SRC SRC7T_LPRS/27MHz_SS 5
47 4 CLK_SRC7C 1 EXT@ 2 1VGAOPT@ 2 VGA option solution
GNDSATA SRC7C_LPRS/27MHz_NS 27M_NSSC <16>
52 R540 0_0402_5% R248 0_0402_5% CLK_NB_14.318M
+1.1VS_CLK 58
GNDCPU
GNDHTT
72 GND48 1 INT@ 2 VGA_DBCLK <36> RS780 1.1V 158R/90.0R
73 GNDPAD PD# 57 2 EXT@ 1 +3VS_CLK R245 0_0402_5%
Q50 EXTPW@ Close to CLK_GEN R249 8.2K_0402_5%
+1.1VALW SI2301CDS-T1-GE3_SOT23-3 +VDDCLK_IO
L98 1 * NON SPREAD 27M and SPREAD 27M output
S

SLG8SP626VTR_QFN72_10x10 27M_SEL
D

3 1 1 2
FBMA-L11-201209-221LMA30T_0805 EXT@ 1 INT@ 2 CLK_SBLINK_BCLK 0 differential spread SRC_7 output
2

EXTPW@ R520 0_0402_5%

CLK_SB#
R601 1st (SILEGO) : SA00001Z310 S IC SLG8SP626VTR QFN 72P CLK GEN 1 INT@ CLK_SBLINK_BCLK#
G

CLK_SB 2
2

R519 0_0402_5% 1 single-ended 66MHz HTT output

100K_0402_5% 2nd (ICS) : SA000023H10 S IC ICS9LPRS488CKLFT MLF 72P CLK GEN SEL_HTT66
2

A EXTPW@ A
1 INT@ 2 CLK_SBSRC_BCLK# 0* differential 100MHz HTT output
1

EXTPW@ R497 0_0402_5%

R599 1 INT@ 2 CLK_SBSRC_BCLK 1* NON SPREAD 100M SATA SRC6 output
Q54 470_0603_5% R518 0_0402_5% SEL_SATA
1

R600 EXTPW@ D 0 SPREAD 100M SATA SRC6 output

1 1

2 1 2 * default
<36,42,46> SUSP# D
100K_0402_5% G
S EXTPW@ 1 R263
2 2 SUSP <42,49> Security Classification Compal Secret Data Compal Electronics, Inc.
3

<36,38,42,50> VGA_ON 1 @ R150 2 2N7002_SOT23 G 0_0402_5%

10K_0402_5% 2 Q52 S 2008/10/06 2010/03/12 Title
Issued Date Deciphered Date
3

EXTPW@ R255 2
C847 EXTPW@
1
@ 0_0402_5%
VGA_ON# <42>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
0.1U_0402_16V4Z 2N7002_SOT23 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1 Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 22 of 55
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT LCD/LED PANEL Conn.

JLVDS1
+LCDVDD
1 1 +INVPWR_B+
41 G1 2 2
+3VALW +3VS
42 G2 3 3

1
W=60mils 43 4 +LCDVDD_L 2 @ 1 +LCDVDD
R250 G3 4
44 G4 5 5 +LCDVDD R522 0_0603_5%
300_0603_5% 45 6
G5 6

1
1 46 G6 7 7 +3VS
R251 C538 8 INVT_PWM

2
8 DISPOFF#
100K_0402_5% 9 9
4.7U_0805_10V4Z 10 I2CC_SCL
2 10 I2CC_SDA
11

2
11
12 12 DAC_BRIG <36>

3
D D S
TXOUT0- D
13 13
AO3413_SOT23-3
G
Q11 2 2 1 2 14 TXOUT0+
G R252 1K_0402_5% Q13 14
15 15
S 1
D 16 TXOUT1-

1
2N7002_SOT23 C539 +LCDVDD 16 TXOUT1+
17 17
W=60mils 18 18

1
D Q23 0.047U_0402_16V7K TXOUT2-
19 19
GMCH_ENVDD UMA@ 2 TXOUT2+
<13> GMCH_ENVDD 2
G
<NCQD0 use> 20 20
1 1 21 21
1 R507 2 S 2N7002_SOT23 C540 C541 22 TXCLK-

3
100K_0402_5% 22 TXCLK+
23 23
4.7U_0805_10V4Z 0.1U_0402_16V4Z 24
2 2 24
25 25
26 26
27 R525 2 @ 1 0_0402_5%
27 LOCAL_DIM <36>

1
D
28 28
VGA_ENVDD 2 Q29 29
<15> VGA_ENVDD 29
G VGA@ 30 R524 2 @ 1 0_0402_5%
30 COLOR_ENG_EN <36>
1 R508 2 S 31

3
100K_0402_5% 2N7002_SOT23 31
32 32
33 33
+3VS 34
+LCDVDD 34
35 35
+INVPWR_B+ B+ 36
36

1
37 37 +3VS
L58 2 1 R121 38 USB20_CMOS_N5 R256 2 1 0_0402_5%
38 USB20_N5 <27>
W=40mils FBMA-L11-201209-221LMA30T_0805 D9 @ 39 USB20_CMOS_P5 R257 2 1 0_0402_5%
39 USB20_P5 <27>
CH751H-40PT_SOD323-2 4.7K_0402_5% 1 1 40
L59 2 @ C546 C547 40
1

2
FBMA-L11-201209-221LMA30T_0805 BKOFF# 1 2 DISPOFF# IPEX_20143-040E-20F
<36> BKOFF#
1 1 10U_0805_10V4Z 0.1U_0402_16V4Z CONN@
C544 C545 R172 1 2 2
2 0_0402_5%
C C
680P_0402_50V7K 68P_0402_50V8J R171 1 2 10K_0402_5% D14 @
2 2 USB20_CMOS_N5
6 CH3 CH2 3

@ +3VS 5 Vp Vn 2
DAC_BRIG 1 2 +3VS
C542 220P_0402_50V7K
INVT_PWM 1 2

1
C543 220P_0402_50V7K USB20_CMOS_P54 1
DISPOFF# +3VS C687 SG@ R253 CH4 CH1
1 2
C548 220P_0402_50V7K 0.1U_0402_16V4Z SG@ CM1293-04SO_SOT23-6
1 2 4.7K_0402_5%

2
BUS_SEL

1
U42

1
D

NC
2 4 2 Q61
<38> PE_GPIO2 A Y G SG@

G
NC7SZ14P5X_NL_SC70-5 S

3
SG@ 2N7002_SOT23 +3VS
SEL1 L B1 DIS

3
<BUS> H B2 UMA

1
BUS_SEL# BUS_SEL# <25> SEL2 L B1 DIS R926
0_0603_5%
<DDC> H B2 UMA SG@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
U68
4 +3VS_SWITCH
VCC
VCC 10 1 1 1
B VGA_TXCLK- B
48 0B1 VCC 18
VGA_TXCLK+ 47 27
VGA_TXOUT2- 1B1 VCC SG@ SG@ SG@
43 2B1 VCC 38
VGA_TXOUT2+ 2 2 2
For DIS only 42 50
VGA ONLY VGA_TXOUT1+ 37
3B1
4B1
VCC
VCC 56
EC_INVT_PWM 1 DISO@2 INVT_PWM VGA_TXOUT1- 36 C1152 C1153 C1154
<36> EC_INVT_PWM 5B1
TXCLK- 2 3 VGA_TXCLK- R260 0_0402_5% VGA_TXOUT0+ 32 2 TXCLK-
VGA_TXCLK- <15> 6B1 A0

1
TXCLK+ 1 4 VGA_TXCLK+ VGA_TXOUT0- 31 3 TXCLK+
VGA_TXCLK+ <15> 7B1 A1
DISO@RP2
DISO@RP2 0_0404_4P2R_5% VGA_PNL_PWM 1 @ 2 R319 VGA_LCD_DAT 22 7 TXOUT2-
TXOUT2- VGA_TXOUT2- R261 0_0402_5% VGA_LCD_CLK 8B1 A2 TXOUT2+
2 3 VGA_TXOUT2- <15> 10K_0402_5% 23 9B1 A3 8
TXOUT2+ 1 4 VGA_TXOUT2+ 11 TXOUT1+
VGA_TXOUT2+ <15> A4
DISO@RP4
DISO@RP4 0_0404_4P2R_5% GMCH_INVT_PWM 1 @ 2 12 TXOUT1-

2
TXOUT1+ VGA_TXOUT1+ R262 0_0402_5% A5 TXOUT0+
2 3 VGA_TXOUT1+ <15> A6 14
TXOUT1- 1 4 VGA_TXOUT1- 15 TXOUT0-
VGA_TXOUT1- <15> A7
DISO@RP6
DISO@RP6 0_0404_4P2R_5% GMCH_TXCLK- 46 19 I2CC_SDA
TXOUT0+ VGA_TXOUT0+ GMCH_TXCLK+ 0B2 A8 I2CC_SCL
2 3 45 20
TXOUT0- 1 4 VGA_TXOUT0-
VGA_TXOUT0+ <15>
VGA_TXOUT0- <15>
PX & VB support GMCH_TXOUT2- 41
1B2
2B2
A9
DISO@RP8
DISO@RP8 0_0404_4P2R_5% R533 +5VS C681 SG@ GMCH_TXOUT2+ 40 17 BUS_SEL#
EC_INVT_PWM 0.1U_0402_16V4Z GMCH_TXOUT1+ 3B2 SEL
1 2 35 4B2
I2CC_SCL 0_0402_5% 2 DISO@ 1 R270 VGA_LCD_CLK VGA_LCD_CLK <16> 0_0402_5% 1 2 GMCH_TXOUT1- 34 1
I2CC_SDA 0_0402_5% 2 5B2 GND
1 R272 VGA_LCD_DAT
VGA_LCD_DAT <16>
U33 GMCH_TXOUT0+ 30 6B2 GND 6
DISO@ 1 @ 2 2 8 GMCH_TXOUT0- 29 9
<15> VGA_PNL_PWM 1A VCC 7B2 GND
R532 0_0402_5% 5 3 INVT_PWM_L1 2 INVT_PWM GMCH_LCD_DATA 25 13
UMA ONLY <13> GMCH_INVT_PWM
BUS_SEL# 1
2A
1OE#
1B
2B 6 R316 0_0402_5% GMCH_LCD_CLK 26
8B2
9B2
GND
GND 16
BUS_SEL 7 4 21
TXCLK- RP1 1 GMCH_TXCLK- 2OE# GND BUS_SEL# GND
4 GMCH_TXCLK- <13> Pop for PX verify 54 SEL2 GND 24
TXCLK+ 2 3 GMCH_TXCLK+ SN74CBTD3306CPWR_TSSOP8 <If pop, Remove R260> 28
GMCH_TXCLK+ <13> GND
UMAO@ 0_0404_4P2R_5% SG@ 33
TXOUT2- GMCH_TXOUT2- GND
1 4 GMCH_TXOUT2- <13> 52 NC GND 39
TXOUT2+ 2 3 GMCH_TXOUT2+ L B1 DIS 5 44
GMCH_TXOUT2+ <13> NC GND
UMAO@ RP3 0_0404_4P2R_5% 1OE# 51 49
TXOUT1+ GMCH_TXOUT1+ NC GND
A TXOUT1-
1 4
GMCH_TXOUT1-
GMCH_TXOUT1+ <13> H Z GND 53
A
2 3 GMCH_TXOUT1- <13> 57 Thermal_GND GND 55
UMAO@ RP5 0_0404_4P2R_5% L B1 UMA
TXOUT0+ 1 4 GMCH_TXOUT0+ 2OE# PI3LVD400ZFEX_TQFN56_11X5
GMCH_TXOUT0+ <13>
TXOUT0- 2 3 GMCH_TXOUT0- H Z SG@
GMCH_TXOUT0- <13>
UMAO@ RP7 0_0404_4P2R_5%

I2CC_SCL 0_0402_5% 2 UMAO@1 R269 GMCH_LCD_CLK GMCH_LCD_CLK <13>

I2CC_SDA 0_0402_5% 2 1 R271 GMCH_LCD_DATA
UMAO@
GMCH_LCD_DATA <13,38> Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 23 of 55
5 4 3 2 1
 5 4 3 2 1

+3VSG +3VSG +HDMI_5V_OUT JHDMI1

HDMI_HPD 19 HP_DET
+HDMI_5V_OUT 18 +5V
17 DDC/CEC_GND

2
10K_0402_5%

10K_0402_5%
R276 R277 HDMI_SDATA 16 SDA

2K_0402_5%

2K_0402_5%
R274 R275 HDMI_SCLK 15 SCL

1
D D
14 Reserved
@ @ 13
HDMI_R_CK- CEC
12 20

1
CK- GND

2
G
11 CK_shield GND 21
HDMI_R_CK+ 10 22

2
VGA@ VGA@ HDMI_SCLK HDMI_R_D0- CK+ GND
3 1 9 D0- GND 23
<16> VGA_HDMI_SCLK

D
8 D0_shield
Q16 VGA@ HDMI_R_D0+ 7 D0+

2
G
<5V tolerant> BSH111 1N_SOT23-3 HDMI_R_D1- 6 D1-
5 D1_shield
3 1 HDMI_SDATA HDMI_R_D1+ 4
<16> VGA_HDMI_SDATA HDMI_R_D2- D1+

D
3 D2-
Q17 VGA@ 2
BSH111 1N_SOT23-3 HDMI_R_D2+ D2_shield
1 D2+
2 @ 1 SUYIN_100042MR019S153ZL
R278 0_0402_5% CONN@

2 @ 1 <NAV70 use>
R279 0_0402_5%

Check 5V tolerant

Place closed to JHDMI1

+3VS

2
R280
C 0_0402_5% C
VGA@
+HDMI_5V_OUT

1 1
D3 VGA@ F1 VGA@
W=40mils C
+5VS 2 1+HDMI_5V_OUT_1 1 2 2 1 VGA@ 2 HDMI_HPD
1 B R281 150K_0402_5%
RB491D_SC59-3 1.1A_6VDC_FUSE C549 E VGA@

1
0.1U_0402_16V4Z <16,27> VGA_HDMI_DET VGA_HDMI_DET 2 VGA@ 1 Q18
VGA@ R282 0_0402_5% MMBT3904_NL_SOT23-3 R283

1
2 @ 365K_0402_1%
R284
VGA@

2
10K_0402_5%

2
HDMI_C_CLK- R285 1 VGA@ 2 0_0402_5% HDMI_R_CK-

1 1 2 2
L60
WCM2012F2SF-900T04_0805
@ 4 4 3
3
<16> VGA_HDMI_TXD2-
C550 VGA@2 1 0.1U_0402_16V7K HDMI_C_TX2-R286 1 2VGA@ 499_0402_1%
C551 VGA@2 1 0.1U_0402_16V7K HDMI_C_TX2+R287 1 2VGA@ 499_0402_1% HDMI_C_CLK+ R288 1 2 0_0402_5% HDMI_R_CK+
B <16> VGA_HDMI_TXD2+ B
VGA@
<16> VGA_HDMI_TXD1-
C552 VGA@2 1 0.1U_0402_16V7K HDMI_C_TX1-R289 1 2VGA@ 499_0402_1%
C553 VGA@2 1 0.1U_0402_16V7K HDMI_C_TX1+R290 1 2VGA@ 499_0402_1% HDMI_C_TX0- R291 1 VGA@ 2 0_0402_5% HDMI_R_D0-
<16> VGA_HDMI_TXD1+
C554 VGA@2 1 0.1U_0402_16V7K HDMI_C_TX0-R292 1 2VGA@ 499_0402_1% 1 1 2
<16> VGA_HDMI_TXD0- 2
C555 VGA@2 1 0.1U_0402_16V7K HDMI_C_TX0+R293 1 2VGA@ 499_0402_1% L61
<16> VGA_HDMI_TXD0+
WCM2012F2SF-900T04_0805
C556 VGA@2 1 0.1U_0402_16V7K HDMI_C_CLK-R294 1 2VGA@ 499_0402_1% @ 4 4 3
<16> VGA_HDMI_TXC- 3
<16> VGA_HDMI_TXC+
C557 VGA@2 1 0.1U_0402_16V7K HDMI_C_CLK+R295 1 2VGA@ 499_0402_1%
HDMI_C_TX0+ R296 1 2 0_0402_5% HDMI_R_D0+
1

D VGA@
2N7002_SOT23
+HDMI_5V_OUT 2
G Q19 HDMI_C_TX1- R297 1 VGA@ 2 0_0402_5% HDMI_R_D1-
1

S VGA@
3

R298 1 1 2
VGA@ L62 2
100K_0402_5% WCM2012F2SF-900T04_0805
@ 4 4 3
2

3
Place closed to JHDMI1 HDMI_C_TX1+ R299 1 2 0_0402_5% HDMI_R_D1+
VGA@

HDMI_C_TX2- R300 1 VGA@ 2 0_0402_5% HDMI_R_D2-

1 1 2 2
L63
WCM2012F2SF-900T04_0805
@ 4 4 3
3
HDMI_C_TX2+ R301 1 2 0_0402_5% HDMI_R_D2+
VGA@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 24 of 55
5 4 3 2 1
 A B C D E

CRT Connector W=40mils

+5VS +R_CRT_VCC +CRT_VCC

2
D7 F2 W=40mils
2 1 1 2

RB491D_SC59-3 1.1A_6VDC_FUSE
1
D4 D5
PJDLC05C_SOT23-3 PJDLC05C_SOT23-3 C558
@ @ 0.1U_0402_16V4Z
2

1
1 1

CRT_R 2 1 CRT_R_1 L64 1 2 FCM2012CF-800T06_2P CRT_R_2 JCRT1

R407 0_0402_5% 6
11
CRT_G 2 1 CRT_G_1 L65 1 2 FCM2012CF-800T06_2P CRT_G_2 1
R408 0_0402_5% 7
12
CRT_B 2 1 CRT_B_1 L66 1 2 FCM2012CF-800T06_2P CRT_B_2 2
R409 0_0402_5% 8 <NAL00 use>
13

1
1 1 1 1 1 1 3
R305 R307 R308 C559 C560 C561 C562 C563 C564 9
14 G 16
150_0402_1% 4 17
2 2 2 2 2 2 G
10

2
140_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 15
10P_0402_50V8J 1 5
150_0402_1% 10P_0402_50V8J C565
C-H_13-12201513CP
100P_0402_50V8J CONN@
2
+CRT_VCC
CRT_DET# <27>
L67 1 2 CRT_HSYNC_2
C569 1 2 0.1U_0402_16V4Z R312 2 1 10K_0402_5% FCM2012CF-800T06_2P DSUB_12

2
L68 1 2 CRT_VSYNC_2 1 R311

1
U18 FCM2012CF-800T06_2P 1 1 100K_0402_5%

OE#
CRT_HSYNC 2 4 CRT_HSYNC_1 C566 C567 DSUB_15

1
A Y 10P_0402_50V8J 10P_0402_50V8J C568 2
2 G 2 2 68P_0402_50V8J 1 2
74AHCT1G125GW_SOT353-5
3

C570 +CRT_VCC
+CRT_VCC 68P_0402_50V8J
2
C571 1 2 0.1U_0402_16V4Z

1
U19

OE#
CRT_VSYNC 2 4 CRT_VSYNC_1
A Y

G
74AHCT1G125GW_SOT353-5

+3VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 U69 Close to Conn side
C1155 C1156 C1157 C1158 4 1 CRT_R
3 SG@ SG@ SG@ SG@ VDD A0 CRT_G +CRT_VCC 3
16 VDD A1 2
CRT_B
For UMA Only 2 2 2 2
23
29
VDD A2 5
6 CRT_HSYNC
GMCH_CRT_R R266 2 UMAO@ 1 0_0402_5% CRT_R 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDD A3 CRT_VSYNC +3VS
<13> GMCH_CRT_R 32 VDD A4 7

GMCH_CRT_G R83 2 UMAO@ 1 0_0402_5% CRT_G VGA_CRT_R 27 8

<13> GMCH_CRT_G 0B1 SEL1 BUS_SEL# <23>

1
VGA_CRT_G 25
GMCH_CRT_B R268 2 UMAO@ 1 0_0402_5% CRT_B VGA_CRT_B 1B1 R317 R318
<13> GMCH_CRT_B 22 2B1
VGA_CRT_HSYNC 20 9 CRT_CLK 4.7K_0402_5% 4.7K_0402_5%
GMCH_CRT_HSYNC R273 2 UMAO@ 1 0_0402_5% CRT_HSYNC VGA_CRT_VSYNC 3B1 A5 CRT_DATA
<13,14> GMCH_CRT_HSYNC 18 4B1 A6 10
VGA_CRT_CLK 12

2
5B1

2
GMCH_CRT_VSYNC R267 2 UMAO@ 1 0_0402_5% CRT_VSYNC VGA_CRT_DATA BUS_SEL#

G
<13,14> GMCH_CRT_VSYNC 14 6B1 SEL2 30

GMCH_CRT_DATA R410 2 UMAO@ 1 0_0402_5% CRT_DATA DSUB_12 1 3 CRT_DATA

<13> GMCH_CRT_DATA
GMCH_CRT_R 26

S
GMCH_CRT_CLK R406 2 UMAO@ 1 0_0402_5% CRT_CLK GMCH_CRT_G 0B2 Q53
<13> GMCH_CRT_CLK 24 1B2

2
GMCH_CRT_B BSH111 1N_SOT23-3

G
21 2B2 GND 3
GMCH_CRT_HSYNC 19 11
GMCH_CRT_VSYNC 3B2 GND DSUB_15 CRT_CLK
17 4B2 GND 28 1 3
GMCH_CRT_CLK
For VGA Only 13 31

S
GMCH_CRT_DATA 5B2 GND Q65
15 6B2 GPAD 33
VGA_CRT_R R306 2 DISO@ 1 0_0402_5% CRT_R BSH111 1N_SOT23-3
<16> VGA_CRT_R
PI3V712-AZLEX_TQFN32_6X3~D
VGA_CRT_G R302 2 DISO@ 1 0_0402_5% CRT_G SG@ 2 @ 1
<16> VGA_CRT_G
R321 0_0402_5%
VGA_CRT_B R304 2 DISO@ 1 0_0402_5% CRT_B
<16> VGA_CRT_B
SEL1 L B1 DIS
VGA_CRT_HSYNC R303 2 DISO@ 1 0_0402_5% CRT_HSYNC 2 @ 1
<16> VGA_CRT_HSYNC
<BUS> H B2 UMA R323 0_0402_5%
VGA_CRT_VSYNC R309 2 DISO@ 1 0_0402_5% CRT_VSYNC
<16> VGA_CRT_VSYNC
SEL2 L B1 DIS
VGA_CRT_DATA R411 2 DISO@ 1 0_0402_5% CRT_DATA Check 5V tolerant for DISO state
4 <16> VGA_CRT_DATA 4
<DDC> H B2 UMA
<16> VGA_CRT_CLK VGA_CRT_CLK R412 2 DISO@ 1 0_0402_5% CRT_CLK

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 25 of 55
A B C D E
 A B C D E

C572 1 2 150P_0402_50V8J U20A

R325 33_0402_5% P1
SB800 Part 1 of 5
W2
A_RST# T4 PAD PCIE_RST# PCICLK0
<13,14,36> A_RST# 2 1 L1 A_RST# PCICLK1/GPO36 W1 PCI_CLK1 <30>

PCI CLKS
PCICLK2/GPO37 W3 PCI_CLK2 <30>
C579 1 2 0.1U_0402_16V7K SB_RX0P_C AD26 W4 PCI_CLK3 <30>
<12> SB_RX0P A_TX0P PCICLK3/GPO38
C573 1 2 0.1U_0402_16V7K SB_RX0N_C AD27 Y1 PCI_CLK4 <30>
<12> SB_RX0N A_TX0N PCICLK4/14M_OSC/GPO39
C574 1 2 0.1U_0402_16V7K SB_RX1P_C AC28
<12> SB_RX1P A_TX1P
C575 1 2 0.1U_0402_16V7K SB_RX1N_C AC29 V2
<12> SB_RX1N A_TX1N PCIRST#
C576 1 2 0.1U_0402_16V7K SB_RX2P_C AB29
<12> SB_RX2P A_TX2P
C580 1 2 0.1U_0402_16V7K SB_RX2N_C AB28
<12> SB_RX2N A_TX2N
C577 1 2 0.1U_0402_16V7K SB_RX3P_C AB26 AA1
<12> SB_RX3P A_TX3P AD0/GPIO0
C578 1 2 0.1U_0402_16V7K SB_RX3N_C AB27 AA4
1 <12> SB_RX3N A_TX3N AD1/GPIO1 1
AD2/GPIO2 AA3
<12> SB_TX0P AE24 A_RX0P AD3/GPIO3 AB1
<12> SB_TX0N AE23 A_RX0N AD4/GPIO4 AA5
<12> SB_TX1P AD25 AB2 SG@

PCI EXPRESS INTERFACES

A_RX1P AD5/GPIO5
<12> SB_TX1N AD24 A_RX1N AD6/GPIO6 AB6 1 2 INT_VGA_EN# <38>
AC24 AB5 R320 0_0402_5% +3VALW
<12> SB_TX2P A_RX2P AD7/GPIO7
<12> SB_TX2N AC25 AA6 C581
A_RX2N AD8/GPIO8
<12> SB_TX3P AB25 A_RX3P AD9/GPIO9 AC2 1 2
<12> SB_TX3N AB24 A_RX3N AD10/GPIO10 AC3 AMD suggest add GPIO control gate 0.1U_0402_16V4Z
AD11/GPIO11 AC4
R326 2 1 590_0402_1% AD29 AC1 <27> SB_GPIO_A_RST# 1 2
PCIE_CALRP AD12/GPIO12

5
+1.1VS_PCIE R327 2 1 2K_0402_1% AD28 AD1 R427 @ 0_0402_5% U21
PCIE_CALRN AD13/GPIO13
AD2 1 2 2

P
AD14/GPIO14 R425 0_0402_5% B PLT_RST#
AA28 GPP_TX0P AD15/GPIO15 AC6 Y 4 PLT_RST# <15,32,34>
AA29 AE2 A_RST# 1
GPP_TX0N AD16/GPIO16 A

G
Y29 AE1 NC7SZ08P5X_NL_SC70-5
GPP_TX1P AD17/GPIO17

1
Y28 AF8

3
GPP_TX1N AD18/GPIO18 R328
Y26 GPP_TX2P AD19/GPIO19 AE3
Y27 AF1 8.2K_0402_5%
+3VS GPP_TX2N AD20/GPIO20 @
W28 GPP_TX3P AD21/GPIO21 AG1
+1.5VS W29 AF2

2
GPP_TX3N AD22/GPIO22 PCI_AD23
AD23/GPIO23 AE9 PCI_AD23 <30>
2

AA22 AD9 PCI_AD24 <28,30> PCI_AD24

R329 GPP_RX0P AD24/GPIO24 PCI_AD25
PCI_AD24 : VDDR Voltage SW
Y21 GPP_RX0N AD25/GPIO25 AC11 PCI_AD25 <30>
4.7K_0402_5% AA25 AF6 PCI_AD26 PCI_AD26 <30>
GPP_RX1P AD26/GPIO26
2
G

AA24 AF4 PCI_AD27 PCI_AD27 <30>

GPP_RX1N AD27/GPIO27 PCI_AD28
W23 AF3 PCI_AD28 <30>
1

H_PWRGD GPP_RX2P AD28/GPIO28 PCI_AD29

3 1 H_PWRGD_L <52> V24 GPP_RX2N AD29/GPIO29 AH2 PCI_AD29 <30>
S

W24 GPP_RX3P AD30/GPIO30 AG2

Q21 W25 AH3
FDV301N_NL_SOT23-3 GPP_RX3N AD31/GPIO31
CBE0# AA8

PCI INTERFACE
CBE1# AD5
2 2
CBE2# AD8
level shift to ISL6265 CBE3# AA10
FRAME# AE8
DEVSEL# AB9
ISL6265 PWROK input, TTL level: 0.8V~2.0V <22> CLK_SBSRC_BCLK M23 PCIE_RCLKP/NB_LNK_CLKP IRDY# AJ3
<22> CLK_SBSRC_BCLK# P23 PCIE_RCLKN/NB_LNK_CLKN TRDY# AE7
When this pin is high, the SVI interface is PAR AC5
<13> NB_DISP_CLKP U29 NB_DISP_CLKP STOP# AF5
active and I2C protocol is running. While this <13> NB_DISP_CLKN U28 AE6
NB_DISP_CLKN PERR#
pin is low, the SVC, SVD, and VFIXEN input SERR# AE4
SG@
<22> NB_HT_CLKP T26 NB_HT_CLKP REQ0# AE11
states determine the pre-PWROK metal VID or <22> NB_HT_CLKN T27 AH5 1 2 PX_EN# <38>
NB_HT_CLKN REQ1#/GPIO40 R322 0_0402_5%
VFIX mode voltage. This pin must be low prior REQ2#/CLK_REQ8#/GPIO41 AH4 Power Xpress Support
<22> CPU_HT_CLKP V21 CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42 AC12
to the ISL6265 PGOOD output going high <22> CPU_HT_CLKN T21 CPU_HT_CLKN GNT0# AD12 PE_GPIO0 VGA RESET, H: Enable
AJ5 SG@
GNT1#/GPO44
<22> VGA_CLKP V23 SLT_GFX_CLKP GNT2#/GPO45 AH6 1
R259
2
0_0402_5%
PE_GPIO1 <38,42> PE_GPIO1 VGA PWR Enable, H: Enable
<22> VGA_CLKN T23 SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46 AB12
CLKRUN# AB11 PE_GPIO2 MODE Switch, H: VGA , L: NB
L29 GPP_CLK0P LOCK# AD7
L28 GPP_CLK0N
INTE#/GPIO32 AJ6
<22> GPP_CLK1P N29 GPP_CLK1P INTF#/GPIO33 AG6
LAN N28 AG4 SG@
<22> GPP_CLK1N GPP_CLK1N INTG#/GPIO34
INTH#/GPIO35 AJ4 1 2 PE_GPIO0 <15>
M29 R258 0_0402_5%
GPP_CLK2P
M28 GPP_CLK2N
T25
CLOCK GENERATOR
<22> GPP_CLK3P GPP_CLK3P
MINI1 V25 H24 LPCCLK0 1 2 LPC_CLK0_EC
<22> GPP_CLK3N GPP_CLK3N LPCCLK0 LPC_CLK0_EC <30,36>
H25 R330 22_0402_5% LPC_CLK1 <30>
LPCCLK1
L24 GPP_CLK4P LAD0 J27 LPC_AD0 <36>
3 3
L23 GPP_CLK4N LAD1 J26 LPC_AD1 <36>
LPC LAD2 H29 LPC_AD2 <36>
P25 GPP_CLK5P LAD3 H28 LPC_AD3 <36>
M25 GPP_CLK5N LFRAME# G28 LPC_FRAME# <36>
LDRQ0# J25
P29 GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 AA18
1 2 25M_CLK_X1 P28 AB19
GPP_CLK6N SERIRQ/GPIO48 SERIRQ <36>
C689
1

27P_0402_50V8J N26
R426 GPP_CLK7P
N27 GPP_CLK7N
Y6 1M_0603_5% G21
ALLOW_LDTSTP/DMA_ACTIVE# ALLOW_LDTSTOP <13>
25MHZ_20PF_7A25000012 T29 H21 H_PROCHOT_R# <8>
2

GPP_CLK8P PROCHOT#
T28 GPP_CLK8N LDT_PG K19 H_PWRGD <8>
CPU

1 2 25M_CLK_X2 G22 LDT_STOP# <8,13>

C688 LDT_STP#
LDT_RST# J24 LDT_RST# <8>
27P_0402_50V8J L25 14M_25M_48M_OSC +RTCBATT
AMD suggest add Crystal for Internal CLK GEN C1 SB_32KHI
32K_X1
25M_CLK_X1 L26 C2 SB_32KHO
25M_X1 32K_X2

1
D2 R331
RTC

RTCCLK PAD T21

INTRUDER_ALERT# B2 1K_0402_5%
25M_CLK_X2 L27 B1
25M_X2 VDDBT_RTC_G +RTCVCC

2
@ R332 20M_0402_5%
@R332
D8
1 2 SB820M_FCBGA605
1 2 3
R333 510_0402_5%
C582 SB820 A12(SA00003IW10)

0.1U_0402_16V4Z
C584 1 1 C585 W=20mils 1

2
0.1U_0402_16V4Z

1 2 SB_32KHI 1U_0402_6.3V4Z 1
R334 C583 2
4 18P_0402_50V8J Y3 @ 4
1

2 2 0_0603_5%
1 OSC NC 2 for Clear CMOS 2 BAS40-04_SOT23-3
R335 Close to SB

1
20M_0603_5% 4 3
OSC NC +CHGRTC
32.768KHZ_12.5PF_Q13MC14610002
C586
2

SB_32KHO
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
18P_0402_50V8J 2008/10/06 2010/03/12 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 26 of 55
A B C D E
 A B C D E

+3VALW +3VALW

2
@ @
R336 R413 1 2 C587 1 2 100P_0402_25V8K
100K_0402_5% 100K_0402_5% R337 100_0402_5%
SG@ U20D
<36> EC_SWI# J2 A10 CLK_48M_USB <22>

1
CRT_DET VGA_HDMI_DET# PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC
K1 RI#/GEVENT22#
CRT_DET D3 G19 USB_RCOMP 1 2
SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP

1
D D 11.8K_0402_1% R338
<36> PM_SLP_S3# F1 SLP_S3#
<25> CRT_DET# 2 <16,24> VGA_HDMI_DET 2 <36> PM_SLP_S5# H1 SLP_S5#

ACPI / WAKE UP EVENTS

G Q22 G Q64 F2
<36> PBTN_OUT# PWR_BTN#
SG@

USB 1.1 USB MISC

3 S S <8,13,36> SB_PWRGD H5 SB800

3
1 2N7002_SOT23 2N7002_SOT23 SUS_STAT# PWR_GOOD 1
<13> SUS_STAT# G6 SUS_STAT# USB_FSD1P/GPIO186 J10
HPD for PX T24 PAD B3 TEST0 Part 4 of 5 USB_FSD1N H11
0 -> DGPU T22 PAD C4 TEST1/TMS OHCI4
T23 PAD F6 H9 USB20_P14
1 -> IGPU TEST2 USB_FSD0P/GPIO185 USB20_P14 <35>
AD21 J8 USB20_N14 BT
<36> EC_GA20 GA20IN/GEVENT0# USB_FSD0N USB20_N14 <35>
<36> EC_KBRST# AE21 KBRST#/GEVENT1#
<36> EC_SCI# K2 LPC_PME#/GEVENT3# USB_HSD13P B12
<36> EC_SMI# J29 LPC_SMI#/GEVENT23# USB_HSD13N A12
H2 GEVENT5#
J1 SYS_RESET#/GEVENT19# USB_HSD12P F11
<32,34> SB_PCIE_WAKE# H6 WAKE#/GEVENT8# USB_HSD12N E11 EHCI13 / OHCI3
F3 IR_RX1/GEVENT20#
H_THERMTRIP# J6 E14
<8> H_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD11P
NB_PWRGD AC19 E12
<13> NB_PWRGD NB_PWRGD USB_HSD11N
EC_RSMRST# G1 J12
<36> EC_RSMRST# RSMRST# USB_HSD10P
USB_HSD10N J14
8L_6L_UMA AD19
R516 1 INT@ CLK_REQ4#/SATA_IS0#/GPIO64
<22,34> MINI1_CLKREQ# 2 0_0402_5% AA16 CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD9P A13 USB20_P9
USB20_P9 <35>
+3VS SB_GPIO_A_RST# AB21 B13 USB20_N9 WWAN
<26> SB_GPIO_A_RST# SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD9N USB20_N9 <35>
SKU_ID AC18
MUXLESS_SEL CLK_REQ0#/SATA_IS3#/GPIO60 USB20_P8
AF20 SATA_IS4#/FANOUT3/GPIO55 USB_HSD8P D13 USB20_P8 <34>
R340 1 VGA@ 2 2.2K_0402_5% SKU_ID SKU ID: 1-> VGA * PX_FN AE19 C13 USB20_N8 Mini1-WLAN
0-> UMA SATA_IS5#/FANIN3/GPIO59 USB_HSD8N USB20_N8 <34>
<39> SB_SPKR AF19 SPKR/GPIO66 EHCI2 / OHCI2
R341 1 2 100K_0402_5% <10,11,22,34> SB_SMCLK0 SB_SMCLK0 AD22 G12 USB20_P7
SCL0/GPIO43 USB_HSD7P USB20_P7 <35>

USB 2.0
<10,11,22,34> SB_SMDAT0 SB_SMDAT0 AE22 G14 USB20_N7 For China WWAN Port7 and Port9 is disable for
SDA0/GPIO47 USB_HSD7N USB20_N7 <35>
Pop for PX verify SB_SMCLK1 F5
R416 1 SG@ PX_FN PX Function: 1-> PX Enable SB_SMDAT1 SCL1/GPIO227 USB20_P6
2009 AMD platform
2 2.2K_0402_5% Cinfigure to output or F4 SDA1/GPIO228 USB_HSD6P G16 USB20_P6 <35>
0-> PX Disable * Internal PU/PD VB_EN AH21 G18 USB20_N6 CardReader
CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N USB20_N6 <35>
2 1 R517 1 INT@ 2 0_0402_5% AB18
<22,32> LAN_CLKREQ# CLK_REQ1#/FANOUT4/GPIO61
R370 100K_0402_5% E1 D16 USB20_P5

GPIO
IR_LED#/LLB#/GPIO184 USB_HSD5P USB20_P5 <23>
AJ21 C16 USB20_N5 Camera
2 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD5N USB20_N5 <23> 2
R418 1 VB@ 2 2.2K_0402_5% VB_EN VB Function: 1-> VB Enable H4
0-> VB Disable * DDR3_RST#/GEVENT7#
D5 GBE_LED0/GPIO183 USB_HSD4P B14
2 1 D7 GBE_LED1/GEVENT9# USB_HSD4N A14
R588 100K_0402_5% G5 GBE_LED2/GEVENT10#
K3 GBE_STAT0/GEVENT11# USB_HSD3P E18
R515 1 @ 2 2.2K_0402_5% 8L_6L_UMA UMA 8L/6L SEL: 1-> 6L UMA AA20 E16
0-> 8L UMA CLK_REQG#/GPIO65/OSCIN USB_HSD3N
EHCI1 / OHCI1
2 1 J16 USB20_P2
USB_HSD2P USB20_P2 <35>
R593 100K_0402_5% H3 J18 USB20_N2 Ext USB3 <Wake Up support>
BLINK/USB_OC7#/GEVENT18# USB_HSD2N USB20_N2 <35>
EC_LID_OUT# D1
<36> EC_LID_OUT# USB_OC6#/IR_TX1/GEVENT6#
R521 1 @ 2 2.2K_0402_5% MUXLESS_SEL MUXLESS SEL: 1->PX with Muxless E4 B17 USB20_P1
USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P USB20_P1 <35>

USB OC
0->PX with Mux VGA_HDMI_DET# D4 A17 USB20_N1 Ext USB2
USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N USB20_N1 <35>
2 1 E8 USB_OC3#/AC_PRES/TDO/GEVENT15#
R612 100K_0402_5% USB_OC#2 F7 A16 USB20_P0
<35> USB_OC#2 USB_OC2#/TCK/GEVENT14# USB_HSD0P USB20_P0 <35>
USB_OC#1 E7 B16 USB20_N0 Ext USB1
<35> USB_OC#1 USB_OC1#/TDI/GEVENT13# USB_HSD0N USB20_N0 <35>
USB_OC#0 F8
<35> USB_OC#0 USB_OC0#/TRST#/GEVENT12#
R345 1 2 33_0402_5%
<39> HDA_BITCLK_AUDIO

<30> HDA_SDOUT
HDA_BITCLK M3 D25 Check SW:
R346 1 HDA_SDOUT AZ_BITCLK SCL2/GPIO193
<39> HDA_SDOUT_AUDIO 2 33_0402_5% N1 AZ_SDOUT SDA2/GPIO194 F23 Cinfigure to output or Internal PU/PD
HDA_SDIN0 L2 B26 Check SW:
<39> HDA_SDIN0 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 SB_SIC <8>
HDA_SDIN1 M2 E26 Cinfigure to output or Internal PU/PD

HD AUDIO
AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 SB_SID <8>
M1 AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197 F25
M4 AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198 E22
R347 1 2 33_0402_5% HDA_SYNC N2 F22
<39> HDA_SYNC_AUDIO AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199 GPIO199 <30>
R348 1
P2 AZ_RST# EC_PWM3/EC_TIMER3/GPIO200 E21 GPIO200 <30> STRAP PIN
<39> HDA_RST_AUDIO# 2 33_0402_5% HDA_RST#
KSI_0/GPIO201 G24
GBE_COL T1 G25
GBE_CRS GBE_COL KSI_1/GPIO202
T4 GBE_CRS KSI_2/GPIO203 E28
L6 GBE_MDCK KSI_3/GPIO204 E29
3 GBE_MDIO 3
L5 GBE_MDIO KSI_4/GPIO205 D29
T9 GBE_RXCLK KSI_5/GPIO206 D28
U1 GBE_RXD3 KSI_6/GPIO207 C29
U3 GBE_RXD2 KSI_7/GPIO208 C28
T2 GBE_RXD1

GBE LAN
U2 GBE_RXD0 KSO_0/GPIO209 B28
T5 GBE_RXCTL/RXDV KSO_1/GPIO210 A27
+3VS

EMBEDDED CTRL
GBE_RXERR V5 B27
EC_RSMRST# GBE_RXERR KSO_2/GPIO211
1 2 P5 GBE_TXCLK KSO_3/GPIO212 D26
R339 2.2K_0402_5% M5 A26
@ HDA_BITCLK R342 1 GBE_TXD3 KSO_4/GPIO213
1 2 2 2.2K_0402_5% SB_SMCLK0 P9 GBE_TXD2 KSO_5/GPIO214 C26
R349 10K_0402_5% T7 A24
@ HDA_SDIN0 R343 1 GBE_TXD1 KSO_6/GPIO215
1 2 2 2.2K_0402_5% SB_SMDAT0 P7 GBE_TXD0 KSO_7/GPIO216 B25
R350 10K_0402_5% M7 A25
@ HDA_SDIN1 R344 1 GBE_TXCTL/TXEN KSO_8/GPIO217
1 2 2 4.7K_0402_5% SUS_STAT# P4 GBE_PHY_PD KSO_9/GPIO218 D24
R351 10K_0402_5% M9 B24
GBE_PHY_INTR GBE_PHY_RST# KSO_10/GPIO219
V7 GBE_PHY_INTR KSO_11/GPIO220 C24
KSO_12/GPIO221 B23
E23 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222 A23
E24 PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223 D22
EMBEDDED CTRL

F21 SPI_CS2#/GBE_STAT2/GPIO166 KSO_15/GPIO224 C22

G29 FC_RST#/GPO160 KSO_16/GPIO225 A22
KSO_17/GPIO226 B22
+3VALW D27
+3VALW PS2KB_DAT/GPIO189
F28 PS2KB_CLK/GPIO190
F29 PS2M_DAT/GPIO191
1 2 GBE_MDIO E27
R352 10K_0402_5% PS2M_CLK/GPIO192
1 2 SB_PCIE_WAKE# 1 2 GBE_PHY_INTR
R355 10K_0402_5% R358 10K_0402_5% SB820M_FCBGA605
1 @ 2 EC_LID_OUT#
R357 100K_0402_5% 1 2 GBE_COL
4
1 2 SB_SIC R353 10K_0402_5% SB820 A12(SA00003IW10) 4
R359 2.2K_0402_5% 1 2 GBE_CRS
1 2 SB_SID R354 10K_0402_5%
R360 2.2K_0402_5% 1 2 GBE_RXERR
1 2 H_THERMTRIP# R356 10K_0402_5%
R361 10K_0402_5%
1 2 SB_SMCLK1
R362 2.2K_0402_5% AMD recommend PD 10K
1 2 SB_SMDAT1 Security Classification Compal Secret Data Compal Electronics, Inc.
R363 2.2K_0402_5% 2008/10/06 2010/03/12 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 27 of 55
A B C D E
 A B C D E

U20B

AH9
SB800 AH28
1 <31> SATA_STX_DRX_P0 SATA_TX0P FC_CLK 1
<31> SATA_STX_DRX_N0 AJ9 SATA_TX0N Part 2 of 5 FC_FBCLKOUT AG28
HDD AJ8
FC_FBCLKIN AF26
<31> SATA_DTX_C_SRX_N0 SATA_RX0N
<31> SATA_DTX_C_SRX_P0 AH8 SATA_RX0P FC_OE#/GPIOD145 AF28
FC_AVD#/GPIOD146 AG29
<31> SATA_STX_DRX_P1 AH10 SATA_TX1P FC_WE#/GPIOD148 AG26
<31> SATA_STX_DRX_N1 AJ10 SATA_TX1N FC_CE1#/GPIOD149 AF27
ODD AG10
FC_CE2#/GPIOD150 AE29
AF29
<31> SATA_DTX_C_SRX_N1 SATA_RX1N FC_INT1/GPIOD144
<31> SATA_DTX_C_SRX_P1 AF10 SATA_RX1P FC_INT2/GPIOD147 AH27

AG12 SATA_TX2P FC_ADQ0/GPIOD128 AJ27

AF12 SATA_TX2N FC_ADQ1/GPIOD129 AJ26
FC_ADQ2/GPIOD130 AH25
AJ12 SATA_RX2N FC_ADQ3/GPIOD131 AH24
AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23
FC_ADQ5/GPIOD133 AH23
AH14 SATA_TX3P FC_ADQ6/GPIOD134 AJ22
AJ14 SATA_TX3N FC_ADQ7/GPIOD135 AG21
FC_ADQ8/GPIOD136 AF21
AG14 SATA_RX3N FC_ADQ9/GPIOD137 AH22
AF14 AJ23

FLASH
SATA_RX3P FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139 AF23
AG17 SATA_TX4P FC_ADQ12/GPIOD140 AJ24
AF17 SATA_TX4N FC_ADQ13/GPIOD141 AJ25
FC_ADQ14/GPIOD142 AG25
AJ17 SATA_RX4N FC_ADQ15/GPIOD143 AH26
AH17

SERIAL ATA
SATA_RX4P
AJ18 SATA_TX5P
AH18 SATA_TX5N FANOUT0/GPIO52 W5
FANOUT1/GPIO53 W6
2 2
AH19 SATA_RX5N FANOUT2/GPIO54 Y9
AJ19 SATA_RX5P
FANIN0/GPIO56 W7
R364 1K_0402_1% V9
SATA_CALRP FANIN1/GPIO57
2 1 AB14 SATA_CALRP FANIN2/GPIO58 W8
+1.1VS_SATA 2 1 SATA_CALRN AA14
R365 931_0402_1% SATA_CALRN
TEMPIN0/GPIO171 B6
TEMPIN1/GPIO172 A6
AD11 A5 @R366
@ R366
<37> SATA_LED# SATA_ACT#/GPIO67 TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174 B5 1 2 EC_THERM# <36>
C7 0_0402_5%
R367 1 TEMP_COMM
+3VS 2 10K_0402_5% Check SW:
A3 Cinfigure to output or Internal PU/PD
VIN0/GPIO175

HW MONITOR
T13 PAD AD16 SATA_X1 VIN1/GPIO176 B4
VIN2/GPIO177 A4
VIN3/GPIO178 C5
A7 MEM_1V5
VIN4/GPIO179
VIN5/GPIO180 B7
VIN6/GBE_STAT3/GPIO181 B8
T15 PAD AC16 SATA_X2 VIN7/GBE_LED3/GPIO182 A8

J5 SPI_DI/GPIO164 NC1 G27

E2 Y2

SPI ROM
SPI_DO/GPIO163 NC2
K4 SPI_CLK/GPIO162
K9 SPI_CS1#/GPIO165
G2 ROM_RST#/GPIO161

SB820M_FCBGA605
3 3

SB820 A12(SA00003IW10)

MEM_1V5 is for gating the

glitch on PCI_AD24
+3VS
C685
2 1

0.1U_0402_16V4Z

5
U22
MEM_1V5 2

P
B
Y 4 1 2 VDDR_SW <48>
1 2 1 R424 33_0402_5%
<26,30> PCI_AD24 A

G
R422 0_0402_5% 2
NC7SZ08P5X_NL_SC70-5

3
C686
150P_0402_50V8J
1
1 @ 2
PCI_AD24 R423 0_0402_5%
1 : VDDR=1.05V
0 : VDDR=0.9V
For VDDR Voltage Switch, AMD suggest
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 28 of 55
A B C D E
 A B C D E

U20E

+1.1VS_VDDC
510mA SB800
1 2 +1.1VS Y14 VSSIO_SATA_1 VSS_1 AJ2
U20C R369 0_0805_5% Y16 A28
VSSIO_SATA_2 VSS_2
131mA SB800 Part 3 of 5 AB16 VSSIO_SATA_3 VSS_3 A2
+3VS AH1 N13 10U_0805_10V4Z 1 2 C590 AC14 E5
VDDIO_33_PCIGP_1 VDDCR_11_1 VSSIO_SATA_4 VSS_4
V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15 AE12 VSSIO_SATA_5 VSS_5 D23
1 2 Y19 N17 1U_0402_6.3V4Z 2 1 C596 AE14 E25
VDDIO_33_PCIGP_3 VDDCR_11_3 VSSIO_SATA_6 VSS_6

CORE S0
C591 22U_0805_6.3V6M AE5 U13 1U_0402_6.3V4Z 2 1 C594 AF9 E6
1 C592 0.1U_0402_16V4Z VDDIO_33_PCIGP_4 VDDCR_11_4 0.1U_0402_16V4Z C597 VSSIO_SATA_7 VSS_7 1
1 2 AC21 VDDIO_33_PCIGP_5 VDDCR_11_5 U17 2 1 AF11 VSSIO_SATA_8 VSS_8 F24
C593 1 2 0.1U_0402_16V4Z AA2 V12 0.1U_0402_16V4Z 2 1 C598 AF13 N15
VDDIO_33_PCIGP_6 VDDCR_11_6 VSSIO_SATA_9 VSS_9

PCI/GPIO I/O
C599 1 2 0.1U_0402_16V4Z AB4 V18 AF16 R13
VDDIO_33_PCIGP_7 VDDCR_11_7 VSSIO_SATA_10 VSS_10
AC8 VDDIO_33_PCIGP_8 VDDCR_11_8 W12 AG8 VSSIO_SATA_11 VSS_11 R17
AA7 VDDIO_33_PCIGP_9 VDDCR_11_9 W18 AH7 VSSIO_SATA_12 VSS_12 T10
AA9 VDDIO_33_PCIGP_10 AH11 VSSIO_SATA_13 VSS_13 P10
+1.1VS_CKVDD L69
AF7 VDDIO_33_PCIGP_11 400mA AH13 VSSIO_SATA_14 VSS_14 V11
AA19 VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 K28 2 1 +1.1VS AH16 VSSIO_SATA_15 VSS_15 U15
K29 FBMA-L11-201209-221LMA30T_0805 AJ7 M18
VDDAN_11_CLK_2 VSSIO_SATA_16 VSS_16
VDDAN_11_CLK_3 J28
22U_0805_6.3V6M C595
External Clock, connect to +1.1VS AJ11 VSSIO_SATA_17 VSS_17 V19
VDDAN_11_CLK_4 K26 1 2 AJ13 VSSIO_SATA_18 VSS_18 M11
71mA J21 directly, no need thick trace AJ16 L12

CLKGEN I/O
VDDAN_11_CLK_5 1U_0402_6.3V4Z C600 VSSIO_SATA_19 VSS_19
AF22 VDDIO_18_FC_1 VDDAN_11_CLK_6 J20 2 1 VSS_20 L18

FLASH I/O
AE25 K21 1U_0402_6.3V4Z 2 1 C601 check can be removed? A9 J7
VDDIO_18_FC_2 VDDAN_11_CLK_7 0.1U_0402_16V4Z C602 VSSIO_USB_1 VSS_21
AF24 VDDIO_18_FC_3 VDDAN_11_CLK_8 J22 2 1 B10 VSSIO_USB_2 VSS_22 P3
1 2 AC22 0.1U_0402_16V4Z 2 1 C603 K11 V4
R371 0_0402_5% VDDIO_18_FC_4 VSSIO_USB_3 VSS_23
B9 VSSIO_USB_4 VSS_24 AD6
VDDRF_GBE_S V1 1 2 D10 VSSIO_USB_5 VSS_25 AD4
R372 0_0402_5% D12 AB7
POWER VDDIO_33_GBE_S M10 1 2 D14
VSSIO_USB_6
VSSIO_USB_7
VSS_26
VSS_27 AC9
43mA R373 0_0402_5% D17 V8
VSSIO_USB_8 VSS_28
+VDDPL_3V_PCIE AE28 VDDPL_33_PCIE E9 VSSIO_USB_9 VSS_29 W9

GBE LAN
F9 VSSIO_USB_10 VSS_30 W10
L70 +1.1VS_PCIE
600mA F12 VSSIO_USB_11 VSS_31 AJ28

PCI EXPRESS
+1.1VS 2 1 U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7 1 2 F14 VSSIO_USB_12 VSS_32 B29
FBMA-L11-201209-221LMA30T_0805 V22 L9 R374 0_0402_5% F16 U4
VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 VSSIO_USB_13 VSS_33
V26 VDDAN_11_PCIE_3 C9 VSSIO_USB_14 VSS_34 Y18
C604 1 2 22U_0805_6.3V6M V27 G11 Y10
C605 1U_0402_6.3V4Z VDDAN_11_PCIE_4 VSSIO_USB_15 VSS_35

GROUND
1 2 V28 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 M6 1 2 F18 VSSIO_USB_16 VSS_36 Y12
C606 1 2 0.1U_0402_16V4Z V29 P8 R375 0_0402_5% D9 Y11
C607 0.1U_0402_16V4Z VDDAN_11_PCIE_6 VDDIO_GBE_S_2 VSSIO_USB_17 VSS_37
1 2 W22 VDDAN_11_PCIE_7 H12 VSSIO_USB_18 VSS_38 AA11
W26 VDDAN_11_PCIE_8 H14 VSSIO_USB_19 VSS_39 AA12
2 2
H16 VSSIO_USB_20 VSS_40 G4
+VDDPL_3V_SATA H18 VSSIO_USB_21 VSS_41 J4
+3VALW
93mA J11 VSSIO_USB_22 VSS_42 G8

L71 +1.1VS_SATA
AD14 VDDPL_33_SATA 32mA J19 VSSIO_USB_23 VSS_43 G9
VDDIO_33_S_1 A21 K12 VSSIO_USB_24 VSS_44 M12
+1.1VS 2 1 AJ20 VDDAN_11_SATA_1 VDDIO_33_S_2 D21 K14 VSSIO_USB_25 VSS_45 AF25
FBMA-L11-201209-221LMA30T_0805 567mA AF18 B21 2.2U_0603_6.3V4Z 1 2 C608 K16 H7

SERIAL ATA
VDDAN_11_SATA_4 VDDIO_33_S_3 2.2U_0603_6.3V4Z C609 VSSIO_USB_26 VSS_46
AH20 VDDAN_11_SATA_2 VDDIO_33_S_4 K10 1 2 K18 VSSIO_USB_27 VSS_47 AH29

3.3V_S5 I/O
C610 1 2 22U_0805_6.3V6M AG19 L10 H19 V10
C611 1U_0402_6.3V4Z VDDAN_11_SATA_3 VDDIO_33_S_5 VSSIO_USB_28 VSS_48
1 2 AE18 VDDAN_11_SATA_5 VDDIO_33_S_6 J9 VSS_49 P6
C612 1 2 1U_0402_6.3V4Z AD18 T6 +1.1VALW N4
C613 0.1U_0402_16V4Z VDDAN_11_SATA_6 VDDIO_33_S_7 VSS_50
1 2 AE16 VDDAN_11_SATA_7 VDDIO_33_S_8 T8 Y4 EFUSE VSS_51 L4
C614 1 2 0.1U_0402_16V4Z L8
VSS_52
D8 VSSAN_HWM
check 220ohm bead 113mA C615 2 1 1U_0402_6.3V4Z
+AVDD_USB
CORE S5

L72 658mA F26 C616 2 1 1U_0402_6.3V4Z M19 M20

VDDCR_11_S_1 VSSXL VSSPL_SYS
+3VALW 2 1 A18 VDDAN_33_USB_S_1 VDDCR_11_S_2 G26
FBMA-L11-201209-221LMA30T_0805 A19 TBD
VDDAN_33_USB_S_2
A20 VDDAN_33_USB_S_3 VDDIO_AZ_S M8 +VDDIO_AZ P21 VSSIO_PCIECLK_1 VSSIO_PCIECLK_14 H23
C617 1 2 10U_0805_10V4Z B18 +1.1VALW P20 H26
C618 10U_0805_10V4Z VDDAN_33_USB_S_4 +VDDCR_USB VSSIO_PCIECLK_2 VSSIO_PCIECLK_15
C619
1 2
1U_0402_6.3V4Z
B19 VDDAN_33_USB_S_5 VDDCR_11_USB_S_1 A11 197mA M22 VSSIO_PCIECLK_3 VSSIO_PCIECLK_16 AA21
1 2 B20 B11 2 1 M24 AA23
USB I/O

C620 1U_0402_6.3V4Z VDDAN_33_USB_S_6 VDDCR_11_USB_S_2 L73 FBMA-L11-160808-221LMT 0603 VSSIO_PCIECLK_4 VSSIO_PCIECLK_17

1 2 C18 VDDAN_33_USB_S_7 M26 VSSIO_PCIECLK_5 VSSIO_PCIECLK_18 AB23
C621 1 2 0.1U_0402_16V4Z C20 47mA C622 1 2 10U_0805_10V4Z P22 AD23
VDDAN_33_USB_S_8 VSSIO_PCIECLK_6 VSSIO_PCIECLK_19
D18 VDDAN_33_USB_S_9 VDDPL_33_SYS M21 +VDDPL_3V P24 VSSIO_PCIECLK_7 VSSIO_PCIECLK_20 AA26
D19 62mA C623 2 1 0.1U_0402_16V4Z P26 AC26
VDDAN_33_USB_S_10 C624 VSSIO_PCIECLK_8 VSSIO_PCIECLK_21
D20 VDDAN_33_USB_S_11 VDDPL_11_SYS_S L22 +VDDPL_11V 2 1 0.1U_0402_16V4Z T20 VSSIO_PCIECLK_9 VSSIO_PCIECLK_22 Y20
E19 VDDAN_33_USB_S_12 17mA T22 VSSIO_PCIECLK_10 VSSIO_PCIECLK_23 W21
PLL

VDDPL_33_USB_S F19 +VDDPL_3V_USB T24 VSSIO_PCIECLK_11 VSSIO_PCIECLK_24 W20

L74 +1.1V_USB
200mA 5mA +3VALW
V20 VSSIO_PCIECLK_12 VSSIO_PCIECLK_25 AE26
+1.1VALW 2 1 C11 VDDAN_11_USB_S_1 VDDAN_33_HWM_S D6 +3V_HWM J23 VSSIO_PCIECLK_13 VSSIO_PCIECLK_26 L21
FBMA-L11-160808-221LMT 0603 +VDDLX_3V
3
D11 VDDAN_11_USB_S_2 197mA VSSIO_PCIECLK_27 K20
3
VDDXL_33_S L20 2 1
C625 2 1 2.2U_0603_6.3V4Z L75 FBMA-L11-160808-221LMT 0603 Part 5 of 5
C626 2 1 0.1U_0402_16V4Z C627 1 2 2.2U_0603_6.3V4Z
SB820M_FCBGA605 SB820M_FCBGA605

SB820 A12(SA00003IW10) SB820 A12(SA00003IW10)

+VDDPL_11V +1.1VALW +VDDPL_3V_USB +3VALW +3V_HWM +3VALW

+VDDPL_3V_PCIE +3VS +VDDPL_3V +3VS
L76 L77 L78
L79 L80 2 1 2 1 2 1
2 1 2 1 FBMA-L11-160808-221LMT 0603 FBMA-L11-160808-221LMT 0603 FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603 FBMA-L11-160808-221LMT 0603
1 1 1 1 1
1 1 1 C630 C632
C628 C629 C631 C633
C634 C635 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
0.1U_0402_16V4Z 2 2 2 2 2
2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z
2 2 2

+VDDPL_3V_SATA +3VS +VDDIO_AZ +3VALW

L81
4 4
2 1 1 2
FBMA-L11-160808-221LMT 0603 R376 0_0402_5%

1 1 1
C636
C637 C638
0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z
2 2 2
For 3V AZ device
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 29 of 55
A B C D E
 A B C D E

REQUIRED STRAPS Check Internal PU/PD

AZ_SDOUT PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LCP_CLK1 GPIO200 GPIO199

PULL LOW POWER ALLOW PCIE WATCHDOG USE CPU/HT CLK EC CLOCKGEN
HIGH MODE GEN2 TIMER DEBUG SEL ENABLE ENABLE H,H = Reserved
ENABLE STRAP Enable
1 H,L = SPI ROM 1

L,H = LPC ROM (Default L,NC)

PULL Performance FORCE PCIE WATCHDOG IGNORE CPU/HT CLK EC CLOCKGEN
LOW MODE GEN1 TIMER DEBUG SEL DISABLE DISABLE L,L = FWH ROM
DISABLE STRAP Disable
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

+VDDIO_AZ +3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

2.2K_0402_5%
R385
R377

R378

R379

R380

R381

R382

R383

R384
INT@ INT@

2
@ @ @ @ @ @
<27> HDA_SDOUT
<26> PCI_CLK1
<26> PCI_CLK2
<26> PCI_CLK3
<26> PCI_CLK4
<26,36> LPC_CLK0_EC
<26> LPC_CLK1
<27> GPIO200
2 <27> GPIO199 2

2.2K_0402_5%
1

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

2.2K_0402_5%
R393

R394
R386

R387

R388

R389

R390

R391

R392
EXT@ EXT@ @
2

2
+3VS +3VS

DEBUG STRAPS

10K_0402_5%

10K_0402_5%
1

1
R395

R396
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
3 3
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

2
USE PCI DISABLE ILA USE FC PLL USE DEFAULT DISABLE PCI <26> PCI_AD29
PULL PLL AUTORUN PCIE STRAPS MEM BOOT <26> PCI_AD28
HIGH <26> PCI_AD27
<26> PCI_AD26
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
<26> PCI_AD25
<26,28> PCI_AD24
<26> PCI_AD23
PULL BYPASS ENABLE ILA BYPASS USE EEPROM ENABLE PCI
LOW PCI PLL AUTORUN FC PLL PCIE STRAPS MEM BOOT

1
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R397

R398

R399

R400

R401
2

2
Check AD29,AD28 strap function @ @ @ @ @
check default

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 30 of 55
A B C D E
 A B C D E F G H

1
SATA HDD Conn. 1

JHDD1

1 GND
C656 1 2 0.01U_0402_16V7K SATA_STX_C_DRX_P0 2
<28> SATA_STX_DRX_P0 A+
C658 1 2 0.01U_0402_16V7K SATA_STX_C_DRX_N0 3
<28> SATA_STX_DRX_N0 A-
4 GND
<28> SATA_DTX_C_SRX_N0 C657 1 2 0.01U_0402_16V7K SATA_DTX_SRX_N0 5
C659 1 SATA_DTX_SRX_P0 B-
<28> SATA_DTX_C_SRX_P0 2 0.01U_0402_16V7K 6 B+
7 GND
+3VS
+3VS 8 V33
1 9 V33
C639 10 V33
11 GND
0.1U_0402_16V4Z 12
2 GND
13 GND
14 V5
15 V5
R405 1 2 0_0805_5% +5VS_HDD 16
+5VS V5
17 GND
18 Reserved
10U_0805_10V4Z 0.1U_0402_16V4Z 19 GND
20 V12
1 1 1 1 21 V12 GND 24
C660 C661 C662 C663 22 23
V12 GND

2 2 2 2 SANTA_192301-1
2 CONN@ 2
1U_0402_6.3V4Z 1000P_0402_50V7K
<NAV70 use>

SATA ODD Conn.

JODD1

1 GND
<28> SATA_STX_DRX_P1 C648 1 2 0.01U_0402_16V7K SATA_STX_C_DRX_P1 2
C649 1 SATA_STX_C_DRX_N1 A+
<28> SATA_STX_DRX_N1 2 0.01U_0402_16V7K 3 A-
4 GND
C650 1 2 0.01U_0402_16V7K SATA_DTX_SRX_N1 5
<28> SATA_DTX_C_SRX_N1 B-
C651 1 2 0.01U_0402_16V7K SATA_DTX_SRX_P1 6
<28> SATA_DTX_C_SRX_P1 B+
7 GND

3 R403 1 @ 3
2 1K_0402_1% 8 DP
9 +5V
+5VS R404 1 2 0_0805_5% +5VS_ODD 10 17
+5V GND
11 MD GND 16
12 GND NC 15
13 GND NC 14

10U_0805_10V4Z 0.1U_0402_16V4Z
OCTEK_SLS-13SB1G_RV
1 1 1 1 CONN@
C652 C653 C654 C655

2 2 2 2

1U_0402_6.3V4Z 1000P_0402_50V7K

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 31 of 55
A B C D E F G H
 A B C D

+3V_LAN

R800
60mil
+3VALW 1 2

0_1206_5%
1 1
C901 C902

4.7U_0603_6.3V6K
U70 2 2
0.1U_0402_16V4Z
+3V_LAN 42 25 +LAN_BIASVDDH
VDDC BIASVDDH
1 1

+1.2V_LAN 0.1U_0402_16V4Z 6 14 +LAN_XTALVDDH

VDDC XTALVDDH
1 1 1 1 15 VDDC
C900 C903 C904 C905 41 VDDC +LAN_AVDDH
AVDDH 30
4.7U_0603_6.3V6K
2 2 2 2 SPROM_CLK SPROM_DOUT
AVDDH 36
0.1U_0402_16V4Z 0.1U_0402_16V4Z (EECLK) (EEDATA)
+LAN_AVDDL 27 AVDDL LAN_MIDI3- On chip 1 0
33 AVDDL TRD3_N 37 LAN_MIDI3- <33>
39 AVDDL
38 LAN_MIDI3+
TRD3_P LAN_MIDI3+ <33> AT24C02 1 1

35 LAN_MIDI2-
TRD2_N LAN_MIDI2- <33> +3V_LAN
34 LAN_MIDI2+
TRD2_P LAN_MIDI2+ <33>
+LAN_GPHYPLLVDDL 24 C906 1 2 0.1U_0402_16V4Z
GPHY_PLLVDDL
31 LAN_MIDI1- @
TRD1_N LAN_MIDI1- <33>

2
32 LAN_MIDI1+ R802 R803
TRD1_P LAN_MIDI1+ <33>
1K_0402_1% 1K_0402_1%
+LAN_PCIEPLLVDD 18 @
PCIE_PLLVDDL LAN_MIDI0- U71 @
29 LAN_MIDI0- <33>

1
TRD0_N
21 PCIE_PLLVDDL 8 VCC A0 1
28 LAN_MIDI0+ 7 2
TRD0_P LAN_MIDI0+ <33> WP A1
SPROM_CLK 6 3
SPROM_DOUT SCL NC
5 SDA GND 4

AT24C02_SO8

2
2 2

LINKLED# 48 2 1 LAN_LINK# <33>

R801 R811 R812
47 0_0402_5% 1K_0402_1% 1K_0402_1%
SPD100LED#
<12> PCIE_PTX_C_IRX_P0 C9071 2 0.1U_0402_16V7K PCIE_PTX_IRX_P0 17 PCIE_TXD_P @
<12> PCIE_PTX_C_IRX_N0 C9081 2 0.1U_0402_16V7K PCIE_PTX_IRX_N0 16 46

1
PCIE_TXD_N SPD1000LED#
<12> PCIE_ITX_C_PRX_P0 22 PCIE_RXD_P
<12> PCIE_ITX_C_PRX_N0 23 PCIE_RXD_N TRAFFICLED# 45 2 1 LAN_ACTIVITY# <33>
LAN_PME# 4 R805
WAKE# 0_0402_5%
LAN_RESET# 2 REST#
20 PCIE_REFCLK_P
R806 1 @ 2 0_0402_5% 19
<27,34> SB_PCIE_WAKE# PCIE_REFCLK_N
<36> EC_PME# R807 1 2 0_0402_5%
+3V_LAN R808 1 2 4.7K_0402_5%

R809 1
20mil
<15,26,34> PLT_RST# 2 0_0402_5% L100
5 +LAN_XTALVDDH 1 1 2 +3V_LAN
MODE C909 BLM18AG601SN1D_2P
<22> CLK_PCIE_LAN
0.1U_0402_16V4Z
<22> CLK_PCIE_LAN#
2
20mil L101
43 SPROM_DOUT +LAN_BIASVDDH 1 1 2
EEDATA C910 BLM18AG601SN1D_2P
44 SPROM_CLK
R810 1 EECLK
+3VS 2 1K_0402_5% 40 VMAIN_PRSINT
0.1U_0402_16V4Z
2
R813 1
20mil
2 10K_0402_5% 1 LOW_PWR
L102
+LAN_AVDDH
1 1 1 2
L103
C911 C912 BLM18AG601SN1D_2P
11 +1.2V_LAN_OUT 1 2 +1.2V_LAN
SR_LX 4.7UH_PG031B-4R7MS_1.1A_20% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
LAN_XTALO_R 2 2
3 13 XTALO SR_VFB 8 1 1 3

C913
LAN_XTALI 12 C914 20mil
XTALI 0.1U_0402_16V4Z 10U_0805_10V4Z L104
2 2 +LAN_PCIEPLLVDD 1 2 +1.2V_LAN
1 1 BLM18AG601SN1D_2P
R814
C915 C916
1 2 LAN_RDAC 26 RDAC 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
SR_VDDP 10 +3V_LAN 2 2
1.24K_0402_1% 1 1
9 C917 C918
SR_VDD

2 2 20mil L105
<22,27> LAN_CLKREQ# 3 CLKREQ# 4.7U_0603_6.3V6K 0.1U_0402_16V4Z +LAN_GPHYPLLVDDL 1 2 +1.2V_LAN
7 1 1 BLM18AG601SN1D_2P
NC C919 C920
PAD

0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2
49

BCM57780A0KMLG_QFN48_7X7 20mil L106

+LAN_AVDDL 1 2 +1.2V_LAN
1 1 BLM18AG601SN1D_2P
C921 C922

LAN_XTALI 0.1U_0402_16V4Z 4.7U_0603_6.3V6K

2 2
LAN_XTALO_R
1

4
R815 4

200_0402_1%

Y5
2

1 2 LAN_XTALO

25MHZ_20PF_7A250000121
1 Security Classification Compal Secret Data Compal Electronics, Inc.
C923 C924 2008/04/16 2010/03/12 Title
33P_0402_50V8J 33P_0402_50V8J
Issued Date Deciphered Date
2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 32 of 55
A B C D
 5 4 3 2 1

D D

BH GS5009-D
LAN Connector
<SP050006B00>
JRJ45
T25 12
<32> LAN_ACTIVITY# Yellow LED-
1 TCT1 MCT1 24 +3V_LAN 2 1 11 Yellow LED+
<32> LAN_MIDI0+ LAN_MIDI0+ 2 23 RJ45_MIDI0+ R823 1K_0402_5%
LAN_MIDI0- TD1+ MX1+ RJ45_MIDI0- RJ45_MIDI3-
<32> LAN_MIDI0- 3 TD1- MX1- 22 1 2 8 PR4-
C938 220P_0402_50V7K
4 21 RJ45_MIDI3+ 7
LAN_MIDI1+ TCT2 MCT2 RJ45_MIDI1+ PR4+
<32> LAN_MIDI1+ 5 TD2+ MX2+ 20
<32> LAN_MIDI1- LAN_MIDI1- 6 19 RJ45_MIDI1- RJ45_MIDI1- 6
TD2- MX2- PR2-
7 18 RJ45_MIDI2- 5
LAN_MIDI2+ TCT3 MCT3 RJ45_MIDI2+ PR3-
<32> LAN_MIDI2+ 8 TD3+ MX3+ 17
<32> LAN_MIDI2- LAN_MIDI2- 9 16 RJ45_MIDI2- RJ45_MIDI2+ 4
TD3- MX3- PR3+
10 15 RJ45_MIDI1+ 3
LAN_MIDI3+ TCT4 MCT4 RJ45_MIDI3+ PR2+
<32> LAN_MIDI3+ 11 TD4+ MX4+ 14
<32> LAN_MIDI3- LAN_MIDI3- 12 13 RJ45_MIDI3- RJ45_MIDI0- 2
TD4- MX4- PR1-
SHLD2 13
RJ45_MIDI0+ 1 14
C
PR1+ SHLD1 C

1
350UH_IH-037-2 10
<32> LAN_LINK# Green LED-
1 1 1 1 R819 R820 +3V_LAN 2 1 9
C928 C929 C930 C931 75_0402_1% 75_0402_1% R824 1K_0402_5% Green LED+
SANTA_130451-K

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 CONN@
2 2 2 2 C942 220P_0402_50V7K
R821 R822
0.1U_0402_16V4Z 0.1U_0402_16V4Z 75_0402_1% 75_0402_1%
RJ45_GND 1 2 LANGND 40mil

2
1 1
RJ45_GND C940
Place close to TCT pin 1000P_1206_2KV7K C941 C939
4.7U_0603_6.3V6K
40mil 2 2

LAN_ACTIVITY# 0.1U_0402_16V4Z
LAN_LINK#

2
D40
LAN_ACTIVITY# 1 2
PJDLC05C_SOT23-3 C943 220P_0402_50V7K
@
LAN_LINK# 1 2
C944 220P_0402_50V7K
B B

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 33 of 55
5 4 3 2 1
 A B C D E

1 1

Mini-Express Card for WLAN

+3VS +1.5VS

1 1 1 1 1 1
C705 C706 C707 C708 C709 C710

4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2 2 2

JMINI1
SB_PCIE_WAKE# R440 1 @ 2 0_0402_5% 1 2 +3VS
<27,32> SB_PCIE_WAKE# 1 2
3 3 4 4
5 5 6 6 +1.5VS
<22,27> MINI1_CLKREQ# 7 7 8 8 Mini Card Power Rating
9 9 10 10
<22> CLK_PCIE_MINI1# 11 11 12 12 Power Primary Power (mA) Auxiliary Power (mA)
<22> CLK_PCIE_MINI1 13 13 14 14
15 15 16 16 Peak Normal Normal
+3VS 1000 750
17 17 18 18
19 20 WL_OFF# +3V 330 250 250 (wake enable)
19 20 WL_OFF# <36>
21 22 PLT_RST#
21 22 PLT_RST# <15,26,32>
23 24 +3V_WLAN 1 2 +3VS +1.5VS 500 375 5 (Not wake enable)
2 <12> PCIE_PTX_C_IRX_N1 23 24 2
25 26 R441 1 2 0_0603_5% +3VALW
<12> PCIE_PTX_C_IRX_P1 25 26
27 28 R442 @ 0_0603_5%
27 28 MINI1_SMBCLK @
29 29 30 30 1 2 SB_SMDAT0 <10,11,22,27>
<12> PCIE_ITX_C_PRX_N1 31 32 MINI1_SMBDAT R443
1 @ 0_0603_5%
2
31 32 SB_SMCLK0 <10,11,22,27>
<12> PCIE_ITX_C_PRX_P1 33 34 R444 0_0603_5%
33 34
35 35 36 36 USB20_N8 <27>
37 37 38 38 USB20_P8 <27>
+3VS 39 39 40 40
41 42 WIMAX_LED#
41 42 WLAN_LED#_L
43 43 44 44
45 45 46 46
0_0402_5%
R445 1 2 E51TXD_P80DATA_R
47
49
47 48 48
50
(9~16mA) +3VS
<36> E51TXD_P80DATA 49 50
E51RXD_P80CLK 51 52
<36> E51RXD_P80CLK 51 52

G1
G2
G3
G3

1
ACES_88910-5204 R530 2 1 0_0402_5% R537

53
54
55
56
CONN@ 100K_0402_5%

D47 @

2
<NAV70 use> WIMAX_LED# 2
1 MINI1_LED# <36>
WLAN_LED#_L
Height : 4mm 3

CHP202UPT_SOT323-3

R531 2 1 0_0402_5%

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 34 of 55
A B C D E
 A B C D E

+USB_VCCA
+3VALW
+USB_VCCA

1
SVPE, 4.4m, 17mohm 1
+5VALW

1
+USB_VCCA + C711
U24 80mil R446 C712
1 8 100K_0402_5% 220U_6.3V_M

2
GND VOUT 2
2 VIN VOUT 7

W=80mils
3 6 470P_0402_50V7K

2
1 VIN VOUT R447 1 1
1 4 EN FLG 5 2 10K_0402_5% USB_OC#0 <27>
C713
RT9715BGS_SO8 1 2
4.7U_0805_10V4Z 1 R448 @ 0_0402_5%
2 C714
0.1U_0402_16V4Z
L83 JUSB1
2 USB20_N0
<42> SYSON# <27> USB20_N0 1 1 2 2 1 1
USB20_N0_R 2
USB20_P0_R 2
3 3
+3VALW USB20_P0
<27> USB20_P0 4 4 3 3 4 4 <NAL00 use>
5 GND
WCM2012F2SF-900T04_0805 6
+5VALW GND

1
+USB_VCCB R449 7
U25 0_0402_5% GND
80mil R450
8 GND
1 GND VOUT 8 1 2 USB_OC#2 <27> 1 2
2 7 100K_0402_5% R451 @ 0_0402_5% SUYIN_020133MB004S580ZL-C
VIN VOUT CONN@
3 6

2
VIN VOUT
1 4 EN FLG 5 1 2 USB_OC#1 <27>
C715 R452
RT9715BGS_SO8 10K_0402_5% 1
4.7U_0805_10V4Z C716 D10
2 USB20_P0_R
6 CH3 CH2 3
0.1U_0402_16V4Z
2
SYSON#
+USB_VCCA 5 Vp Vn 2

USB20_N0_R 4 1
CH4 CH1
2 CM1293-04SO_SOT23-6 2

To USB/B Connector To CardReader/B Connector

+USB_VCCB

(Port 1,2)
JUSB2 JCR1 +3VS
1 10 C717
1 GND 4.7U_0805_10V4Z
2 2 GND 9
3 3 8 8 1 2
4 7
4
5 5
6 USB20_N1
7
6 6
5
5IN1_LED# <37> Bluetooth Conn.
6 USB20_N1 <27> 5
7 USB20_P1 4
7 USB20_P1 <27> 4
8 3 USB20_N6
8 3 USB20_N6 <27>
9 USB20_N2 2 USB20_P6
9 USB20_N2 <27> 2 USB20_P6 <27>
10 USB20_P2 1
10 USB20_P2 <27> 1
13 GND 11 11
14 12 +3VALW +3VS
GND 12 ACES_85201-08051
CONN@
ACES_85201-1205N
CONN@ <NEW70 use> 1 BT@
C718 C719
<NAL00 use> BT@
0.1U_0402_16V4Z BT@ 1U_0402_6.3V4Z

3
2
S
G Q24
3 BT@ 2 3
<36> BT_ON# 1 2
R453 10K_0402_5%
D AO3413_SOT23-3

1
C720 W=40mils
To 3G Module Connect BT@
0.1U_0402_16V4Z
+BT_VCC
+3VS_WWAN
1

1
C721 BT@ C722 BT@ BT@
R454
2

+3VS_WWAN +BT_VCC 4.7U_0805_10V4Z 300_0603_5%

(Port 9) R457 2 0.1U_0402_16V4Z
JP4 100K_0402_5% +3VS +3VS_WWAN JBT1

2
1 1 Peak: 2.75A 10 GND 8 8
BT@
2 7
1

2 Normal: 1.1A 7

1
WWAN_OFF# 3G@ 2 D
3 3 WWAN_OFF# <36> 1 6 6 USB20_P14 <27>
4 WWAN_LED# <36> R455 0_1206_5% 5 2 Q25
4 5 USB20_N14 <27>
5 4 G 2N7002_SOT23
5 4
6 USB20_N9 <27> 3 S

3
6 3
7 7 USB20_P9 <27> 1 2 2
8 8 9 GND 1 1
9 + C723
9 USB20_N7 <27> 150U_B_6.3VM_R40M
10 change to SGA00002N80 ACES_87213-0800G
10 USB20_P7 <27>
11 3G@ CONN@
GND 2
GND 12
Close to WWAN CONN <NAL00 use>
ACES_87036-1001-CP
CONN@

<NAV70 use>
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 35 of 55
A B C D E
 5 4 3 2 1

+3VALW For EC Tools

L84
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2+EC_VCCA +3VALW
1 1 C725 1 1 2 2
1
BLM18AG601SN1D_2P JP7 Place on MiniCard door
C724 1 1
C726 C727 C728 C729 1 E51RXD_P80CLK
2 2 E51RXD_P80CLK <34>
1000P_0402_50V7K 1000P_0402_50V7K C730 3 E51TXD_P80DATA
KSO[0..17] 2 2 2 2 1 1 3 E51TXD_P80DATA <34>
KSO[0..17] <37> 4 4
2

ECAGND
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
KSI[0..7] ACES_85205-0400
KSI[0..7] <37>
@
D D
+3VALW

111
125
22
33
96

67
9
U26 65W/90W# 2 1
VGA_DBCLK R458 100K_0402_5%

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
VR_ON 2 1
EC must program to 500KHZ output R459 100K_0402_5%
Start and stop follow SUP high/Low 3S/4S# 1 2
EC_GA20 1 21 R460 4.7K_0402_5%
<27> EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F VGA_DBCLK <22>
EC_KBRST# 2 23 BEEP#
<27> EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# <39>
SERIRQ 3 26
<26> SERIRQ LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF
<26> LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF <46,49>
C732 LPC_AD3 5 2 1 ECAGND
<26> LPC_AD3 LAD3
@ 22P_0402_50V8J @ LPC_AD2 7 PWM Output C731 0.01U_0402_16V7K
<26> LPC_AD2 LAD2
2 1 2 1 LPC_AD1 8 63 BATT_TEMP
<26> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <44>
R461 33_0402_5% LPC_AD0 BATT_OVP
<26> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP <46>
ADP_I/AD2/GPIO3A 65 ADP_I <46>
LPC_CLK0_EC 12 AD Input 66 AD_BID0 Analog Project ID definition
<26,30> LPC_CLK0_EC PCICLK AD3/GPIO3B
A_RST# 13 75 AD_PID0
<13,14,26> A_RST# PCIRST#/GPIO05 AD4/GPIO42
37 76 +3VALW
EC_SCI# ECRST# SELIO2#/AD5/GPIO43
<27> EC_SCI# 20 SCI#/GPIO0E
+3VALW 2 1 1 2 38 CLKRUN#/GPIO1D

2
R462 47K_0402_5% @ R428 10K_0402_5% 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG <23>
2 1 70 EN_DFAN1 Ra R463 For PEW56 PID
EN_DFAN1/DA1/GPIO3D EN_DFAN1 <41>
C733 0.1U_0402_16V4Z DA Output 71 IREF
IREF/DA2/GPIO3E IREF <46>
KSI0 55 72 CALIBRATE# PEW@ 100K_0402_5% 56@ R464
KSI0/GPIO30 DA3/GPIO3F CALIBRATE# <46>
+5VS KSI1 56

1
KSI2 KSI1/GPIO31 AD_PID0
57 KSI2/GPIO32
KSI3 58 83 EC_MUTE# 18K_0402_5%
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# <40>

2
C 1 2 TP_CLK KSI4 59 84 1 C
R465 4.7K_0402_5% KSI5 KSI4/GPIO34 PSDAT1/GPIO4B WWAN_LED# R464 C734
60 KSI5/GPIO35 PSCLK2/GPIO4C 85 WWAN_LED# <35> Rb
1 2 TP_DATA KSI6 61 PS2 Interface 86 3G_LED# For NEW76/86/96 PID
KSI6/GPIO36 PSDAT2/GPIO4D 3G_LED# <37>
R466 4.7K_0402_5% KSI7 62 87 TP_CLK 768696@ 8.2K_0402_5% 0.1U_0402_16V4Z
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <37> 2
KSO0 39 88 TP_DATA For PEW76/86/96 PID NEW@ R464 100K_0402_5%
TP_DATA <37>

1
KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 1 2
40 KSO1/GPIO21
KSO2 41
KSO3 KSO2/GPIO22 3S/4S#
42 KSO3/GPIO23 SDICS#/GPXOA00 97 3S/4S# <46>
+3VALW 1 2 KSO4 43 98 65W/90W#
KSO4/GPIO24 SDICLK/GPXOA01 65W/90W# <46>
R541 2.2K_0402_5% KSO5 VLDT_EN
@ EC_SMB_CK2 KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
VLDT_EN <42,48>
+3VS 1
R467
2
2.2K_0402_5% KSO7
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# <37> Analog Board ID definition
46 KSO7/GPIO27 SPI Device Interface
1 @ 2 EC_SMB_DA2 KSO8 47 +3VALW
R468 2.2K_0402_5% KSO9 KSO8/GPIO28
48 KSO9/GPIO29 SPIDI/RD# 119 EC_SI_SPI_SO <37>
+3VALW 1 2 KSO10 49 120
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <37>

2
R542 2.2K_0402_5% KSO11 50 SPI Flash ROM 126 EC_SPICLK_L For Capilano VGA identify
KSO12 KSO11/GPIO2B SPICLK/GPIO58 R469
51 KSO12/GPIO2C SPICS# 128 EC_SPICS#/FSEL# <37>
KSO13 52 Ra CAP@ R470
KSO14 KSO13/GPIO2D 100K_0402_5%
53 KSO14/GPIO2E
KSO15 54 73 WWAN_OFF#
WWAN_OFF# <35>

1
+3VALW KSO16 KSO15/GPIO2F CIR_RX/GPIO40 AD_BID0 18K_0402_5%
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74
KSO17 82 89
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <46>

1
1 2 EC_SMB_CK1 90 BATT_BLUE_LED# 1
BATT_CHGI_LED#/GPIO52 BATT_BLUE_LED# <37> Delay EC_PWROK 50ms
R471 2.2K_0402_5% 91 INT_VGAPWR_ON R470 C735
EC_SMB_DA1 EC_SMB_CK1 CAPS_LED#/GPIO53 BATT_AMB_LED# INT_VGAPWR_ON <38> for VGA criterial Rb
1 2 <44> EC_SMB_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 BATT_AMB_LED# <37>
R472 2.2K_0402_5% EC_SMB_DA1 78 93 PWR_LED PWR_LED <37> 8.2K_0402_5% 0.1U_0402_16V4Z
<44> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 2
1 2 KSO1 EC_SMB_CK2 79 SM Bus 95 SYSON
<8,16> EC_SMB_CK2 SYSON <42,47>

2
R473 47K_0402_5% EC_SMB_DA2 SCL2/GPIO46 SYSON/GPIO56 VR_ON
<8,16> EC_SMB_DA2 80 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 121 VR_ON <52>
1 2 KSO2 127 ACIN
B R474 47K_0402_5% AC_IN/GPIO59 ACIN <16,37,42,43> B

2 1 LID_SW#
R475 100K_0402_5% PM_SLP_S3# 6 100 EC_RSMRST#
<27> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <27> EC_SPICLK <37>
1 @ 2 EC_PME# PM_SLP_S5# 14 101 EC_LID_OUT#
<27> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <27>
R476 10K_0402_5% EC_SMI# 15 102 EC_ON EC_SPICLK_L 1 2 @
<27> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <38>
2 1 ENBKL 16 103 EC_SWI# R419 0_0402_5% C783 33P_0402_50V8K
LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# <27>
R488 100K_0402_5% MINI1_LED# 17 104 EC_PWROK
<34> MINI1_LED# SUSP#/GPIO0B ICH_PWROK/GPXO06
2 1 LOCAL_DIM LOCAL_DIM 18 GPO 105 BKOFF# Reserve for EMI, close to EC
<23> LOCAL_DIM PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <23>
R526 100K_0402_5% COLOR_ENG_EN 19 GPIO 106 WL_OFF#
<23> COLOR_ENG_EN EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# <34>
2 1 COLOR_ENG_EN EC_INVT_PWM 25 107 KB926_ID
<23> EC_INVT_PWM EC_THERM#/GPIO11 GPXO10
R527 100K_0402_5% FAN_SPEED1 28 108 VGA_ON <22,38,42,50> Delay SUSP# 10ms
<41> FAN_SPEED1 BT_ON# FAN_SPEED1/FANFB1/GPIO14 GPXO11
<35> BT_ON# 29 FANFB2/GPIO15
For Low PWR panel use E51TXD_P80DATA 30
E51RXD_P80CLK EC_TX/GPIO16 VGATE
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 VGATE <52>
ON/OFF 32 112 ENBKL
<38> ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL <13>
<37> PWR_SUSP_LED PWR_SUSP_LED 34 114 EAPD
PWR_LED#/GPIO19 GPXID3 EAPD <39>
WLAN_LED# 36 GPI 115 EC_THERM# EC_PWROK 1 2
<37> WLAN_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# <28> SB_PWRGD <8,13,27>
116 SUSP# R254 0_0402_5%
GPXID5 SUSP# <22,42,46>
117 PBTN_OUT#
GPXID6 EC_PME# PBTN_OUT# <27>
GPXID7 118 EC_PME# <32>
EC_CRY1 122
EC_CRY2 XCLK1
123 XCLK0 V18R 124
1
AGND

C736
GND
GND
GND
GND
GND

EC_CRY1 EC_CRY2 C737 100P_0402_50V8J

4.7U_0805_10V4Z BATT_TEMP 2 1
KB926QFD3_LQFP128_14X14 2 C738 100P_0402_50V8J
2 2
11
24
35
94
113

69

C739 C740 20mil BATT_OVP 2 1

1

C741 100P_0402_50V8J
A A
15P_0402_50V8J X1 15P_0402_50V8J ECAGND 2 L85 1 ACIN 2 1
KB926 Rev:D3(SA00001J580)
OSC

OSC

1 1 +3VALW BLM18AG601SN1D_2P

2 1 KB926 Rev:E0(SA00001J5A0)
R529 100K_0402_5%
NC

NC

32.768KHZ_12.5PF_Q13MC14610002 KB926_ID
1
R528 @
2
100K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

High : D3 SCHEMATIC, MB A5911
EC Version control Low : E0 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 36 of 55
5 4 3 2 1
 +5VS
+5VS

JTP1
1 C745
1
2 2 TP_CLK <36>
3 0.1U_0402_16V4Z
3 TP_DATA <36>
+3VALW 1 2 C742 1 2 0.1U_0402_16V4Z 4 LEFT_BTN#
R479 0_0603_5% 4 RIGHT_BTN#
5 5
6 6
+SPI_VCC 7 GND
8 GND
U27
<36> EC_SPICS#/FSEL#
EC_SPICS#/FSEL# 1 8 ACES_85201-0605N
R480 1 CS# VCC
2 4.7K_0402_5% SPI_WP# 3 WP# SCLK 6 EC_SPICLK_R R481 1 2 0_0402_5% EC_SPICLK <36>
CONN@
+3VALW R482 1 2 4.7K_0402_5% SPI_HOLD# 7 5 EC_SO_SPI_SI_R R483 1 2 0_0402_5% RIGHT_BTN# TP_CLK
HOLD# SI EC_SO_SPI_SI <36>
4 2 EC_SI_SPI_SO_R R484 1 2 0_0402_5%
GND SO EC_SI_SPI_SO <36>
LEFT_BTN# TP_DATA
MX25L1605DM2I-12G SOP 8P

2
SA00002TO00 SW1 SW2
SMT1-05-A_4P SMT1-05-A_4P
LEFT_BTN# 3 1 RIGHT_BTN# 3 1 D11 D13

4 2 4 2

U28 @ PJDLC05C_SOT23-3 PJDLC05C_SOT23-3

5
6

5
6
EC_SPICS#/FSEL# 1 8 +SPI_VCC
SPI_WP# CE# VDD EC_SPICLK_R
3 6

1
SPI_HOLD# WP# SCK EC_SO_SPI_SI_R
7 HOLD# SI 5
4 2 EC_SI_SPI_SO_R
VSS SO

2
MX25L1005AMC-12G_SOP8
@
0_0402_5% R485

1
@
C746
33P_0402_50V8K
Right side
Left side

JLED2 JLED1
1 1 +3VALW 1 1 +3VALW
2 LID_SW# LID_SW# <36> 2 LID_SW#
2 ACIN_LED# 2 ACIN_LED#
3 3 3 3
4 3G_LED# 4 3G_LED#
4 3G_LED# <36> 4
5 WLAN_LED# 5 WLAN_LED#
5 WLAN_LED# <36> 5
JKB1 6 MEDIA_LED# 6 MEDIA_LED#
6 6
(Left) 7 7 +3VS 7 7 +3VS
KSO0 26 28 8 PWR_LED# 8 PWR_LED#
KSO1 KSO0 G2 8 ON/OFFBTN# 8 ON/OFFBTN#
25 KSO1 G1 27 9 9 ON/OFFBTN# <38> 9 9
KSO2 24 10 10
KSO3 KSO2 KSI[0..7] 10 10
23 KSO3 KSI[0..7] <36> GND 11 GND 11
KSO4 22 12 12
KSO5 KSO4 KSO[0..17] GND GND
21 KSO5 KSO[0..17] <36>
KSO6 20 ACES_85201-1005N ACES_85201-1005N
KSO7 KSO6 CONN@ CONN@
19 KSO7
KSO8 18
KSO9 KSO8
17 KSO9
KSO10 16
KSO11 KSO10 +3VS
15 KSO11
KSO12 14 ACIN_LED#
KSO13 KSO12
13 KSO13

2
KSO14 12 +3VS
KSO15 KSO14 R486
11 KSO15

1
KSO16 D
10 KSO16
KSO17 9 <16,36,42,43> ACIN 2 Q71 100K_0402_5%
KSO17

5
KSI0 8 G U29

1
KSI1 KSI0
7 S
B 2

P
5IN1_LED# <35>

3
KSI2 KSI1 2N7002_SOT23 MEDIA_LED#
6 KSI2 4 Y
KSI3 5 1
KSI3 A SATA_LED# <28>

G
KSI4 4
KSI5 KSI4 NC7SZ08P5X_NL_SC70-5
3

3
KSI6 KSI5
2 KSI6
KSI7 1 KSI7 PWR_LED#
(Right) KSO16 C747 1 2 100P_0402_50V8J

6
ACES_88747-2601
KSO17 C748 1 100P_0402_50V8J
CONN@ 2
LED1 NEW95 LED Option
KSO15 C749 1 100P_0402_50V8J KSO7 C750 1 100P_0402_50V8J DMN66D0LDW-7_SOT363-6 HT-191NB5_BLUE
2 2 <36> PWR_LED 2
Q26A 2 95@ 1
2
KSO14 C751 1 2 100P_0402_50V8J KSO6 C752 1 2 100P_0402_50V8J +3VS 1 7585@ 2 2 1 PWR_LED# R477 680_0402_5%

1
R487 R477 2.2K_0402_5% B
KSO13 C753 1 2 100P_0402_50V8J KSO5 C754 1 2 100P_0402_50V8J 100K_0402_5% Change to SC591NB5A30 for BC bin 2 95@ 1
R478 680_0402_5%
KSO12 C755 1 2 100P_0402_50V8J KSO4 C756 1 2 100P_0402_50V8J LED2
1

HT-191UD5_AMBER 2 95@ 1
R499 680_0402_5%
KSI0 C757 1 2 100P_0402_50V8J KSO3 C758 1 2 100P_0402_50V8J +3VALW 1 7585@ 2 2 1 PWR_SUSP_LED#
R478 3.9K_0402_5% A 2 95@ 1
KSO11 C759 1 2 100P_0402_50V8J KSI4 C760 1 2 100P_0402_50V8J PWR_SUSP_LED# R498 680_0402_5%
3

KSO10 C761 1 2 100P_0402_50V8J KSO2 C762 1 2 100P_0402_50V8J LED3

HT-191NB5_BLUE
KSI1 C763 1 2 100P_0402_50V8J KSO1 C764 1 2 100P_0402_50V8J
DMN66D0LDW-7_SOT363-6 BATT_BLUE_LED#
<36> PWR_SUSP_LED 5 +3VALW 1 7585@ 2 2 1 BATT_BLUE_LED# <36>
Q26B R499 2.2K_0402_5% B
2

KSI2 C765 1 2 100P_0402_50V8J KSO0 C766 1 2 100P_0402_50V8J Change to SC591NB5A30 for BC bin
4

R490
KSO9 C767 1 2 100P_0402_50V8J KSI5 C768 1 2 100P_0402_50V8J 100K_0402_5% LED4
HT-191UD5_AMBER
KSI3 C769 1 2 100P_0402_50V8J KSI6 C770 1 2 100P_0402_50V8J
1

+3VALW 1 7585@ 2 2 1 BATT_AMB_LED# BATT_AMB_LED# <36>

KSO8 C771 1 2 100P_0402_50V8J KSI7 C772 1 2 100P_0402_50V8J R498 3.9K_0402_5% A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 37 of 55
 A B C D E

ON/OFF switch Power Button PX MODE SELECT CONTROL <AMD Suggestion>

+3VS
+3VALW +3VS +3VS
TOP Side INT_VGA_EN# keeps HIGH if PX is enable
SG@
1 2 D46 RB751V_SOD323

2
R493 @ 10K_0603_5% 1 2
<26> INT_VGA_EN#

2
R500 R502 R324
1 2 R495 1.8K_0402_5%
1 R494 @ 10K_0603_5% 100K_0402_5% 100K_0402_5% 1
100K_0402_5% @ @ Q74A @ Q74B @

1
Bottom Side EN1# DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6

1
@ SW3 D12 6 1 4 3 1 SG@ 2
<13> AUX0N PE_GPIO2 <23>

1
SMT1-05-A_4P D R513 0_0402_5%
2 ON/OFF <36>
1 3 ON/OFFBTN# 1 EN1 2 Q70
3 G @
51ON# <43>

5
2 4 S 2N7002_SOT23 EN1

3
DAN202UT106_SC70-3 Pop for PX verify

3
EN1#
6
5

5
C773 Q73A Q73B
ON/OFFBTN# <37>
2 @ 5 @
<26> PX_EN#
1000P_0402_50V7K 6 1 4 3
1 <13,23> GMCH_LCD_DATA
DMN66D0LDW-7_SOT363-6

4
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
Q75A @ Q75B @

1
D
EC_ON 2 Q27
<36> EC_ON
G AUX0N 1 @ 2 PE_GPIO2 Verify only
2

S 2N7002_SOT23 R514 0_0402_5%

3
R496

10K_0402_5%
1

AUX0N I2C_DATA
PX_EN# INT_VGA_EN# DISPLAY OUTPUT
EDP_DISABLED EDP_ENABLED

IGP only mode 1 X X 0 IGP( LVDS,EDP,VGA,DP)

2 2

VGA only mode 1 X X 1 VGA( LVDS,EDP,CRT,DP)

PX (MUXED) 0 0/1 0/1 1 VGA/IGP(CRT, LVDS, EDP); MXM(DP)

VGA Power ON Circuit
PX (MUXLESS) 0 X X 0 IGP( LVDS,EDP,CRT,DP)

+3VALW +3VALW

U30A U30B
SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14

14

For PX sequence and internal clock mode, VGA

P

1 I O 2 3 I O 4 PWR need ramp up after SB_CLK oscillate

G

G
7

SB_PWROK

3 +3VALW +3VALW
38ms 3
Delay EC_PWROK 50ms SB_CLK
for VGA criterial INT@
U30C U30D
14

14

<36> INT_VGAPWR_ON 1 2
R512 0_0402_5% SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 50ms
VGAPWR_ON
P

1 2 5 6 9 8 VGA_PWR_ON_L
<22,36,42,50> VGA_ON I O I O
R501 0_0402_5% 2
G

EXT@ C775
7

0.1U_0402_16V4Z
1 GPIO1_DELAY
For PX sequence, >1mS delay is required between
2

R509
0_0402_5%
PE_GPIO1 and VGA_PWR_ON
+3VS +3VALW +3VALW DISO@
C776
1
1

1 2 0.1U_0402_16V4Z
R415 PE_GPIO1
31.6K_0402_1% U30E U30F
For VGA Power on control
14

14

R414 SG@ @ SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 >1ms

10K_0402_1%
P

P
2

1 2 11 10 13 12 1 SG@ 2
<26,42> PE_GPIO1 I O I O VGA_PWR_ON <42,50,51>
R505 0_0402_5%
G

2 2 VGA_PWR_ON
1

D Q66 C778 C777

Pop for PX verify
7

2 SG@ 0.1U_0402_16V4Z
<42> PE_GPIO1#
G 0.1U_0402_16V4Z @
2N7002_SOT23
S 1 1
3

4 4
1

D Q76
GPIO1_DELAY 2 INT@
G
2N7002_SOT23
S
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 38 of 55
A B C D E
 A B C D E F G H

1 2
R784 0_0805_5%
+3VS +VDDA

+5VAMP
U81
60mil 40mil

1
+5VS L87 1 2 1 IN

1
R783 5 +VDDA 4.75V
OUT

C678

C899

C947
D38 20K_0402_1% FBMA-L11-201209-221LMA30T_0805 2
R789 L88 1 GND
2 1 1 1
RB751V_SOD323 10K_0402_5% 3 4 1 2

2
1 C936 FBMA-L11-201209-221LMA30T_0805 SHDN BYP C949 1

22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 2 MONO_IN @ @ G9191-475T1U_SOT23-5 0.01U_0402_25V7K
1U_0402_6.3V4Z 2 2 2

1
R786
2 HD Audio Codec (output = 300 mA)

1
C 2.4K_0402_1%
C952 1 R787 Q72
<36> BEEP# 2 1 2 2
1U_0402_6.3V4Z B
560_0402_5% E

3
2SC2411KT146_SOT23-3

C946 1 R788
<27> SB_SPKR 2 1 2
1U_0402_6.3V4Z

1
560_0402_5%
D37
RB751V_SOD323

L82
2 10mil BLM18AG601SN1D_2P
0.1U_0402_16V4Z +3VS_DVDD 1 2 +3VS MIC2_VREFO
1 1 1
C933 C953 C926
+AVDD_HDA

1
10U_0805_10V4Z
L86 2 2 2 R585
1 2 0.1U_0402_16V4Z 40mil 2.2K_0402_5%
+VDDA
BLM18AG601SN1D_2P 1 1 1 0.1U_0402_16V4Z
C935 C945

2
C950 Close to Conn
2 10U_0805_10V4Z INT_MIC 2

25

38

9
2 2 2 U82
0.1U_0402_16V4Z 1

DVDD
AVDD1

AVDD2

DVDD_IO
C808
220P_0402_50V7K
AMP_LEFT 2
14 LINE2_L LOUT1_L 35 AMP_LEFT <40>
15 36 AMP_RIGHT
LINE2_R LOUT_R AMP_RIGHT <40>
C794 1 2 MIC2_C_L 16 39
INT_MIC MIC2_L LOUT2_L
2 1INT_MIC_2 4.7U_0805_10V4Z JP1
R523 1K_0402_1% C797 1 2 MIC2_C_R 17 41 INT_MIC 1
4.7U_0805_10V4Z MIC2_R LOUT2_R 1
15mil 2 2
23 LINE1_L SPDIFO2 45

2
24 LINE1_R DMIC_CLK1/2 46 3 G1
D27 4 G2
18 LINE1_VREFO NC 43
@ ACES_88266-02001
20 LINE2_VREFO DMIC_CLK3/4 44 1 2 1 2 C948 CONN@
R792 0_0402_5% 22P_0402_50V8J For EMI PJDLC05C_SOT23-3
MIC2_VREFO 19 MIC2_VREFO
BITCLK 6 HDA_BITCLK_AUDIO <27>
MIC1_L C934 1 2 MIC1_C_L 21
<40> MIC1_L

1
4.7U_0805_10V4Z MIC1_L
MIC1_R C932 1 2 MIC1_C_R 22 8 1 2 HDA_SDIN0 <27>
<40> MIC1_R MIC1_R SDATA_IN
4.7U_0805_10V4Z R793 33_0402_5%
MONO_IN 12 37
PCBEEP_IN MONO_OUT

CBP 29
11 2.2U_0402_6.3V6M
3 <27> HDA_RST_AUDIO# RESET# 3
31 C951 1 2
CPVEE
<27> HDA_SYNC_AUDIO 10 SYNC 10mil 1
MIC1_VREFO 28 MIC1_VREFO
<27> HDA_SDOUT_AUDIO 5 C954 HP_RIGHT
SDATA_OUT HP_RIGHT <40>
32 HP_RIGHT 2.2U_0402_6.3V6M
HPOUT_R 2 HP_LEFT
2 GPIO0/DMIC_DATA1/2 HP_LEFT <40>
3 GPIO1/DMIC_DATA3/4 CBN 30
R794 2 1 20K_0402_1% SENSE_A 13 10mil
<40> MIC_PLUG# SENSE A
R795 2 1 5.11K_0402_1% SENSE_B 34 27 CODEC_VREF
<40> HP_PLUG# SENSE B VREF
1 1

10U_0805_10V4Z

0.1U_0402_16V4Z
<36> EAPD 1 2 47 EAPD JDREF 40

20K_0402_1%

C927

C937
R796 0_0402_5%

1
48 33 HP_LEFT
SPDIFO1 HPOUT_L 2 2

R797
4 DVSS1 AVSS1 26
7 DVSS2 AVSS2 42

2
ALC272-VA2-GR_LQFP48_7X7 1 2 1 2
Change to ALC272X R798 0_0805_5% R799 0_0805_5%

DGND AGND
1 2 1 2
R804 0_0805_5% R816 0_0805_5%
ALC272X
Sense Pin Impedance Codec Signals Function 1 2 1 2
R818 0_0805_5% R817 0_0805_5%
39.2K PORT-A (PIN 39, 41) LOUT2
20K PORT-B (PIN 21, 22) MIC1
SENSE A
10K PORT-C (PIN 23, 24) LINE1 GND GNDA GND GNDA
4 4

5.1K PORT-D (PIN 35, 36) LOUT1

39.2K PORT-E (PIN 14, 15) LINE2
20K PORT-F (PIN 16, 17) MIC2
SENSE B
10K Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-I (PIN 32, 33) HP Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 39 of 55
A B C D E F G H
 A B C D E

GAIN0 GAIN1 AV(inv) Ri

0 0 6dB 90k +5VAMP
0.1U_0402_16V4Z
0 1 10dB 70k
1 0 15.6dB 45k 1 1 Int. Speaker Conn.
1 1 21.6dB 25k C959 C960
10U_0805_10V4Z
2 2
1 JSPK2 1
SPKL+ R834 1 2 0_0603_5% SPK_L+ 1
SPKL- R833 1 SPK_L- 1
10 dB 2 0_0603_5% 2 2
+5VAMP 20mil Left

2
1

1
D39

16
15
3 G1

6
U83 R827 @ R829 4
100K_0402_5% 100K_0402_5% @ G2

VDD
PVDD1
PVDD2
ACES_88266-02001
PJDLC05C_SOT23-3 CONN@

2
SCA00001100
C958 1 2 0.47U_0603_10V7K 7 2 GAIN0
RIN+ GAIN0

1
3 GAIN1
C957 GAIN1

1
1 2 1 2 AMP_C_RIGHT 17
<39> AMP_RIGHT R830 0_0603_5% RIN- SPKR+ @ R825 R826
ROUT+ 18
0.47U_0603_10V7K 100K_0402_5% 100K_0402_5% JSPK1
SPKR+ R831 1 2 0_0603_5% SPK_R+ 1
SPKR- SPKR- R832 1 1
14 2 0_0603_5% SPK_R- 2

2
C955 1 ROUT- 2
2 0.47U_0603_10V7K 9 LIN+ 20mil

2
LOUT+ 4 SPKL+ D41 3 G1
Right
C971 4
AMP_C_LEFT @ G2
<39> AMP_LEFT 1 2 1 2 5 LIN-
R828 0_0603_5% 8 SPKL- ACES_88266-02001
0.47U_0603_10V7K LOUT- PJDLC05C_SOT23-3 CONN@
SCA00001100

1
NC 12
2 2
EC_MUTE# BYPASS 10 Keep 10 mil width
<36> EC_MUTE# 19 SHUTDOWN
2

GND5
GND1
GND2
GND3
GND4
C956
0.47U_0603_10V7K
1
21
20
13
11
1 TPA6017A2_TSSOP20

2 2
C779 C774

330P_0402_50V7K 330P_0402_50V7K
Headphone Out
1 1 JHP1
1
<39> HP_LEFT R686 1 2 56.2_0603_1% HPOUT_L_1 1 2 HPOUT_L_2 2
L94 FBMA-L11-160808-700LMT_2P
<39> HP_RIGHT R685 1 2 56.2_0603_1% HPOUT_R_1 1 2 HPOUT_R_2 3
L93 FBMA-L11-160808-700LMT_2P
4

HP_PLUG# 5
<39> HP_PLUG#

SINGA_2SJ-0960-C01
3 CONN@ 3
MIC_PLUG# <NAL00 use>
HP_PLUG#

2
MIC1_VREFO MIC1_VREFO
@ D24

2
PJDLC05C_SOT23-3
SCA00001100
D43 D42
RB751V_SOD323 RB751V_SOD323

1 1

1 1

1
R692 R693
MIC JACK
4.7K_0402_5%
4.7K_0402_5% JMIC1

2
1
R694 1 2 MIC1_L_1 L89 1 2 MIC1_L_R 2
<39> MIC1_L
1K_0603_1% FBMA-L11-160808-700LMT_2P
R695 1 2 MIC1_R_1 L90 1 2 MIC1_R_R 3
<39> MIC1_R
1K_0603_1% FBMA-L11-160808-700LMT_2P

2
1 1 4

C780 C781 MIC_PLUG# 5

<39> MIC_PLUG#
220P_0402_50V7K 220P_0402_50V7K
2 2
@
PJDLC05C_SOT23-3 D29 6
4 SCA00001100 4
SINGA_2SJ-A960-C01

1
CONN@
<NAV70 use>

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 40 of 55
A B C D E
 FAN1 Conn
+5VS
+5VS
C821 10U_0805_10V4Z

1
1 2
2 D25
@ 1SS355_SOD323-2
R566
0_0603_5%

2
@ U35 @ D26 BAS16_SOT23-3
1 8 1 2
1

EN GND
2 VIN GND 7
+VCC_FAN1 3 6
VOUT GND C823
<36> EN_DFAN1 1 2 4 VSET GND 5
R567 0_0402_5% 1 10U_0805_10V4Z
C822 APL5607KI-TRG_SO8 1 2
@
0.01U_0402_25V4Z +3VS C824
2 1000P_0402_50V7K
1 2

1
R568
10K_0402_5%
40mil JFAN1

2
+VCC_FAN1
1
<36> FAN_SPEED1 2
3
1
C825 CONN@
1000P_0402_50V7K ACES_85205-03001
2
LDO FAN

H1 H2 H4 H5 H6 H7 H8 H9 H10
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

1
H11 H12 H19 H24 H20 H21 H22 H23
H_3P0 H_3P0 H_3P0 H_3P0 H_4P2 H_4P2 H_4P2 H_4P2

1
H14 H15 H18 H17 H13
H_4P0 H_4P0 H_3P4 H_3P0X3P5N H_3P0N

1
FD1 FD2 FD3 FD4

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 41 of 55
 A B C D E

+5VALW TO +5VS +5VALW

+5VALW +5VS
+1.1VALW TO +1.1VS +5VALW

2
U36 +1.1VALW +1.1VS

2
SI4800BDY-T1-GE3_SO8 U38 R570
8 1 AO4430L_SO8 R583 100K_0402_5%
7 2 8 1 100K_0402_5%

2
6 3 1 1 7 2

1
2
1 1 5 C827 R571 6 3 1 1

1
1
C826 C828 470_0603_5% 1 5 C838 R578 VLDT_EN# SYSON#
<35> SYSON#
10U_0805_10V4Z C829 R577 C837

1
10U_0805_10V4Z 2 2 1K_0402_5% 10U_0805_10V4Z C839 470_0603_5% D

1
2 2
10U_0805_10V4Z 1U_0402_6.3V4Z 2 2 D Q30
<36,47> SYSON 2

1
2 1U_0402_6.3V4Z Q40 G 2N7002_SOT23
<36,48> VLDT_EN 2

2
1

1
D 10U_0805_10V4Z G 2N7002_SOT23 S

3
1

1
1 D 1
2 SUSP S R573

3
G 2VLDT_EN# 100K_0402_5%
+VSB 1 2 5VS_GATE S Q31 G R584

3
R574 100K_0402_5% 2N7002_SOT23 +VSB 1 2 1.1VS_GATE S Q37 10K_0402_5%

2
1 R581 47K_0402_5% 2N7002_SOT23

2
1
D C834
+5VALW

300K_0402_5%
SUSP 2 1

1
Q33G 0.1U_0603_25V7K D C844 +5VALW
2

R595
2N7002_SOT23 S VLDT_EN# 2
3

2
Q39G 0.1U_0603_25V7K

2
2N7002_SOT23 S 2 R576

3
R587 100K_0402_5%

1 2
100K_0402_5%
D

1
ACIN 2 Q48 SUSP
+3VALW TO +3VS <16,36,37,43> ACIN <22,49> SUSP

1
G 2N7002_SOT23 VGA_ON#
<22> VGA_ON#
+3VS S

1
+3VALW D

1
U39 D Q35
<22,36,46> SUSP# 2
SI4800BDY-T1-GE3_SO8 <22,36,38,50> VGA_ON 2 Q42 G 2N7002_SOT23

1
8 1 G 2N7002_SOT23 S

3
1
7 2 S

3
2
6 3 R580

C840
1
C841
1 5 C842
1 1
R579
470_0603_5%
+1.5V to +1.5VSG R586
10K_0402_5%
10K_0402_5%

2
10U_0805_10V4Z C836 +1.5V +1.5VSG
4

2
10U_0805_10V4Z 2 2

1 1
2 2
10U_0805_10V4Z 1U_0402_6.3V4Z U37 VGA@
D AO4430L_SO8
2 SUSP 8 1 +5VALW
G 7 2

2
+VSB 2 1 3VS_GATE S Q36 6 3 1 1
3

2
2 R582 200K_0402_5% 2N7002_SOT23 C832 C833 R572 2
1 1 5
C830 C831 VGA@ VGA@ VGA@ R589
1

D VGA@ 10U_0805_10V4Z 470_0603_5% 100K_0402_5%

1

4
SUSP C843 VGA@ 2 2
1U_0402_6.3V4Z
2

1
Q38G 2 2

1
2N7002_SOT23 S 0.1U_0603_25V7K 10U_0805_10V4Z 10U_0805_10V4Z PE_GPIO1#
<38> PE_GPIO1#
3

1
2 D
2VGA_PWR_ON#

1
G D
+VSB 1 VGA@ 2 1.5VSG_GATE S Q32 <26,38> PE_GPIO1 2 Q67

3
R575 100K_0402_5% 2N7002_SOT23 G 2N7002_SOT23
+1.5VS

1
VGA@ S

3
510K_0402_5%
1 R609

1
D

VGA@ R596
Q59 VGA@ C835 100K_0402_5%
+1.5V SI2301CDS-T1-GE3_SOT23-3 +1.5VS VGA_PWR_ON# 2 VGA@ 1 2 VGA@
R503 47K_0402_5% G 0.1U_0603_25V7K

2
2
S

Q34
D

3 1 S

3
1 2N7002_SOT23

2
2

C848 +5VALW
1
R314 C690 R313 VGA@
G
2

1
470_0603_5% 0.1U_0603_25V7K D

2
100K_0402_5% 10U_0805_6.3V6M 2 ACIN 2 Q49
2 G VGA@ R602
1

S 2N7002_SOT23 100K_0402_5%

3
1

1
2 VGA_ON# VGA_PWR_ON#
1

R511 D G
VGA_ON 2 1 2 Q9 S Q10
3

1
47K_0402_5% G 2N7002_SOT23 D
1
S 2 Q68
+1.8VS to +1.8VSG <38,50,51> VGA_PWR_ON
3

C691 SSM3K7002FU_SC70-3 G 2N7002_SOT23

1
3 S 3

3
0.22U_0603_16V4Z2 R608
100K_0402_5%
+1.8VS +1.8VSG
U45 VGA@

2
SI4800BDY-T1-GE3_SO8
8 1
7 2

2
6 3 1 1
1 1 5 C855 R594
+1.0VSG +VGA_CORE +1.8VS C856 C854 VGA@ VGA@
10U_0805_10V4Z C853 470_0603_5%
4

VGA@ VGA@ 2 2 VGA@

1
2

2 2 1U_0402_6.3V4Z Q58
R598 R603 R592 10U_0805_10V4Z 10U_0805_10V4Z +3VSG +3VS SI2301CDS-T1-GE3_SOT23-3 +3VSG

1
470_0603_5% 470_0603_5% 470_0603_5% D

S
VGA@ VGA@ VGA_PWR_ON#

D
2 3 1
G
1

2
+VSB 2 VGA@ 1 1.8VSG_GATE S Q43 VGA@ C849 1 1

3
R510 100K_0402_5% 2N7002_SOT23 VGA@ R114 VGA@ C234 R112

G
2
1

D D D VGA@ 470_0603_5%

3VSG_GATE
510K_0402_5%

2 VGA_PWR_ON# 2 VGA_PWR_ON# 2 VGA_ON# 1 0.1U_0603_25V7K 100K_0402_5% 10U_0805_6.3V6M VGA@

1

D 2 2
@ R606

G G G C852

1
S Q51 S Q55 S Q46 VGA_PWR_ON# 2 VGA@ 1 2 VGA@ 3VSG_GATE 1 2
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 R489 100K_0402_5% G 0.1U_0603_25V7K R611 33K_0402_5%

1
VGA@ VGA@ Q47 2 D VGA@
1 S
3

2N7002_SOT23 2 VGA_PWR_ON#
2

1
C692 VGA@ VGA@ D VGA@ G
VGA@ VGA_PWR_ON 1 2 2 Q8 S Q7

3
1

2
0.1U_0603_25V7K D 10K_0402_5% R607 1 G 2N7002_SOT23
+1.5V +2.5VS +0.75VS +CPU_VDDR +NB_CORE ACIN 2 Q60 S

3
G @ C846 SSM3K7002FU_SC70-3
4 S 2N7002_SOT23 VGA@ 4
3
2

2
0.1U_0603_25V7K
R605 R590 R591 R604 R610
470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
1

Security Classification Compal Secret Data Compal Electronics, Inc.

1

D D D D D
2 SYSON# 2 SUSP 2 SUSP 2 VLDT_EN# 2 VLDT_EN# Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title
G G G G G
S Q57 S Q44 S 2N7002_SOT23 S Q56 S Q69 SCHEMATIC, MB A5911
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2N7002_SOT23 2N7002_SOT23 Q45 2N7002_SOT23 2N7002_SOT23 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 42 of 55
A B C D E
 A B C D

PR1
1M_0402_1%
1 2
VIN VIN
VS

1
1 1

VIN PR2
10K_0402_5%
PR3
84.5K_0402_1%
PR4
SP02000GC00

8
ACES_50305-00441-001 PL1 PR5 PU1A 22K_0402_5%

2
SMB3025500YA_2P 10K_0402_1% 3 1 2

P
DC_IN_S1 PACIN +
1 1 1 2 1 2 1 O
<16,36,37,42> ACIN

1
2 2 - 2

1
G
3 <BOM Structure> PC1
3

1
4 LM393DR_SO8 PR7 1000P_0402_50V7K

4
4 PD1 PC2 20K_0402_1%
5

2
GND

1
6 PR8 RLZ4.3B_LL34 0.1U_0603_25V7K

2
GND PC3 PC4 PC5 PC6 10K_0402_5%
PJP1 1000P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7K

2
PR9
10K_0402_5%
1 2
RTCVREF
<46,49> PACIN

Vin Dectector
Min. Typ Max.
H-->L 16.976V 17.525V 17.728V
2
L-->H 17.430V 17.901V 18.384V 2

PJ32
2 1 PJ29
+1.0VSGP 2 1 +1.0VSG
2 1
- + +1.8VSP2 2 1 +1.8VS

2
PBJ1 @PC148
@ PC148 JUMP_43X118

2
0.1U_0402_16V7K (3A,120mils ,Via NO.=6) @ PC130
@PC130 JUMP_43X118
2 1 +RTCBATT 0.1U_0402_16V7K (3A,120mils ,Via NO.=6)

1
+RTCBATT

1
ML1220T13RE PJ1 PJ22
45@ +3VALWP 2 2 1 1 +3VALW +1.8VSP1 2 2 1 1 +1.8VS

2
@ PC7
@PC7 JUMP_43X118 @ PC71
@PC71 JUMP_43X118
0.1U_0402_16V7K (3.9A,160mils ,Via NO.= 8) 0.1U_0402_16V7K (3A,120mils ,Via NO.=6)

1
VIN 2
PJ3
1 2
PJ26
1
+5VALWP 2 1 +5VALW +1.1VALWP 2 1 +1.1VALW

2
@ PC9
@PC9 JUMP_43X118 @ PC8
@PC8 JUMP_43X118
2

0.1U_0402_16V7K (5A,200mils ,Via NO.= 10) 0.1U_0402_16V7K (5.2A,220mils ,Via NO.=11)

PD2

1
RLS4148_LL34-2
PD3
RLS4148_LL34-2 PJ11
PJ5
1

+0.75VSP 2 2 1 1 +0.75VS
BATT+ 2 1 +VSBP 2 2 1 1 +VSB
1

2
3 3

@ PC10
@PC10 JUMP_43X118

2
PR10 PR11 PC11 JUMP_43X39 0.1U_0402_16V7K (3A,120mils ,Via NO.=6)
68_1206_5% 68_1206_5% 0.1U_0402_25V6 (120mA,40mils ,Via NO.= 2)

1
1
PR12 PQ1
2

200_0603_5% PJ6
CHGRTCP 1 2 N1 3 1 PJ8 +1.5VP 2 1 +1.5V
VS +NB_COREP 2 2 1 1 +NB_CORE
2 1

2
@PC12
@ PC12 JUMP_43X118
1

2
@ PC15
@PC15 JUMP_43X118 0.1U_0402_16V7K
1

PR13 PC13 0.1U_0402_16V7K PJ19

1
100K_0402_1% 0.22U_0603_25V7K PC14 2 1

1
0.1U_0603_25V7K 2 1
2

PR14 TP0610K-T1-E3_SOT23-3 JUMP_43X118

2

22K_0402_1% (5A,200mils ,Via NO.=10)

1 2 (9.5A,400mils ,Via NO.=20)
<38> 51ON# PJ9
+2.5VSP 2 2 1 1 +2.5VS

2
@PC16
@ PC16 JUMP_43X39
RTCVREF 0.1U_0402_16V7K
1

1
PR15
200_0603_5% PJ21
PR16 PR17 PU2 JUMP_43X39
560_0603_5% 560_0603_5% 3.3V PJ20
+CPU_VDDRP 1 2 2 +CPU_VDDR
2

N2 1
1 2 1 2 3 OUT IN 2 +VGA_COREP 2 2 1 1 +VGA_CORE

2
+CHGRTC 2 PC70
@ PC69
@PC69 JUMP_43X118 0.1U_0402_25V6 (1.5A,60mils ,Via NO.= 3)
1

GND PC18 0.1U_0402_16V7K PJ13

1
4
PC17 G920AT24U_SOT89-3 1U_0805_25V4Z 2 2 4

1 1
1

10U_0805_10V4Z 1
2

JUMP_43X118

(25A,1000mils ,Via NO.=50)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 43 of 55
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C

VL

GND 10
1
GND 9 1

8 VL
8
7 7

21K_0402_1%
6 EC_SMDA
6

1
5 EC_SMCA
5

2
PR28
4 TH PR29 PC21 PR27
4 PI 100_0402_1% 0.1U_0603_25V7K 10K_0402_1% PR21 @
3

2
3 100K_0402_1%
2 2
1 <40,41>

2
1 PU3

1
2
PJP2
VMB 1 VCC TMSNS1 8

2
SUYIN_200275GR008G13GZR PR32
100_0402_1% 2 7 PR30
CONN@ EC_SMB_DA1 <36> GND RHYST1
PL2 9.53K_0402_1%
SMB3025500YA_2P
<40,41> 3 6

1
OT1 TMSNS2

2
BATT_S1 1 2 BATT+

1
1

1
4 OT2 RHYST2 5
PH1
EC_SMB_CK1 <36>
1

1
G718TM1U_SOT23-8
PC20 PC19 PR261 100K_0402_1%_NCP15WF104F03RC

1
1000P_0402_50V7K 0.01U_0402_25V7K 1K_0402_5% @PR169
@ PR169
2

2
PR24
6.49K_0402_1% 47K_0402_1%
2 1 +3VALWP MAINPWON <8,45,49>

1
100K_0402_1%_NCP15WF104F03RC
PH2 @

1
PR33
1K_0402_1%

2
2
2 2

BATT_TEMP <36>

PQ3 TP0610K-T1-E3_SOT23-3

B+ 3 1 +VSBP
0.22U_0603_25V7K

0.1U_0603_25V7K
1

1
PC24

PC25

PR34
100K_0402_1% @ @
2

3 3
2

VL
1 2
PR36
22K_0402_1%
2

PR38
100K_0402_1%

PR39
1

0_0402_5% D
1 2 2 PQ4
<45,47> SPOK G 2N7002W-T/R7_SOT323-3
0.1U_0402_16V7K

S
3
1

PC27

@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 44 of 55
A B C D
 5 4 3 2 1

TPS51427_B+
TPS51427_B+

PR50
PJ12 0_0805_5%
2 1 1 2
B+ 2 1

2200P_0402_50V7K

2200P_0402_50V7K
JUMP_43X118

10U_1206_25V6M

10U_1206_25V6M
1
2200P_0402_25V7K

2200P_0402_25V7K

5
6
7
8
PC45
D D
2

8
7
6
5

1
PC122

PC31

PC28

PC30
VL

2
PC120

1U_0603_10V6K
PQ6
1

2
2
PQ5 PC40 AO4466_SO8

4.7U_0603_6.3V6M
AO4466_SO8 0.1U_0603_25V7K 4

1
PC41
4

PC29
1
+5VALWP

3
2
1
PL4

1
2
3
PL3 4.7UH_SIL1045R-4R7PF_6.3A_30%

7
4.7UH_SIL1045R-4R7PF_6.3A_30% PU4 PC36 2 1
1 2 1U_0603_10V6K

VIN

V5FILT

LDO
+3VALWP 33 19 1 2
TP V5DRV

5
6
7
8

4.7_1206_5%
1

8
7
6
5

PR43
DH3 26 15 DH5
PR41 PR40 DRVH2 DRVH1 PR47 2.2_0603_5% PQ8
4.7_1206_5% PQ7 2 1 BST3A 24 VBST2 VBST1 17 BST5A 2 1 AO4712_SO8
1

66.5K_0402_1%
1 AO4712_SO8 2.2_0603_5%

2
2

2
PR42 PC42 4

PR49
PC39 + 0_0402_5% 4 PC43 0.1U_0603_25V7K

2
680P_0402_50V7K
220U_6.3V_M 0.1U_0603_25V7K

1
1
LX3 25 16 LX5 1
2

2 LL2 LL1

PC34
PC37 @

3
2
1

2
680P_0402_50V7K + PC35

1
2
3
DL3 23 18 DL5 220U_6.3V_M

1
DRVL2 DRVL1
2
2

0_0402_5%
PGND 22

2
FB3 30 VOUT2

PR48
@ PR44
@PR44
C 10K_0402_1% C
VOUT1 10
VL 32
1

REFIN2

1
11 FB5
2VREF_TPS51427 FB1

1 2 1 VREF2
PC47 0.22U_0603_10V7K
VSW 9
8 LDOREFIN @PR59
@ PR59 0_0402_5%
SKIPSEL 29 2 1 VL
+3.3VALWP Ipeak=5.9A ; Imax=4.1A;Iocp=6.6A
PR45 0_0402_5%
Choke DCRmax=23m ohm, 1 2
Rds(on)=18m ohm(max) ; Rds(on)=15m 20 NC PGOOD2 28
PD17 PR46
ohm(typical) GLZ5.1B_LL34-2 100K_0402_1%
Vlimit=(5E-06 * 294K)/10=147mV 1 2 1 2 4 13 SPOK <44,47>
VS EN_LDO PGOOD1 PR60
Ilimit=147mV/18m ~ 147mV/15m
2
200K_0402_5%

330K_0402_1%
2

=8.17A ~ 9.8A
PR58

14 EN1 TRIP1 12 2 1
PC44
Delta I=1.94A (Freq=300KHz) 0.22U_0603_25V7K

TONSE
VREF3
1

Iocp=Ilimit+Delta I/2 27 31 ILIM2 2 1

GND
1

EN2 TRIP2
1

=9.14A ~ 10.77A

0_0402_5%
PD16 PR57
VL

2
1SS355_SOD323-2 @ PR56
@PR56 SN0806081RHBR_QFN32_5X5 294K_0402_1%

21
PR51
0_0402_5%
2
2

B PR52 B
1

1
1U_0603_10V6K
806K_0603_1% 2VREF_TPS514271 +5VALWP Ipeak=7A ; Imax=5A;Iocp=8.4A
PR54 @ PR55
@PR55 PR53 Choke DCRmax=23m ohm
1

2
PC143
0_0402_5% 47K_0402_5% 0_0402_5% Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
2 1 1 2
Vlimit=(5E-06 * 330K)/10=165mV

2VREF_TPS514272
<8,44,49> MAINPWON
1
0.047U_0402_16V7-K

Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
1

PC38

Delta I=1.96A (Freq=400KHz)

Iocp=Ilimit+Delta I/2
2

=9.729A ~ 11.562A
@ PC46
@PC46
3

0.047U_0402_16V7K
2

2 PQ37
TP0610K-T1-E3_SOT23-3
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 45 of 55
5 4 3 2 1
 A B C D

Iada=0~4.74A(90W/19V=4.736A) B+
CP = 85%*Iada ; CP = 4.03A

PQ14 P2 PQ15 P3 B+ CHG_B+

PQ16
AO4407_SO8 AO4407_SO8 PJ23 AO4407_SO8
VIN 8 1 1 8 1 4 2 2 1 1 1 8
7 2 2 7 PR61 2 7
1 6 3 3 6 2 3 0.02_2512_1% JUMP_43X118 CSIN 3 6 1

5 5 5

2200P_0402_25V7K
10U_1206_25V6M

10U_1206_25V6M

0.1U_0603_25V7K
5600P_0402_25V7K
CSIP PR63

4
1

1
PC50

PC51
47K_0402_1%
VIN

PC48

PC61
PQ17 TP0610K-T1-E3_SOT23-3 1 2

PC56

2
1

3 1 DCIN PD8

1
P3

2
PR62 1SS355TE-17_SOD323-2

1
100K_0402_1%
0.1U_0603_25V7K
47K_0402_1% PR65 1 2 ACOFF

1
PR94 PQ18 10K_0402_1%

1
PC62

PR64
200K_0402_1% PDTC115EU_SOT323
2

PR67
2

1 1
PD9 200K_0402_1%

2
PR66 2 FSTCHG 1 2 VIN
FSTCHG <36>

2
3

PD10 2 1 2 1
47K PQ19 1SS355TE-17_SOD323-2 3 SUSP# PD11
PDTA144EU_SOT323-3 1 2 6251VDD 100K_0402_1% SUSP# <22,36,42> PQ20 1SS355TE-17_SOD323-2

2.2U_0603_6.3V6K
2 47K BAS40CW_SOT323-3 PDTC115EU_SOT323 2 1 2

PC49
PR68

3
1
10K_0402_5% wrong Value
FSTCHG 2 1 PU5 PC127
1

0.1U_0603_25V7K
0.1U_0603_25V7K

1
PQ21 1 2 1 24 DCIN 2 1 PQ23D
1

VDD DCIN
1

1
100K_0402_1%
PDTC115EU_SOT323

PC52
PR70 47K_0402_5% PC67 2 PACIN
6251VDD 1 2 0.1U_0402_16V7K 2N7002W-T/R7_SOT323-3
G

PR71
2 PR69 2 23 S

3
ACSET ACPRN

1
150K_0402_1% PR72
2N7002W-T/R7_SOT323-3

PQ24 20_0402_5%
2

2
1

PQ22 D PDTC115EU_SOT323 6251_EN CSON

3 EN CSON 22 1 2

2
2 PC53
3

5
6
7
8
G 2 0.047U_0603_16V7K
<36> 3S/4S#
2
S 4 21 1 2 CSOP PQ55 2
3

1
CELLS CSOP PR73

AO4466_SO8
PC54 6800P_0402_25V7K 20_0402_5%
1 2 5 20 2 1
3

ICOMP CSIN
1

2
PQ56 D 2N7002W-T/R7_SOT323-3 PR74 4
PC129 20_0402_5%
2
G 1 2 1 PR75 2 10K_0402_1% 6 19 0.1U_0603_25V7K
1 2
<40,41>

1
PR77 VCOMP CSIP PR76 PL5
S
3

PC55 1 2 100_0402_1% 2_0402_5% 10UH_PCMB104T-100MS_6A_20% PR78 0.02_1206_1% BATT+

3
2
1
ACON 0.01U_0402_25V7K PC57 1 2 7 18 LX_CHG 1 2 CHG 1 4
<49> ACON ICM PHASE

4.7_1206_5%
@ 100P_0402_50V8J

5
6
7
8

1
<36> ADP_I 2 3

PR80
PR79 PC58 6251VREF 8 17 DH_CHG
22K_0402_5% PR81 VREF UGATE PR82 PC59
1 2

10U_1206_25V6M

10U_1206_25V6M
PACIN 1 2 80.6K_0402_1% 0_0603_5% 0.1U_0603_25V7K PQ57
<43,49> PACIN
2 1 0.1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1 @

2
<36> IREF CHLIM BOOT

AO4466_SO8
0.01U_0402_25V7K

4
1

1
PC68

PC63
PQ53 PR84 PD12

680P_0402_50V7K
PC60

PDTC115EU_SOT323 PR83 6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2

ACLIM VDDP

PC128
100K_0402_1%
2

2
1
2.55K_0402_1%
PR85

12.1K_0402_1% 20K_0402_1% 1 26251VDD

3
2
1

2
ACOFF 2 PR87 11 14 DL_CHG
<36,49> ACOFF
2

VADJ LGATE
1

2
PR86 @
4.7_0603_5%
12 13 PC64
2

1
GND PGND 4.7U_0805_6.3V6K
3

2
1

PQ54 D ISL6251AHAZ-T_QSOP24
2
<36> 65W/90W# G 2N7002W-T/R7_SOT323-3
S
3

3 3

VMB
<40,41>
PR88
15.4K_0402_1%

1
Iada=0~4.74A(90W) CP= 85%*Iada; CP=4.03A <36> CALIBRATE#
1 2
2

Iada=0~3.42A(65W) CP= 85%*Iada; CP=2.91A VS PR89

PR90 LI-3S :13.5V----BATT-OVP=1.5012V 340K_0402_1%
31.6K_0402_1%

2
0.01U_0402_25V7K
BATT-OVP=0.1112*VMB
1

CP mode Per cell=4.5V

PC65

1
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
PR91

2
where Vaclm=1.464V (90W), Iinput=4.03A 499K_0402_1%
PR84=12.1K;PR87=20K
where Vaclm=0.391(65W), Iinput=2.91A

2
8
PR92 PU18B
PR84=12.1K;PR85=2.55K 10K_0402_1% LM358DT_SO8 5

P
+
IREF=0.7224*Icharge 1 2 7 0
<36> BATT_OVP 6
-

0.01U_0402_25V7K
4

1
PR93

PC66
105K_0402_1%
ADP_I = 19.9*3.42*0.95*0.02=1.29V

2
2
4 4

Charging Voltage
BATT Type (0x15) CV mode

Normal 3S LI-ON Cells

Security Classification Compal Secret Data Compal Electronics, Inc.
12600mV 12.60V Issued Date 2007/09/20 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
Size Document Number Rev
- AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, September 14, 2010 Sheet 46 of 55
A B C D
 A B C D

PJ14
1.1VALW_B+ 2 1 B+
2 1

2200P_0402_50V7K

10U_1206_25V6M
JUMP_43X118

1
PC139

PC72
5
6
7
8

2
1 1

PQ25

PR96
255K_0402_1% 4
1 2
PR97 PR98
0_0402_5% 0_0603_5%
1 2 BST_1.1VALW
1 2 AO4466_SO8

3
2
1
<44,45> SPOK
DCR= 7.5 mohm

1
PR99 PL6

15

14
1
30K_0402_5% PC74 PU6 PC75 1UH_FDUE1040D-1R0M-P3_21.3A_20%
@ @0.1U_0402_16V7K BST_1.1VALW-11 2 1 2

BOOT
NC
EN/DEM
+1.1VALWP

2
2
2 13 DH_1.1VALW 0.1U_0603_25V7K
TON UGATE

1
PR101 3 12 LX_1.1VALW
VOUT PHASE

5
6
7
8
100_0603_1% PQ26 PR100 1
+5VALW 1 2 4 11 1 2 +5VALW 4.7_1206_5%
VDD CS PR102 + PC76

2
5 10 7.32K_0402_1% 330U_6.3V_M
FB VDDP

1
DL_1.1VALW 2
6 PGOOD LGATE 9 4

PGND
PC77 PC78

GND
4.7U_0603_6.3V6K PC79 680P_0603_50V7K

2
1
@ 47P_0402_50V8J
<Vo=1.1V> VFB=0.75V 1 2 RT8209BGQW_WQFN14_3P5X3P5 PC80

3
2
1
4.7U_0805_10V6K AO4456_SO8

2
V=0.75*(1+4.7K/10K)=1.1V
Fsw=280KHz
2
PR103 2

Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm. 4.7K_0402_1%

1 2
Ipeak=7.42A, Imax=5.2A, Iocp=8.9A

1
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A
=>1/2Delta I=1.03A PR104
Vtripmax=Iocp*Rdson=8.9*5.6*1.3=0.065V 8.45K_0402_1%
Rcs=Vtrip/9uA=0.065V/9uA=7.2K 2
choose Rcs=7.32K
Iocpmax=((7.32K*11uA)/0.0045)+1.03A=19A PJ15
Iocpmin=((7.32K*9uA)/(0.0056*1.3))+1.03A=10A 1.5V_B+ 2 2 1 1 B+
Iocp=10A~19A

2200P_0402_50V7K

10U_1206_25V6M
JUMP_43X118

1
PC81

PC82
5
6
7
8
PQ27

2
PR105 0_0402_5% PR106
1 2 226K_0402_1% 4
<36,42> SYSON
1 2
PR108
0_0603_5%
BST_1.5V 1 2 AO4466_SO8

3
2
1
1

3 3

@ PR109
@PR109 PC84 PL7
15

14
1

30K_0402_5% @PC85
@PC85 PU7 0.1U_0603_25V7K 1UH_MMD-10DZ-1R0M-X1A_18A_20%
0.1U_0402_16V7K BOOT BST_1.5V-1 1 2 1 2
NC
EN/DEM

+1.5VP
2
2

2 13 DH_1.5V
TON UGATE

1
PR111 3 12 LX_1.5V PR110 @
VOUT PHASE

5
6
7
8
100_0603_1% PQ28 4.7_1206_5% 1
+5VALW 1 2 4 11 1 2 +5VALW
VDD CS PR112 + PC86

2
5 10 13K_0402_1% 330U_6.3V_M
FB VDDP
1

1
DL_1.5V PC88 @ 2
6 PGOOD LGATE 9 4
PGND

PC87 680P_0603_50V7K
GND

4.7U_0603_6.3V6K PC89
2

2
1
@ 47P_0402_50V8J
1 2 RT8209BGQW_WQFN14_3P5X3P5 PC90
7

3
2
1
4.7U_0805_10V6K AO4456_SO8

2
<Vo=1.5V> VFB=0.75V PR113
10K_0402_1%
Vo=0.75*(1+10K/10K)=1.5V 1 2
Fsw=280KHz
1

Cout ESR=17 mohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm

PR114
Ipeak=13.5A, Imax=9.5A, Iocp=16.2A 10K_0402_1%
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=3.9A
2

=>1/2Delta I=1.95A
4
Vtripmax=Iocp*Rdson=16.2*5.6*1.3=0.118V 4

Rcs=Vtrip/9uA=0.118V/9uA=13.1K
choose Rcs=13K
Iocpmax=((13K*11uA)/0.0045)+1.95A=32A
Iocpmin=((13K*9uA)/(0.0056*1.3))+1.95A=18A Security Classification Compal Secret Data Compal Electronics, Inc.
Iocp=18A~32A Issued Date 2007/09/20 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 47 of 55

A B C D
 A B C D

FB1_NB_COREP
POWER_SEL +5VALW

2
HIGH 0.95V
PR158

1
11.8K_0402_1%
LOW 1.1V PR131
PJ16

1
10K_0402_1%
10K_0402_5% NB_CORE_B+ 2 1 B+
2 1

1
PR159 D

2200P_0402_50V7K

10U_1206_25V6M
1 1 2 2 PQ44 @ JUMP_43X79 1

G SSM3K7002F_SC59-3

1
PQ43 D
S

1
SSM3K7002F_SC59-3

PC140

PC91
<13> POWER_SEL 1 2 2

100U_25V_M
PR157 G 1

5
6
7
8
0_0402_5% S PQ29

2
1

PC218
PC125 +

2
PC126 0.1U_0402_25V6
0.01U_0402_25V7K
2

PR115 2
255K_0402_1% 4
1 2
PR116 PR117
100K_0402_5% 0_0603_5%
1 2 BST_NB_CORE
1 2 AO4466_SO8

3
2
1
<36,42> VLDT_EN
DCR= 7.5 mohm

1
@ PR118
@PR118 PL8

15

14
1
30K_0402_5% PC94 PU8 PC93 1UH_FDUE1040D-1R0M-P3_21.3A_20%
0.1U_0402_16V7K BST_NB_CORE-1
1 2 1 2

BOOT
NC
EN/DEM
+NB_COREP

2
2
2 13 DH_NB_CORE 0.1U_0603_25V7K
TON UGATE

1
PR120 3 12 LX_NB_CORE
VOUT PHASE

5
6
7
8
100_0603_1% PQ30 PR119 @ 1
1 2 4 11 1 2 +5VALW 4.7_1206_5%
+5VALW VDD CS PR121 + PC95

2
FB1_NB_COREP 5 10 7.5K_0402_1% 330U_6.3V_M
FB VDDP

1
DL_NB_CORE 2
6 PGOOD LGATE 9 4

PGND
<Vo=1.1V> VFB=0.75V PC96 PC97 @

GND
4.7U_0603_6.3V6K PC98 680P_0603_50V7K

2
V=0.75*(1+4.7K/10K)=1.1V

1
2
@ 47P_0402_50V8J 2

Fsw=280KHz 1 2 RT8209BGQW_WQFN14_3P5X3P5 PC99

3
2
1
4.7U_0805_10V6K AO4456_SO8

2
Cout ESR=15m ohm Rdson(max)=18m Rdson(typ)=15m
Ipeak=7.6A, Imax=5.4A, Iocp=9.2A PR122
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A 2.37K_0402_1%
1 2
=>1/2Delta I=1.03A

1
Vtripmax=Iocp*Rdson=9.2*5.6*1.3=0.067V
Rcs=Vtrip/9uA=0.067V/9uA=7.44K PR123
choose Rcs=7.5K 8.87K_0402_1%
Iocpmax=((7.5K*11uA)/0.0045)+1.03A=19.36A

2
Iocpmin=((7.5K*9uA)/(0.018*1.3))+1.03A=10.3A
Iocp=10.3A~19.36A

+1.5V
PU16
+5VALW APL5508-25DC-TRL_SOT89-3
1

3 3

+3VS 2 3
PJ24 IN OUT
+2.5VSP
1

4.7U_0805_6.3V6K
@ JUMP_43X79

1
GND
1

1
2

PC115 PC114
1

PC113
1U_0402_6.3V6K 1U_0402_6.3V6K @ PR153
@PR153
2

150_1206_5%
2

2
6

PU12
1

5 PC116
VCNTL

VIN 4.7U_0805_6.3V6K
7 POK
4
2

PR155 VOUT
3
10K_0402_1% VOUT +CPU_VDDRP
1

22U_0805_6.3V6M
0.01U_0402_25V7K

VLDT_EN 1 2 8 2
EN FB
1

PC119
GND
1

9 PR154 PC118
2

VIN
1

PR188 @ 31.6K_0402_1%
2

PC121 47K_0402_5% APL5915KAI-TRL_SO8

1

0.1U_0402_16V7K
2

+5VALW PR161 PR156 VDDR_SW

165K_0402_1% 249K_0402_1%
2

HIGH 1.05V
1

@PR152
@ PR152 SSM3K7002F_SC59-3
4
10K_0402_1% PQ58 LOW 0.9V 4
1

D
2
2

<28> VDDR_SW G
S
3
1

PR160
10K_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2010/03/12 Title
SCHEMATIC, MB A5911
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 48 of 55
A B C D
 5 4 3 2 1

PR124
+1.5V 1K_1206_5%
1 2

PQ31
PR125 TP0610K-T1-E3_SOT23-3
B+

1
VIN PD13 1K_1206_5%
2 1 1 2 3 1

1
PJ17
JUMP_43X79 LL4148_LL34-2 PR126

2
1K_1206_5%
PU9 1 2

2
D D

100K_0402_5%

100K_0402_5%
1 6
VIN VCNTL
+3VALW

1
PR128
PR127

PR129
2 5 1K_1206_5%

2
GND NC

1
PC101 1 2

1
PC100 3 7 1U_0603_6.3V6M
4.7U_0805_6.3V6K PR130 VREF NC

2
1K_0402_1% 4 8
VOUT NC
9

2
TP
APL5336KAI-TRL SOP

1
0.1U_0402_16V7K
PR133 PR132
+0.75VSP

1
D

1K_0402_1%
2N7002W-T/R7_SOT323-3
300K_0402_5% PQ32 100K_0402_5%

PC102
1 2 2 PR134 PQ33
<22,42> SUSP

DTC115EUA_SC70-3
G

1 2
1
S PC103

3
PC104 10U_0805_6.3V6M <36,46> ACOFF 2

2
0.22U_0402_10V4Z PQ34

2
DTC115EUA_SC70-3

3
Ipeak=1A, Imax=0.7A

C C

PR135 B+
VL 2.2M_0402_5%
2 1

1
VS PR136
499K_0402_1%

1
PR137

2
100K_0402_1%

8
<8,44,45> MAINPWON PD14 PU1B
2 5

P
+
1 7 O

0.01U_0402_25V7K
<46> ACON 3 - 6

1
G

1
1000P_0402_50V7K

32.4

PC107
B BAS40CW_SOT323-3 LM393DR_SO8 PR138 B

4
1

1
191K_0402_1%

PC106
PC105 PR139

2
0.1U_0603_25V7K

PRG++ 2

2
499K_0402_1%

PR140 PQ35 PR141

1
34K_0402_1% D 47K_0402_5%
2 1 2 2 1
RTCVREF G PACIN <43,46>

1
S

SSM3K7002FU_SC70-3
PQ36
ACIN

1
DTC115EUA_SC70-3
@ PR142
@PR142
Precharge detector

66.5K_0402_1%
2 +5VALW
Min. typ. Max.

2
H-->L 14.589V 14.84V 15.243V

3
L-->H 15.562V 15.97V 16.388V
BATT ONLY
Precharge detector
Min. typ. Max.
A
H-->L 6.138V 6.214V 6.359V A

L-->H 7.196V 7.349V 7.505V

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401827 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, September 14, 2010 Sheet 49 of 55

5 4 3 2 1
 5 4 3 2 1

D
PR144 D
200K_0402_1%
1 2 VGA_ON <22,36,38,42>

1
316K_0402_1% PC156
PR145 0.22U_0402_10V4Z

2
PR147
402K_0402_1% PU11

1
+1.8VSP1 2 1 1 FB EN/SYNC 10

PC153 2 9 PL9
0.1U_0402_16V7K GND GND 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
PJ28 1 2 3 SW SW 8 1 2 +1.8VSP1
+5VALW
1 1 2 2 4 IN IN 7

22U_0805_6.3V6M

22U_0805_6.3V6M
0.1U_0402_25V6

10U_0805_10V4Z

10U_0805_10V4Z
JUMP_43X79 1 2 5 BS POK 6

B340A_SMA2
PR148 PR143

1
PC157

PC123

PC154

PD15

PC117

PC124
0_0402_5% 11 4.7_1206_5%
TP

2
MP2121DQ-LF-Z_QFN10_3X3

2
@

1
PC155
680P_0603_50V7K

2
C C

+5VALW

+3VALW
1

+3VALW PC109 @
1U_0402_6.3V6K
+1.5V
2

1
PC147
1U_0402_6.3V6K
1

VGA@

2
B @PJ18
@ PJ18 B
1

JUMP_43X79

1
PU14
2

6 PJ31

1
VCNTL JUMP_43X79
5 3 +1.8VSP2
2

VIN VOUT VGA@ PU10

9 VIN VOUT 4
1

2
6 VCNTL
1

8 @ PR149
@PR149 5 3

2
EN VIN VOUT
+1.0VSGP
1

@PC112
@ PC112 7 2 15K_0402_1% PC108 @ PC111 @ 9 4
GND

POK FB VIN VOUT

1
4.7U_0603_6.3V6K 0.01U_0402_25V7K 22U_0805_6.3V6M
2

1
8 FB=0.8V PR174
2

EN

1
APL5913-KAC-TRL_SO8 PC142 7 2 1.54K_0402_1% PC145 PC144

GND
1

4.7U_0603_6.3V6K POK FB VGA@ 0.022U_0402_25V7K 22U_0805_6.3V6M

@

2
1

VGA@ VGA@ VGA@

2
APL5913-KAC-TRL_SO8

1
PR150 @ VGA@

1
12K_0402_1%
2

VGA@ PR175
VGA@ PR173 6.04K_0402_1%
VGA_PWR_ON 1 2
<38,42,51> VGA_PWR_ON

2
10K_0402_5%
@ PR151
200K_0402_1%
VGA_ON 1 2
1

@
PR146
1

@ PC150
@PC150 47K_0402_5%

1
0.1U_0402_10V7K
VGA@ PC146 1 @PR172
@ PR172
2

1U_0402_6.3V6K 22K_0402_5% Ien=10uA, Vth=0.3V, notice

A A
2

the res. and pull high

2
voltage from HW

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/08/10 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 50 of 55
5 4 3 2 1
 A B C D E F G H

1 1

VGA_CORE
F=1/(75*e-12*33)=400K
Ipeak=33A Imax=23.1A Iocp=39.6A
Rsenmax=(5.6*1.3*39)/20=14.2 Kohm choose
Rsen=14.3Kohm
PL13 Iocpmin=(14.3*20)/(5.6*1.3)=39.3A
B+ 1 2 B+_core

HCB4532KF-800T90_1812
VGA@

10U_1206_25V6M

10U_1206_25V6M
1 VGA@ LX_VCORE
VGA@

1
PC164
DH_VCORE 1 PR183 2 DH_VCORE-1

PC165
PR184 0_0603_5%
2

BST_VCORE
1 2 1 2

2
0_0603_5% PC166 VGA@
+5VS VGA@ 0.1U_0603_25V7K
VGA@

5
NC TPCA8030-H_SOP-ADV8-5

5
VGA@ PQ38 VGA@ TPCA8030-H_SOP-ADV8-5
PR185 PQ45 @
0_0603_5%

16

15
8

1
PU998

2
1 PR1862 7138_VCORE 4

PHASE

BOOT
UG
GND

PGOOD
4
4.7_0603_5% VGA@
3 VIN PVCC 14 1 2 PC167 DCR=2.2m OHM
+3VS

3
2
1
7138_VCORE 2.2U_0603_6.3V6K

3
2
1
VGA@ PL14
PC168 4 13 DL_VCORE
2.2U_0603_6.3V6K VCC LG 0.56U_PCMC104T-R56MN_25A_20%
2 2
2

VGA@ 1 2 +VGA_COREP
@ PR187 APW7138NITRL_SSOP16 VGA@

5
6
7
8

5
6
7
8

1
10K_0402_5% 12
2

PGND

1
AO4456_SO8

AO4456_SO8
PR191
VGA@ VGA@ 4.7_1206_5% PR298 1 PC169
1

VGA@ PR190 PQ39 PQ40 VGA@ 0_0402_5%

+

330U_6.3V_M
1 2 5 11 ISEN_VCORE
1 2 VGA@

1 2
<38,42,50> VGA_PWR_ON PR177 20K_0402_1% EN ISEN
4 4 PR297

2
14.3K_0402_1% PC171 VGA@ VGA@

FSET
GCORE_SEN 2

NC
VGA@

VO
FB
1 2 GCORE_SEN <17>
680P_0603_50V7K

2
VGA@
6

10

3
2
1

3
2
1
10_0402_5%
VFB=0.6V

2
VGA@
ESR=15 mohm
1

VGA@
PC170
VGA@
2

0.1U_0402_10V7K PR193

1
1

1 Rds(TYP)=2.3mohm; MAD@ PR197

22P_0402_50V8J

4.99K_0402_1% 68.1K_0402_1%
1

1
PR195 VGA@ Rds(max)=3.2mohm +3VS
PC172

PR196
2200P_0402_25V7K

VGA@ PC998
22K_0402_1% 0.01U_0402_25V7K
2

2
VGA@ @ PAK@
2

2
PR197 VGA@
1

PC174

43.2K_0402_1% PR211
33K_0402_1%
10K_0402_5%
2

1 1
1
VGA@ PAK@ VGA@ PR199

1
MAD@ PR198 PQ41 D 10K_0402_5%
9.53K_0402_1% PR198 2 1 2
G VGA@

2N7002W-T/R7_SOT323-3

2
8.87K_0402_1% S PR200 @

1
10K_0402_1%
PC175
4700P_0402_25V7K

1
3 3
MAD@ PR201 VGA@
31.6K_0402_1%

1
PAK@ PR201
25.5K_0402_1%
+3VS

2
+3VS

2
@ PR212

2
PR210 VGA@ 10K_0402_5%
10K_0402_5% VGA@ PR203
GPU_VID1 <16>

1
1
PQ60D 10K_0402_1%
2 1 2

1
1
PQ42 D VGA@ PR202 2N7002W-T/R7_SOT323-3 G

2
2N7002W-T/R7_SOT323-3 2 1 2 VGA@ S

3
VGA@ G PR205 VGA@
Park XT Madison S 10K_0402_5% 10K_0402_1%

1
VGA@
PC177 @PR204
@PR204

1
GPU_VID0 GPU_VID1 Core Voltage Level GPU_VID0 GPU_VID1 Core Voltage Level 4700P_0402_25V7K 10K_0402_1%

2
1 1 0.93 V 1 1 0.9 V

1 0 1.0 V 1 0 0.95 V +3VS

2
0 1 1.05V 0 1 1.0V @ PR213

10K_0402_5%
0 0 1.12 V 0 0 1.05 V VGA@ PR206

1
1
D 10K_0402_1%
PQ61 2 1 2
4 2N7002W-T/R7_SOT323-3 G GPU_VID0 <16> 4

2
S

3
VGA@ PR207 VGA@
10K_0402_1%

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/12/18 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 51 of 55
A B C D E F G H
 A B C D E F G H

CPU_B+ PL15
LGATE_NB HCB4532KF-800T90_1812
PC183 1 2 B+

10U_1206_25V6M

2200P_0402_50V7K
33P_0402_50V8K

0.01U_0402_25V7K

100U_25V_M

1000P_0402_50V7K

1000P_0402_50V7K
2 1 1

1
+

PC185

PC186

PC187

PC188
PQ50

1
1 1

PC219

PC220
2 1 2 1 UGATE_NB 8 1
G2 D2
7 2

2
PR214 PC184 S2/D1 D2 2
6 3

2
44.2K_0402_1% 1200P_0402_50V7K S2/D1 G1
5 S2/D1 S1 4
PR215
2_0603_5% AO4932_SO8
+5VS 1 2 PC189 PL16
1000P_0402_50V7K 3.3UH_SIQB74B-3R3PF_5.9A_20%
2 1 PHASE_NB 1 2
PR230

1
PC190 PR216 0_0603_5% +CPU_CORE_NB
0.1U_0603_16V7K 22K_0402_1% BOOT_NB 1 2 1 2 PR217
2 1 4.7_1206_5% 1

2
PR218 PC191
10_0402_5% 0.22U_0603_10V7K + PC192

1 2
1 2 +CPU_CORE_NB 220U_D2_4VM
PC193
CPU_B+ 1 2
680P_0603_50V7K 2 +VDDNB
PR219
CPU_VDDNB_FB_H <8> Design Current: 2.8A

2
2_0603_5% PR221
+3VS +5VS +3VS 13.7K_0402_1% Max current: 4A

1
2 1 PHASE_NB
PR220
LGATE_NB
OCP_min:5A
0_0402_5%

1
PC194 CPU_B+
0.1U_0603_16V7K PHASE_NB

2
1

2200P_0402_50V7K
PR222 PR223 UGATE_NB

0.01U_0402_25V7K
10U_1206_25V6M

10U_1206_25V6M
0_0402_5% @ 105K_0402_1%

5
2 1 PQ46

TPCA8030-H_SOP-ADV8-5
CPU_VDDNB_FB_L <8>
PR224
2

2
1

1
PC195

PC196

PC197

PC198
0_0402_5%
PR225
1

PR227 @ 10K_0402_1% PR226

2
105K_0402_1% PR228 10_0402_5% UGATE0 4
@ 105K_0402_1% 48

47

46

45

44

43

42

41

40

39

38

37
2

1
PU15
2 PHASE0 2

FB_NB

COMP_NB

FSET_NB

VSEN_NB

RTN_NB

OCSET_NB

PGND_NB

LGATE_NB

PHASE_NB

UGATE_NB
VIN

VCC
2

PR229 PL17

3
2
1
2.2_0603_1% 0.36UH_PCMC104T-R36MN1R17_30A_20%
<36> VGATE 1 36 BOOT_NB BOOT0 1 2 1 2 1 2 +CPU_CORE
PR237 0_0402_5% OFS/VFIXEN BOOT_NB

2
1 2 2 35 BOOT0 PC199 @
PGOOD BOOT0

5
<26> H_PWRGD_L 1 2 0.22U_0603_10V7K PQ47 PR232

1
PR231 0_0402_5% @ 3 34 UGATE0 PQ48 16.2K_0402_1%

TPCA8028-H_SOP-ADVANCE8-5
PWROK UGATE0 PR233
2 1 4 33 PHASE0 TPCA8028-H_SOP-ADVANCE8-5 4.7_1206_5%

1
<8> CPU_SVD PR234 0_0402_5% SVD PHASE0
1 PR235 2
5 32 4 4 4.02K_0402_1%

1 2
SVC PGND0 +5VS
2 1
<8> CPU_SVC PR236 0_0402_5% 6 31 LGATE0 PC200 PC201
ENABLE LGATE0 680P_0603_50V7K 2 1
7 30

3
2
1

3
2
1

2
RBIAS PVCC 0.1U_0402_16V7K
<36> VR_ON 8 29 LGATE1
OCSET LGATE1

1
PR238 PR239 ISL6265IRZ-T_QFN48_6X6~D PC202
2 1 2 1 9 28 1U_0603_16V6K LGATE0
21.5K_0402_1% 95.3K_0402_1% VDIFF0 PGND1

ISN0
ISP0
10 27 PHASE1
FB0 PHASE1
11 26 UGATE1
COMP0 UGATE1 CPU_B+
12 25 BOOT1 +CPU_CORE_0
VW0 BOOT1
Design Current: 25A
COMP1
VDIFF1
VSEN0

VSEN1
RTN0

RTN1

2200P_0402_50V7K
0.01U_0402_25V7K
ISN0

ISN1
VW1
ISP0

ISP1
FB1

10U_1206_25V6M

10U_1206_25V6M
Max current: 35A
TP

5
PQ51

TPCA8030-H_SOP-ADV8-5
OCP_min:42A
13

14

15

16

17

18

19

20

21

22

23

24

49

1
PC203

PC204

PC205

PC206
PR242 0_0402_5%

ISP0
ISN0

2
1

ISN1
ISP1

UGATE1 4
<8> CPU_VDD0_FB_H
0_0402_5%

VSEN0 0_0402_5%
2 PR244 1

2 PR250 1
0_0402_5%

PR241 PR240
+CPU_CORE 2 1 1 2 PHASE1
3 3
10_0402_5% PR243 PL18
2

3
2
1
2.2_0603_1% 0.36UH_PCMC104T-R36MN1R17_30A_20%
<8> CPU_VDD0_FB_L RTN0 BOOT1 1 2 1 2 1 2 +CPU_CORE
PR245 10_0402_5%

2
2 1 PC207 @

5
0.22U_0603_10V7K PQ52 PR247

1
RTN1 16.2K_0402_1%

TPCA8028-H_SOP-ADVANCE8-5
<8> CPU_VDD1_FB_L PR246 10K_0402_1% TPCA8028-H_SOP-ADVANCE8-5 PR248
2 1 PQ49 4.7_1206_5%

1
1 PR249 2
@ PR252 1K_0402_1% 4 4 4.02K_0402_1%

1 2
+1.5VS 2 1
PC208 PC209
<8> CPU_VDD1_FB_H VSEN1 680P_0603_50V7K 2 1
PR251

3
2
1

3
2
1

2
+CPU_CORE 2 10_0402_5%
1 0.1U_0402_16V7K

DIFF_0 VW0 DIFF_1 VW1

LGATE1
PR253 PC210 PR254 PC213

ISN1
ISP1
255_0402_1% 4700P_0402_25V7K 255_0402_1% 4700P_0402_25V7K
2 1 2 1 FB_0 2 1 COMP0 2 1 2 1 2 1 FB_1 2 1 COMP1 2 1

PC211 PC212 PC214 PC215

180P_0402_50V8J 1000P_0402_50V7K 180P_0402_50V8J 1000P_0402_50V7K

PR255 PR257 PR258 PR260

1K_0402_5% PR256 PC216 6.81K_0402_1% 1K_0402_5% PR259 PC217 6.81K_0402_1%
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

54.9K_0402_1% 1200P_0402_50V7K 54.9K_0402_1% 1200P_0402_50V7K

1

PR262 @ PR263 @
1K_0402_5% 1K_0402_5%
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/04/16 Deciphered Date 2010/03/12 Title
SCHEMATIC, MB A5911
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 52 of 55
A B C D E F G H
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
Before modify to fault, we recognize that
VGAPWRSEL pin is open drain state. But after
D D
ADD 2 switch mos and remove 2 pull check with AMD AE regoer to clear the foul that ADD PQ60 and PQ61 remove PR212(10K,0402) and 2009/08/21
1 high resistance to modify VGA_CORE VGAPWRSEL pin has driviing ability.so i take
away 2 pull high resistance and add 2 switch
0.1 52 PR213(10K.0402) EVT_NEW75
switch level
mos to modify the switch level.

2 change thermister , tune PH1

protection and recovery set change thermister from 150K to 100K 0.1 44
thermister part number SL200000V00 and PR28
change to 21K, PR30 change to 9.53K 2009/08/27 EVT_NEW75
point

Cause GPU have GCORE_SEN and FB_GND pin ADD GCORE_SEN and FB_GND net, also add
3 Add GPU voltagr sence net so power add receive net. 0.1 51 PR296(0_0402_1%), PR297(10_0402_5%) and 2009/09/04 EVT_NEW75
PR298(0_0402_5%)

4 change DC-IN connector part number to meet pin definition 0.1 43 change part number is SP020908120 2009/09/10 EVT_NEW75

Cause meet battery Ki value setting

5 change reistance PR81 value
C C
6 ADD switch circuit for 1.05V
from 1.106 to 0.7224. change PR81 0.1 46 change resistance PR81 value from 154K to 80.6K 2009/09/22 EVT_NEW75
from 154K(0402_1%) to 80.6K(0402_1%)
ADD PR161 (165K_0402_1%),
Cause follow AMD electrcial sheet, PQ58,PR152(10K_0402_5%),PR160(10K_0402_5%),
VDDIO/ VDDR voltage setting procedure. 0.1 48
PC131(0.1U_25V6) , change PR161 value from 100K
2009/09/22
EVT_NEW75
AMD processor will switch between 1.05V to 249K, and ADD enable net name -VDDR_SW
and 0.9V by VDDIO and VDDR

7 change resistance size

cause for component de-rating . Prevent the
component break down when inrush current happen.
0.1 46 change PR61 from (0.02_1206_1%) to (0.02_2512_1%) 2009/10/06 EVT_NEW75

change PR198 from 9.76_0402_1% to 9.53_0402_1%,

8 Modify VGA_CORE mapping table.
cause ATI change power play voltage, so change the
table value.
0.1 51 PR197 from 37.4_0402_1% to 64.9_0402_1% and 2009/10/06 EVT_NEW75
PR201 from 17.8_0402_1% to 31.6_0402_1%

9 Change 1.0VSGP enable RC value

Prevent LDO can't turn off when it should turn off 0.1 50 Change PR173 from 100K_0402_5% to 10K_0402_5%,
PC146 from 0.1u_0402 to 1u_0402
2009/10/15 EVT_NEW75

Cause light load efficiency result is fail,

B 10 Change lowside MOS of VGA_CORE and we get result after discuss FAE. The 0.1 51 Change PQ39 and PQ40 from TPCA8028(SB00000GL00)
to AO4456(SB000009F80)
2009/11/19 EVT_NEW75
B
reason is lowside mos Rdson too less and IC
will detect not very sensitive

Change PR40 and PR47 from 0_0603_5% to

11 Change 3/5Valw boost resistance
value For EMI request
0.1 45 2.2_0603_5%(SD013220B80) 2009/11/19 EVT_NEW75

Add pc219 and pc220 are both S CER CAP

12 ADD two capacity
For EMI request
0.1 52 1000P 50V K X7R 0402 2009/11/23 EVT_NEW75

Cause madison and park need different voltage switch

13 ADD three resistance level so add different resistance value for the 0.1 51 Add PR197( 68.1K_0402_1%) , PR198 (
9.53K_0402_1%) and PR201 ( 31.6K_0402_1%)
2009/11/23 EVT_NEW75
problem.

14 Change chock Cause A phase put wrong chock 0.2 37,39,40 Change PL9 from SH00000FK00 to SH000009Q00 2009/11/23 EVT_NEW75

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 53 of 55
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List)

DVT Stage
PVT Stage
1. remove Y4 related
1. un-pop D39,D41 p.40
2. add a bead on +VDDA11PCIE ---ok (add L28)
D
3. use 6mohm MOS on +1.1VS ---ok (U38,U37) 2. pop D27 p.39 D

4. +1.1VALW vlotage level --check PW rail 3. un-pop Q73,Q74,Q75,Q70,R500,R502 p.38

5. check EC sequence (syson/vga_on) --ok 4. Change R470 to 8.2K p.36
6. VRAM ID --ok 5. Change R600,R510,R489 to 100K p.22/p.42
7. VRAM_RST circuit -- check slew rate 6. Change C847 to 0.1u p.22
8. 3G module circuit update --ok 7. Change C739,C740 to 15p p.36
9. EC 500K circuit --ok 8. Change LED resistance R477,R499 change to 2.2K p.37
10. MEMZN circuit (0ohm/10uF) --ok
9. Change R611 to 33K p.42
11. check GBE PU/PD --ok
10. Change HDMI_HPD PU from +3VSG to +3VS p.24
12. check capacitor size
13. TXC crystal value --ok (change X1,Y2), Y5 11. Change C957,C971 to 0.47u_0603 p.40
14. internal clock circuit --ok 12. Remove VGA option solution
15. ADD VGAPWR_ON --ok, INT_VGAPWR_ON unpop R147,R420,R421,R248 pop R161 p.16/p.22/p.17
C 16. define PX_FN/CLK_MODE strap pin --ok 13. Pop R595,R596,Q49,Q48 change R595 to 300k p.42 C

17. define CLK_REQ for internal CLKREQ --ok 14. Change LED1,LED3 to SC591NB5A30 p.37
18. change 4.7u_0805 type --ok 15. Change Q5,Q26 to SB00000DH00 p.16/p.37
19. BOM change for SG --ok 16. Change C468~C475 to MAD@ p.20
20. add VGAPWR_ON for SG&int clock use --ok
17. Change C305,C306 to 0603 size p.18
21. add PJ25 --ok
18. Change LED control circuit, Pop R537,R457 p.34/p.35
22. LED1/3 680ohm, LED2/4 3.9Kohm --ok
23. add MUXLESS strap --ok (R521,R612) 19. Update AMP GAIN to 10dB p.40
24. add LPW planel feature --ok (LOCAL_DIM / 20. Change C11,C56,C723 to SGA00002N80 p.8/p.9/p.35
COLOY_ENG_EN) 21. Change TPC24 to TPC12 for layout
25. EC version control--ok (R529,R528)
26. WiMAX LED combine circuit --ok (R530,R531,D47)
27. change INT_VGAPWR_ON to EC_pin91 --ok MP Stage
B 28. add VB function --ok (R533,R532) 1. Add R541, R542 for TSI leakage current issue. (option) p.36 B

29. Add R534,R535,R536 for layout --ok

2. Change C21 from 3300pF to 100pF
30. change Y5 to 33p cap
3. Unpop C21
31. pop ESD diode --ok
32. set T25 to BH for main --ok 4. Unpop SW3
33. Define Board file ID for SW req. --ok 5. Change C305 to MAD@

6. Change VGA to R3 P/N 0419

7. Unpop ESD Diode D24 / D27 / D29 0512

For PEW change list
1. Change Strap/PID/BID for SW
2. Change EC version to E0
3. Change thermal sensor to SB-TSI
A 4. Define 8L_6L_UMA strap on SB A

5. Change EC version to D3 06/29

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2010/03/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A5911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401827
Date: Tuesday, September 14, 2010 Sheet 54 of 55
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
Cause NB_CORE and 1.1VALW efficiency measurement
D
15 Change chock result fail. so change inductor from 1.8uH to 1.0 0.2 47,48 Change PL6 and PL8 from SH000009680
SH000009U00
to 2009/12/01 EVT_NEW75
D
uH, and change the tye from ferrite to moding
Cause change low side MOS from TPCA8028 to
AO4456. And there have different Rds(on). then Change PR190 from SD000004100 (S RES 1/16W 8.2K
16 Change resistance value
OCP will different, so i need to change ocp
0.2 51 +-1% 0402) to SD00000QM80 (S RES 1/16W 14.3K 2009/12/01 EVT_NEW75
setting resistance. +-1% 0402)

17 ADD sunbber Cause VGA_CORE phase ringing too strong, so add

sunbber to reduce the ringing
0.2 51 ADD PR191(SD001470B80 ,S RES 1/4W 4.7 +-5% 1206
) and PC171(SE025681K80 S CER CAP 6,80P 50V K
2009/12/01 EVT_NEW75

X7R 0603 )

18 Change resistance value change VGA_CORE switch frequency fromm 300K to

400K, for solve efficiency fail issue
0.2 51
Change PR196 from 44.2K to 33K
2009/12/01 EVT_NEW75

Delete component PC73, PC83

19 and PC92 Cause for design resinable 0.2 47,48 Delete PC73,PC83 and PC92 2009/12/01 EVT_NEW75

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
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