Lab 01: Introduction to Cadence Schematic

Capture and Simulation

ECEN 454 - 507

Brandon Daniels - 825003805
TA: Zhiyang Ong
Schematics

Full Adder

4 Bit Adder
8 Bit Adder

Symbols

Full Adder
4 Bit Adder

8 Bit Adder
Verilog Testfixtures

Full Adder

4 Bit Adder
8 Bit Adder
Simulation Results

Full Adder

4 Bit Adder
8 Bit Adder

Discussion

The full adder produced the expected outputs on all test cases. Because the amount of test cases
increases exponentially for the 4 bit and 8 bit adders, only a selection of cases were tested. The 4 bit adder
produced the expected outputs for all 4 test cases, as given in the lab manual. For the 8 bit adder, the
clock changed position every 50 nanoseconds, and the output can be traced one clock cycle after the
input. For example, the output of the 8 bit adder at 500 nanoseconds corresponds to the inputs to the
inputs at 400 nanoseconds. The 8 bit adder produced the expected outputs for all but one test case. The
initial case of adding the values 01111110 and 11100111 did not result in the proper value, but every
other test managed to produce the correct output.