Logic Design: Chap. 4.2, Appendix A

Jin-Soo Kim
(jinsoo.kim@snu.ac.kr)
Systems Software &
Architecture Lab.
Seoul National University Logic Design
Fall 2019
Chap. 4.2, Appendix A

▪ Information encoded in binary
• Low voltage = 0, High voltage = 1
• One wire per bit
• Multi-bit data encoded on multi-wire buses
▪ Combinational elements
• Operate on data
• Output is a function of input
▪ State (sequential) elements

• Store information
4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 2

▪ Use voltage thresholds to extract discrete values from continuous signal
▪ Simplest version: 1-bit signal
• Either high range (1) or low range (0)
• With guard range between them
▪ Not strongly affected by noise or low quality circuit elements
• Can make circuits simple, small, fast, and robust
0 1 0
Voltage
Time
▪ Three components required to implement a digital system
• Combinational elements to compute Boolean functions
• Sequential elements to store bits
• Clock signals to regulate the updating of the memory elements
Sequential
elements
Combinational
In Out
…
elements
Clock
▪ Outputs are Boolean functions of inputs And
a
▪ Respond continuously to changes in inputs b
out
(with some, small delay)
out = a & b
Or
Rising Delay Falling Delay a
a && b b out
b
out = a | b
Voltage
a Not
a out
out = ~a
▪ Acyclic network of logic gates
• Continuously responds to changes on primary inputs
• Primary outputs become (after some delay) Boolean functions of primary inputs
Acyclic Network
Inputs Outputs

▪ AND-gate ▪ Adder
• Y = A & B • Y = A + B
A
A + Y
Y
B B
▪ Multiplexer ▪ Arithmetic/Logic Unit

• Y = S? A : B • Y = F(A, B)
M A
A U ALU Y
Y
B X
B
S F
▪ Flip-flops
Shifter
Edge-triggered D flip-flop
4-bit register

▪ Register: stores data in a circuit
• Uses a clock signal to determine when to update the stored value
• Edge-triggered: update when Clk changes from 0 to 1
Clk
D Q
D 1 0 1
Clk
Q 1 0

▪ Register with write control
• Only updates on clock edge when write control input is 1
• Used when stored value is required later
Clk
D Q Write
Write
Clk D 1 0 1
Q 1 1

▪ Stores word of data
• Different from program registers seen in assembly code
▪ Collection of edge-triggered latches Structure
i7
▪ Loads input on rising edge of clock
D
C
Q+ o7
i6 D
Q+ o6
C
i5 D
Q+ o5
C
i4 D
Q+ o4 I O
C
i3 D
Q+ o3
C
i2 D
Q+ o2
i1
C
D
Clock
C
Q+ o1
i0 D
Q+ o0
C
Clock
▪ Stores data bits
▪ For most of time acts as barrier between input and output
▪ As clock rises, loads input
State = x State = y
Rising
Input = y Output = x Output = y
clock
x y

▪ Combinational logic transforms data during clock cycles
• Between clock edges
• Input from state elements, output to state element
• Longest delay determines clock period

▪ Accumulator circuit
▪ Load or accumulate on each cycle
Comb. Logic
0 Clock
A Load
L 0
Out In x0 x1 x2 x3 x4 x5
U MUX
In 1 Out x0 x0+x1 x0+x1+x2 x3 x3+x4 x3+x4+x5
Load
Clock

▪ A collection of registers
• Holds values of “program registers”
• x0 ~ x31 in RISC-V
• Register identifier (5 bits) serves as address
▪ Multiple ports
• Can read and/or write multiple words
in one cycle
• Each has separate address and data input/output
• Data is written to the register
Clock
only when RegWrite signal is enabled

▪ Reading ▪ Writing
• Like combinational logic • Like register
• Output data generated based on • Update only as clock rises
input address (after some delay)
00010 x2
Rising
clock
00110 x6 0x12
0x12
1
Clock Clock

▪ Random access memory for storing program data
▪ Operations similar to registers
▪ Reading: like combinational logic
▪ Writing: update only as clock rises
▪ Read/Write controlled using MemWrite and
MemRead signals
Clock
▪ Another read-only memory needed for instructions
▪ Dual-port memory: single memory for both instructions and data
• One read port for instructions, another read or write port for data

▪ Computation
• Performed by combinational logic
• Computes Boolean functions
• Continuously reacts to input changes
▪ Storage
• Registers
– Hold single words, Loaded as clock rises
• Random-access memories
– Hold multiple words
– Possibly multiple read or write ports
– Read word when address input changes
– Write word as clock rises

Logic Design: Chap. 4.2, Appendix A

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Logic Design: Chap. 4.2, Appendix A

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Jin-Soo Kim

Chap. 4.2, Appendix A

▪ State (sequential) elements

4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 2

4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 6

▪ Multiplexer ▪ Arithmetic/Logic Unit

4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 8

4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 9

4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 10

4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 12

4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 13

In 1 Out x0 x0+x1 x0+x1+x2 x3 x3+x4 x3+x4+x5

4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 14

4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 15

4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 16

4190.308: Computer Architecture | Fall 2019 | Jin-Soo Kim (jinsoo.kim@snu.ac.kr) 17

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