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NOTE: When ordering, use the entire part number. Add the suffix 9A to S
obtain the TO-252AA variant in the tape and reel, i.e., RFD15P05SM9A.
Packaging
JEDEC TO-220AB JEDEC TO-251AA
JEDEC TO-252AA
DRAIN
(FLANGE)
GATE
SOURCE
4-96 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFD15P05, RFD15P05SM, RFP15P05
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
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RFD15P05, RFD15P05SM, RFP15P05
1.2 -16
POWER DISSIPATION MULTIPLIER
1.0
0.6 -8
0.4
-4
0.2
0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE
2
ZθJC, NORMALIZED TRANSIENT
1
THERMAL IMPEDANCE
0.5
0.2
0.1
0.1 PDM
0.05
t1
0.02
0.01 t2
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 100 101
t1 , RECTANGULAR PULSE DURATION (s)
-100 -200
TC = 25oC VGS = -20V TC = 25oC
IDM , PEAK CURRENT CAPABILITY (A)
100µs
175 – T C
I = I 25 ----------------------
150
-10
1ms
VGS = -10V
OPERATION IN THIS 10ms
AREA MAY BE TRANSCONDUCTANCE
100ms
LIMITED BY rDS(ON) DC MAY LIMIT CURRENT
IN THIS REGION
-1 -10
-1 -10 -100 10-5 10-4 10-3 10-2 10-1 100 101
VDS , DRAIN TO SOURCE VOLTAGE (V) t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
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RFD15P05, RFD15P05SM, RFP15P05
-50 -40
PULSE DURATION = 80µs VGS = -10V
STARTING TJ = 150oC
DUTY CYCLE = 0.5% MAX
IAS , AVALANCHE CURRENT (A)
TC = 25oC
STARTING TJ = 25oC VGS = -8V
VGS = -6V
If R = 0 -10
tAV = (L) (IAS) / (1.3RATED BVDSS - VDD) VGS = -4.5V
VGS = -5V
If R ≠ 0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
-1 0
0.1 1 10 100 0 -1.5 -3.0 -4.5 -6.0 -7.5
tAV, TIME IN AVALANCHE (ms) VDS , DRAIN TO SOURCE VOLTAGE (V)
-40 2.5
IDS(ON) , DRAIN TO SOURCE CURRENT (A)
-24 1.5
175oC
-16 1.0
-8 0.5
0 0
0 -2 -4 -6 -8 -10 -80 -40 0 40 80 120 160 200
VGS , GATE TO SOURCE VOLTAGE (V) TJ , JUNCTION TEMPERATURE (oC)
2.0 2.0
VGS = VDS
ID = -250µA
NORMALIZED DRAIN TO SOURCE
ID = -250µA
BREAKDOWN VOLTAGE
THRESHOLD VOLTAGE
1.5 1.5
NORMALIZED GATE
1.0 1.0
0.5 0.5
0 0
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ , JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
JUNCTION TEMPERATURE VOLTAGE vs JUNCTION TEMPERATURE
4-99
RFD15P05, RFD15P05SM, RFP15P05
-37.5 -7.5
C, CAPACITANCE (pF)
1000
VGS = 0V, f = 1MHz RL = 3.33Ω
CISS = CGS + CGD IG(REF) = -0.65mA
800
CRSS = CGD VGS = -10V
COSS ≈ CDS + CGS -25 -5.0
600 0.75 BVDSS 0.75 BVDSS
COSS 0.50 BVDSS 0.50 BVDSS
400 0.25 BVDSS 0.25 BVDSS
-12.5 -2.5
200
CRSS
0 0 0.0
0 -5 -10 -15 -20 -25 IG(REF) IG(REF)
20 t, TIME (ms) 80
VDS , DRAIN TO SOURCE VOLTAGE (V) IG(ACT) IG(ACT)
VDS
tAV
L 0
VARY tP TO OBTAIN
REQUIRED PEAK IAS RG
-
VDD
+
0V DUT VDD
tP IAS
VGS
VDS
IAS tP
0.01Ω
BVDSS
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON tOFF
td(ON) td(OFF)
tr tf
0
RL 10% 10%
DUT - VDS
VDD 90% 90%
RG
VGS + VGS
0
10%
50% 50%
PULSE WIDTH
90%
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
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RFD15P05, RFD15P05SM, RFP15P05
VDS
VDS
RL Qg(TH)
0
VGS = -2V
VGS
- -VGS VGS = -10V
VDD
+ Qg(-10)
VGS = -20V
DUT
VDD
Ig(REF)
Qg(TOT)
0
Ig(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
4-101
RFD15P05, RFD15P05SM, RFP15P05
CA 12 8 1.6e-9
CB 15 14 1.47e-9 LDRAIN
5
CIN 6 8 1.09e-9 10 2
DPLCAP DRAIN
DBODY 5 7 DBDMOD RSCL1
DBREAK 7 11 DBKMOD RSCL2
DPLCAP 10 6 DPLCAPMOD 5
51 ESCL
EBREAK 5 11 17 18 -73.0
+
EDS 14 8 5 8 1 EBREAK
17
EGS 13 8 6 8 1 - 6 RDRAIN 18 -
ESG
ESG 5 10 8 6 1 +
8 16
EVTO 20 6 8 18 1 VTO
- DBODY
+
EVTO MOS2
GATE RGATE 21
-
+
IT 8 17 1 9 18 11
1 20 8 MOS1
LGATE 6
LDRAIN 2 5 1e-9
LGATE 1 9 6.73e-9 DBREAK
RIN CIN
LSOURCE 3 7 6.69e-9 RSOURCE LSOURCE
8
3
MOS1 16 6 8 8 MOSMOD M = 0.99 SOURCE
MOS2 16 21 8 8 MOSMOD M = 0.01
7
RBREAK 17 18 RBKMOD 1 S1A S2A
12 15 RBREAK
RDRAIN 50 16 RDSMOD 63.6e-3 13 14 17 18
RGATE 9 20 7.37 8 13
RIN 6 8 1e9 S1B S2B
13 RVTO
RSCL1 5 51 RSCLMOD 1e-6 CB
RSCL2 5 50 1e3 CA IT 19
RSOURCE 8 7 RDSMOD 46.5e-3 + + 14 -
RVTO 18 19 RVTOMOD 1 6 5 VBAT
EGS 8 EDS 8
- - +
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 -0.65
.MODEL DBDMOD D (IS = 1.27e-13 RS = 1.62e-2 TRS1 = 1.35e-3 TRS2 = -4.33e-6 CJO = 1.25e-9 TT = 7.97e-8)
.MODEL DBKMOD D (RS = 2.54e-1 TRS1 = 4.54e-3 TRS2 = -1.12e-5)
.MODEL DPLCAPMOD D (CJO = 285e-12 IS = 1e-30 N = 10)
.MODEL MOSMOD PMOS (VTO = -3.78 KP = 6.97 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 9.15e-4 TC2 = -4.0e-7)
.MODEL RDSMOD RES (TC1 = 5.47e-3 TC2 = 1.37e-5)
.MODEL RSCLMOD RES (TC1 = 1.9e-3 TC2 = -7.5e-6)
.MODEL RVTOMOD RES (TC1 = -3.71e-3 TC2 = -2.41e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.65 VOFF = 1.65)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.65 VOFF = 3.65)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.60 VOFF = -4.40)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.40 VOFF = 0.60)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; authored by William J. Hepp and C. Frank Wheatley.
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RFD15P05, RFD15P05SM, RFP15P05
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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