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IRFR320, IRFU320

Data Sheet July 1999 File Number 2412.3

3.1A, 400V, 1.800 Ohm, N-Channel Power Features


MOSFETs • 3.1A, 400V
These are N-Channel enhancement mode silicon gate
• rDS(ON) = 1.800Ω
power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a • Single Pulse Avalanche Energy Rated
specified level of energy in the breakdown avalanche mode • SOA is Power Dissipation Limited
of operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching • Nanosecond Switching Speeds
convertors, motor drivers, relay drivers, and drivers for high • Linear Transfer Characteristics
power bipolar switching transistors requiring high speed and
• High Input Impedance
low gate drive power. These types can be operated directly
from integrated circuits. • Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Formerly developmental type TA17404.
Components to PC Boards”
Ordering Information Symbol
PART NUMBER PACKAGE BRAND D

IRFR320 TO-252AA IFR320

IRFU320 TO-251AA IFU320 G


NOTE: When ordering, use the entire part number. Add the suffix 9A
to obtain the TO-252AA variant in tape and reel, i.e., IRFR3209A.
S

Packaging
JEDEC TO-251AA JEDEC TO-252AA

SOURCE
DRAIN
GATE GATE DRAIN
(FLANGE)

DRAIN (FLANGE) DRAIN SOURCE

4-395 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
IRFR320, IRFU320

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified


IRFR320, IRFU320 UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 400 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 400 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 3.1 A
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 2.0 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 12 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 50 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 190 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 300 oC
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 260 oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. TJ = 25oC to 125oC.

Electrical Specifications TC = 25oC, Unless Otherwise Specified


PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V, (Figure 10) 400 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V, 3.1 - - A
(Figure 7)
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 1.7A, VGS = 10V, (Figures 8, 9) - 1.600 1.800 Ω
Forward Transconductance (Note 2) gfs VDS ≥ 10V, ID = 2.0A, (Figure 12) 1.7 2.6 - S
Turn-On Delay Time td(ON) VDD = 200V, ID ≈ 3.1A, RGS = 18Ω, RL = 63Ω, - 10 15 ns
Rise Time tr VGS = 10V - 14 21 ns
MOSFET Switching Times are Essentially Indepen-
Turn-Off Delay Time td(OFF) dent of Operating Temperature - 30 45 ns
Fall Time tf - 13 20 ns
Total Gate Charge Qg(TOT) VGS = 10V, ID = 3.1A, VDS = 0.8 x Rated BVDSS, - 13 20 nC
(Gate to Source + Gate to Drain) IG(REF) = 1.5mA, (Figure 14)
Gate to Source Charge Qgs Gate Charge is Essentially Independent of Operat- - 2.2 3.3 nC
ing Temperature
Gate to Drain “Miller” Charge Qgd - 7.2 11 nC
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz, (Figure 11) - 350 - pF
Output Capacitance COSS - 64 - pF
Reverse Transfer Capacitance CRSS - 8.1 - pF
Internal Drain Inductance LD Measured From the Drain Modified MOSFET - 4.5 - nH
Lead, 6.0mm (0.25in) from Symbol Showing the
Package to Center Internal Device
of Die Inductances
D
Internal Source Inductance LS Measured From the - 7.5 - nH
Source Lead, 6.0mm LD
(0.25in) from Package to
Source Bonding Pad
G
LS

Thermal Resistance, Junction to Case RθJC - - 2.5 oC/W

Thermal Resistance, Junction to Ambient RθJA Typical Solder Mount - - 110 oC/W

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IRFR320, IRFU320

Source to Drain Diode Specifications


PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET - - 3.1 A
D
Symbol Showing the In-
Pulse Source to Drain Current ISDM - - 12 A
tegral Reverse P-N
(Note 3)
Junction Rectifier
G

S
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 3.1A, VGS = 0V, - - 1.6 V
(Figure 13)
Reverse Recovery Time trr TJ = 25oC, ISD = 3.1A, dISD/dt = 100A/µs 120 270 600 ns
Reverse Recovery Charge QRR TJ = 25oC, ISD = 3.1A, dISD/dt = 100A/µs 0.64 1.4 3.0 µC
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 50V, starting TJ = 25oC, L = 3.1mH, RGS = 25Ω, peak IAS = 3.1A.

Typical Performance Curves Unless Otherwise Specified

1.2 4.0
POWER DISSIPATION MULTIPLIER

1.0
3.2
ID, DRAIN CURRENT (A)

0.8
2.4
0.6

1.6
0.4

0.8
0.2

0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150
TC , CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE

10
ZθJC, TRANSIENT THERMAL IMPEDANCE

0.5
1
0.2

0.1 PDM
0.05
0.1 0.02
t1
0.01
t2
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
10-2
10-5 10-4 10-3 10-2 0.1 1 10
t1, RECTANGULAR PULSE DURATION (s)

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE

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IRFR320, IRFU320

Typical Performance Curves Unless Otherwise Specified (Continued)

100 5
OPERATION IN THIS VGS = 10V
VGS = 6.0V
AREA IS LIMITED
BY rDS(ON)
4
ID, DRAIN CURRENT (A)

ID, DRAIN CURRENT (A)


PULSE DURATION = 80µs
10µs DUTY CYCLE = 0.5% MAX
10
3
100µs
VGS = 5.5V
2
1 1ms
VGS = 5.0V

10ms 1
TJ = MAX RATED VGS = 4.0V VGS = 4.5V
TC = 25oC
SINGLE PULSE DC
0.1 0
1 10 100 1000 0 40 80 120 160 200
VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

5 10
PULSE DURATION = 80µs VGS = 10V PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
VDS ≥ 350V
4
VGS = 6.0V
ID, DRAIN CURRENT (A)

ID, DRAIN CURRENT (A)

1
3
VGS = 5.5V

TJ = 150oC TJ = 25oC
2
0.1
VGS = 5.0V

1
VGS = 4.0V VGS = 4.5V

0 10-2
0 3 6 9 12 15 0 2 4 6 8 10
VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

10 3.0
PULSE DURATION = 80µs PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE

VGS = 10V, ID = 1.7A


rDS(ON), DRAIN TO SOURCE

8 2.4
VGS = 10V
ON RESISTANCE
ON RESISTANCE

6 1.8
VGS = 20V

4 1.2

2 0.6

0 0
0 3 6 9 12 15 -40 0 40 80 120 160
ID, DRAIN CURRENT (A) TJ , JUNCTION TEMPERATURE (oC)

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 9. NORMALIZED DRAIN TO SOURCE ON


VOLTAGE AND DRAIN CURRENT RESISTANCE vs JUNCTION TEMPERATURE

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IRFR320, IRFU320

Typical Performance Curves Unless Otherwise Specified (Continued)

1.25 750
ID = 250µA VGS = 0V, f = 1MHz
NORMALIZED DRAIN TO SOURCE

CISS = CGS + CGD


1.15 600 CRSS = CGD
COSS ≈ CDS + CGD
BREAKDOWN VOLTAGE

C, CAPACITANCE (pF)
CISS

1.05 450
COSS

0.95 300

0.85 150 CRSS

0.75 0
-40 0 40 80 120 160 1 2 5 10 2 5 102
TJ , JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE

5 100
PULSE DURATION = 80µs PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX ISD, SOURCE TO DRAIN CURRENT (A) DUTY CYCLE = 0.5% MAX
gfs, TRANSCONDUCTANCE (S)

VGS = 0V
4

TJ = 25oC 10
3

TJ = 150oC TJ = 150oC TJ = 25oC


2
1

0 0.1
0 1 2 3 4 5 0 0.3 0.6 0.9 1.2 1.5
ID, DRAIN CURRENT (A) VSD, SOURCE TO DRAIN VOLTAGE (V)

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

20
ID = 3.1A

VDS = 320V
16
VGS, GATE TO SOURCE (V)

VDS = 200V
VDS = 80V
12

0
0 4 8 12 16 20
QG(TOT) , TOTAL GATE CHARGE (nC)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

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IRFR320, IRFU320

Test Circuits and Waveforms

VDS
BVDSS

L tP
VDS

VARY tP TO OBTAIN IAS


+ VDD
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS
0
0.01Ω
tAV

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

tON tOFF

td(ON) td(OFF)

tr tf
RL VDS
90% 90%

+
VDD 10% 10%
RG
- 0

DUT 90%

VGS 50% 50%


PULSE WIDTH
VGS 10%
0

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

VDS
CURRENT (ISOLATED
REGULATOR SUPPLY)
VDD

SAME TYPE Qg(TOT)


AS DUT VGS
12V
0.2µF 50kΩ Qgd
BATTERY
0.3µF
Qgs

D
VDS

G DUT
0

IG(REF) S
0
VDS IG(REF)
IG CURRENT ID CURRENT
SAMPLING SAMPLING
RESISTOR RESISTOR 0

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

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IRFR320, IRFU320

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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