ECE 474A/57A

Control and Datapath Interaction

Computer-Aided Logic Design

  Binary information in digital system Input data

can be classified into two categories

Control
Signals

Lecture 6   Data Input signal

(external)
Controller
(FSM)
Datapath

  Discrete elements of information

Algorithmic State Machines (ASMs)
Status
manipulated by arithmetic, logic, Signals

shift, and other data processing

  Operations implemented via digital Output
components such as adders, data

decoders, muxes, etc.

  Control
  Provides command signals that
coordinate the execution of various
operations in data section to
accomplish desired task

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What Control Path Implements? Flowcharts and Algorithmic State Machines (ASM)

  Sequencing of control signals to execute algorithm implemented by circuit   Flowchart

  Algorithm   Convenient way to graphically specify sequence of procedural steps and decision
  Finite set of instructions/steps to solve a problem paths for algorithm
  Terminates in finite time at a known end state   Enumerates sequence of operations and conditions necessary for execution

  Many representations
  Algorithmic State Machine (ASM)
Lamp doesn’t   Flowchart defined specifically for digital hardware algorithms
Ingredients work int fib(int n)
  1/3 cup unsweetened cocoa {
  1/4 cup cornstarch if (n < 2)
  2 tablespoons butter
return n;   Flowchart vs. ASM
  2 2/3 cups skim milk
Lamp plugged
No Plug in lamp
in?
else   Conventional flowchart
Steps return fib(n-1) + fib(n-2);
Yes }   Sequential way of representing procedural steps and decision paths for algorithm
1.  Combine all ingredients in a small saucepan.
2.  Heat over low heat, stirring constantly, until Yes   No time relations incorporated
mixture boils. Boil gently, stirring constantly, Bulb burned Replace bulb
for one minute. out?   ASM chart
3.  Pour into serving dishes and chill until No   Representation of sequence of events together with timing relations between states of
thickened.
sequential controller and events occurring while moving between steps
Buy new lamp

Recipe Flowchart Computer Program

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1
ASM Chart State box

  Three basic elements   Used to indicate states in control sequence

State name Binary code
  State box   State name and binary code placed on top
  Decision box of box Register operations
Moore-type output signals
  Conditional box   Register operations and names of output
signals generated in state placed inside box
  State and decision boxes used in conventional flowcharts
  Conditional box characteristic to ASM
  Example
  State name: S_pause
From exit path of decision box   Binary encoding: 0101
State name Binary code
  Register operation: R ← 0 S_pause 0101
Register operations Condition Register operations   Register R is to be cleared to 0 R←0
Moore-type output signals Start_OP
Mealy-type output signals
  Output signal asserted: Start_OP = 1
Exit path Exit path
Exit path   Launches some operation in datapath

State Box Decision Box Conditional Box

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Decision Box Conditional Box

  Reflects the effect of an input   Unique to ASM

From exit path of decision box
  external or internal, input or status
Condition
  Inputs come from one of exit paths of
decision boxes Register operations
  Diamond shaped box Exit path Exit path   Register operation or outputs listed inside Mealy-type output signals

  Condition to be tested inside Exit path box generated during given state
  Two or more outputs represent exit paths   Generated as Mealy-type signals
dependant on value tested   Associated with the state transition
  In binary case one path represents true the
other false, represented by 1 and 0   Example
respectively
B
  Status of input B checked B
1 0 1 0
  Conditional operation executed depending
  Example on result coming from decision box
  Check B   If B = 1, assert Incr_Reg signal Incr_Reg

  If B is true (=1), take path marked 1   Otherwise Incr_Reg remains unchanged

  If B is false (=0), take path marked 0

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2
ASM Block Interpretation of Timing Operations

Reset_b Reset_b
  Structure consisting of   Conventional flowchart, evaluation of
  One state box S_0 001 each follows one another S_0 001

  All decision and conditional boxes A←A+1   Reg A incremented A←A+1

associated with its exit paths   Condition E evaluated
  Block has one entrance and any   If E= 1
E E
number of exits paths 0 1   clear B 0 1

  Each block in ASM dedicated to state F Clear_B

  Go to state S_3 F Clear_B
0 1 0 1
of system during one clock cycle
S_1 010 S_2 011 S_3 100   In ASM the entire block considered as S_1 010 S_2 011 S_3 100

  Simplifications one unit

  All operations within block occurring
  ASM Block not usually drawn because
blocks are well defined during single edge transition
  The next state evaluated during the
  Can label just the “1” and omit the “0”
same clock
  System enters next state S_1, S_2, or
  ASM chart consists of one or more S_3 during transition of next clock
interconnect ASM Blocks
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ASM Example ASM Example Continued

Reset_b
  Convert pseudo code to ASM chart S0:
busy = 0;
S0:
busy = 0;
ones = 0; S_0 001 ones = 0;
busy = 0
  Example if(start == 1) ones = 0 if(start == 1)
goto S1 goto S1
  Want to detect the number of 1’s in a 2- else else
start == 1
bit register called Input goto S0 goto S0
S1: 1 S1:
  start input indicates when to begin busy = 1; busy = 1;
S_1 010
comparison if(Input[1] == 1) if(Input[1] == 1)
busy = 1
ones ++; ones ++;
  busy output indicates when comparison in
progress goto S2 Input[1] == 1
1 goto S2
  ones hold count value S2: S2:
busy = 1; ones++ busy = 1;
  F outputs result if(Input[0] == 1) if(Input[0] == 1)
ones ++; ones ++;
S_2 011
goto S3 busy = 1 goto S3
S3: S_3 111 S3:
busy = 0; busy = 0
busy = 0;
1
F = ones; Input[0] == 1
F = ones
F = ones;
ones++
goto S0 goto S0

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3
 ASM – Mux ASM – Full Adder

  Describe a 4x1 MUX using a ASM   Describe a 1-bit full adder using
S_0 001
an ASM chart
x1 x2 x3 x4 s1 s0 f
A B S_0 001
0 0 x1
1
s0 0 1 2 3 0 1 x2 s1
cout FA cin
s1
1 0 x3 1
a
1 1 x4 1 1
F
s0 s0
f 1 1
b b
4x1 mux a b cin f cout
F = x4 F = x3 F = x2 F = x1
0 0 0 0 0 1 1 1 1
cin cin cin cin
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
f=1 f=0 f=0 f=1 f=0 f=1 f=1 f=0
1 0 0 1 0
cout = 1 cout = 1 cout = 1 cout = 0 cout = 1 cout = 0 cout = 0 cout = 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Smaller Multiplier Smaller Multiplier -- Sequential (Add-and-Shift) Style

  Multiplier in array style   Smaller multiplier: Basic idea

  Fast, reasonable size for 4-bit: 4*4 = 16 partial product AND terms, 3 adders   Don’t compute all partial products simultaneously
  Rather big for 32-bit: 32*32 = 1024 AND terms, and 31 adders   Rather, compute one at a time (similar to by hand), maintain running sum

32-bit adder would have 1024 gates here

Step 1 Step 2 Step 3 Step 4
a3 a2 a1 a0 0110 0110 0110 0110
+ 0 0 11 + 0 01 1 + 00 1 1 + 00 1 1
b0
pp4 pp3 pp2 pp1

(running sum) 0000 00110 010010 0010010

b1 (partial product) + 0 1 1 0 +0 1 1 0 + 0000 + 0000
a
0 0
(new running sum) 0 0 1 1 0 010010 0010010 00010010

b2
+ (5-bit)
00 a
b3
+ (6-bit)
0 00

+ (7-bit) ... and 31 adders here (big adders)

p7..p0
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4
Smaller Multiplier -- Sequential (Add-and-Shift) Style Smaller Multiplier -- Sequential (Add-and-Shift) Style
multiplier multiplicand
multiplier multiplicand Step 0
  Design circuit that computes one •  Set running sum to 0 start
start
partial product at a time, adds to multiplicand •  Load values
multiplicand
mdld register (4)
running sum mdld
load
register (4) load 0110
  Note that shifting running sum
right (relative to partial product) Step 1
after each step ensures partial •  Check multiplier bit 0 (mr0)
•  mr0=1, add multiplicand to running sum
product added to correct running •  Shift running sum right 1 position
sum bits multiplier

controller
multiplier

controller
mrld register (4) mrld
load 0011
register (4)
load Step 2
mr3 4-bit adder
mr3 4-bit adder •  Check multiplier bit 1 (mr1)
•  mr0=1, add multiplicand to running sum mr2
mr2
mr1
mr1 •  Shift running sum right 1 position
mr0
mr0
rsload
rsload Step 3 load
load rsclear running sum
rsclear running sum •  Check multiplier bit 2 (mr2) clear
clear rsshr
rsshr shr register (8) •  Shift running sum right 1 position
shr 00000000
00010010
00100100
01001000
10010000
00110000
01100000
register (8)

Step 1 Step 2 Step 3 Step 4

0110 0110 0110 0110
+ 001 1 + 0 01 1 + 0011 + 0011
Step 4
•  Check multiplier bit 3 (mr3)
0000 00110 010010 0010010 (running sum)
•  Shift running sum right 1 position
+ 0110 +0 1 1 0 + 0000 + 0000 (partial product) product
product
00110 010010 0010010 0 0 0 1 0 0 1 0 (new running sum)

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ASM – Sequential Multiplier ASMs to FSMDs

multiplier multiplicand
Reset_b start
multiplicand
  Able to convert between formats
mdld register (4)
S_0
load   Once we have a FSMD, we’ve already seen how to implement in hardware
Reset_b
S_pause 0101 A1 0101
multiplier S_0 001
start
controller

1 R←0
mr1 mrld register (4) A←A+1
1 load Start_OP
rsload = 1 mr3 4-bit adder
S_1 mr2 1 B 0
S_4 mr1 0 E 1
mdld = 1 mr0
rsshr = 1 F
mrld = 1 Incr_Reg 0 1 Clear_B
rsclear = 1 rsload load
1 rsclear clear running sum S_1 010 S_2 011 S_3 100
mr2 rsshr shr register (8)
S_2
rsload = 1
S_5
1 rsshr = 1
mr0
rsload = 1 product
1
mr3 S_0 A=A+1
S_3
rsload = 1 S_pause A1 E’F’
rsshr = 1 E / Clear_B = 1
R=0 E’F
S_6 B B’ / Incr_Reg = 1
Start_OP = 1
rsshr = 1
S_1 S_2 S_3

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5
Not Used Much, But …

  There are commerical ASM Editors

  Mentor Graphics
  Summit Design, Inc.
  Others…

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