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Minimizing the effect of IR drop to improve the signal integrity in high speed
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 Minimizing the effect of IR Drop to improve the Signal Integrity in High Speed
On-Chip SOC.
V.Kameswar Rao1, P R Sekhar2, Srinivas.D3, P.K.Seshu4, R.Henry5, R Udaiya Kumar6
1,2,3,4
PG Scholar, 5 Lecturer, 6Senior Lecturer, Department of Microelectronics and VLSI design,
International Institute of Information Technology, Pune. Phone: +91-9860564603

Abstract
Today's very deep sub-micron
semiconductor technology has enabled large-
scale integration of multi-million gates on a
single chip. Signal integrity (SI) is and will
continue to be a major concern in Very High
Speed deep sub-micron VLSI designs where the
proximity of signal carrying lines leads to
coupling effect, crosstalk, glitches, unpredictable
signal delays and other parasitic side effects. Figure1. Low Power IC design with multi
However, at present there are no standard test supply voltages and different threshold voltages
methods that are capable of detecting the various
faults related to signal integrity. This paper is Multiple supply voltage (Vdd) designs also need
addressing some of the signal integrity issues to use level shifters. Because of circuit
related to timing (glitches) [5] and IR drop due complexity, it is more difficult to verify that a
to the effect of cross talk between two I/Os level shifter is not suffering from any noise
operating at high frequencies. We also try to problems. Low power designs also use gates at
analyze and validate the SI effects by multiple threshold voltage (Vt), values. Devices
representing the different transmission with high Vt generally have a higher holding
interconnects models functioning in multi-supply resistance, which makes them more vulnerable as
voltage design with different clock frequencies. victims of crosstalk. Lower Vt devices, on the
other hand, are worse as attackers due to their
Key Words: crosstalk, IR Drop, glitches, power faster transition times. They also tend to be more
dissipation, coupling effect. sensitive to waveform effects at their inputs.

Introduction Implementation

SI issues of High Speed I/O Interfaces in Low 1) Lumped Model

Power VLSI Design.
Signal integrity generally covers several
types of issues that can cause signals to behave
in unexpected ways like a) timing changes due to
crosstalk b) Noise (glitches) due to crosstalk c)
Voltage (IR) drop.
The objective of the Signal Integrity for low
power IC Design.
--To improve the impedance matching.
--Minimize the effect of switching threshold.
--To increase the slew rate.
--To minimize IR Drop.
The circuits parasitic of a wire are
distributed along its length and are not lumped
into a single position. Yet, when only one
parasitic component is dominant, when the
interaction the component is small with aspect to
the circuit behavior. [10] [2] The advantage of
this approach is that the effects if the parasitic
can be described by an ordinary differential
equations.

In low power design techniques, Circuits are

designed using multiple supply voltages and
multi-threshold devices, which can create Figure 2: Reflected Signal at the load
coupling effect between signals at different (lumped model)
voltages. Coupling from a higher voltage to a
lower voltage is much more severe than coupling
The distributed model is complex, and also has
between signals of the same voltage.
no closed form solutions exist. The simple
lumped model can adequately design the
behavior of the distributed model.
A common practice is to study the transient
behavior of the complex transistor interconnect
wire networks is to reduce the circuit to reduce to
simple RLC or RC network. However this to
means to analyze such a network in order to
analyze the first order of the equation.
If a short length of a transmission line is
considered, then the lumped approximation
applies and the transmission line can be
modeled, as shown in Figure 2, with series
resistance and inductance and with shunt
capacitance and conductance.
Figure 3. Lumped model of a short length of a
transmission line.
Applying Kirchoff’s voltage law around the
loop, then
v (z +∆z, t) − v(z, t) = −Ri(z, t) − L [di(z, t)/dt]
(1)
Similarly, Kirchoff’s current law applied at z
+∆z yields
i(z +∆z, t) − i(z, t) = −Gv(z +∆z, t) − C[dv(z
+∆z, t)/dt] (2)
Divide through by ∆z and let ∆z → 0, then (1)
and (2) transform from difference equations to
the differential equation
[∂v(z, t)/∂z] = −ri (z, t) − l [∂i (z, t)/∂t] (3)
[∂i(z, t)/∂z] = −gv (z, t) − c [∂v(z, t)/∂t] (4)
Where the lumped component values transition
to the per-unit-length quantities r, l, c, and g due
to normalization by ∆z. Simultaneous solution of
the transmission line equations (3) and (4) yields
the voltage and current at any point on the
transmission line.
Analyzing the Interconnect Model
IR Drop Analysis (Reflection Coefficient)
using S-parameters
To evaluate or analyze interconnect
across the two end; [4] the signal integrity
analysis of high-speed electronic designs
requires that the interconnect models be valid
over a wide bandwidth. To represent the
frequency-dependent behavior of a complex
structure, S parameters, which have long been
used in the microwave community, are
beginning to gain popularity in the analog and
digital designs.
vv
Figure 4 S-Parameter Models for Two Port
Network
If we consider that a resistor (R) relates the total
voltage (V) to the total current (I) through
(R)(I)=(V), then the S parameters relate the
incident voltage wave (V+) to the reflected and
transmitted voltage waves (V-) through
(S)(V+)=(V-). The concept of S parameters is
crucial to the high-speed design process because
the wave phenomena are much more prominent
at high frequencies, and to achieve the desired
"transmitted" voltage, we would want to tune a
system for minimum "reflection," for
example.[7] As we head for the 90nm and 65nm
silicon processes, the use of S parameters will
become even more important, because the fast-
switching analog and digital ICs can be best
characterized through similar procedures adopted
in the RF or microwave designs. The large
reflected wave travels back to the driver where it
is absorbed by the matched source impedance.
[10] Due to the presence of the reflected
waveform, the signal integrity along the
transmission line is not good, but it can be quite
good at the load, which is where it matters for a
point to- point net. Once the load capacitance is
charged, then the driver no longer needs to
supply current to hold the receiver in the logic
high state; therefore, the static logic condition
does not dissipate power.
However, the reflected wave is
significant and can cause difficulties on more
complex topologies (such as multi-drop nets).
Also, a bidirectional bus using source
termination can be slower because it must wait
for the signal to return and terminate in the
source impedance before the bus can be turned
around into receive mode.
Finite Difference Time Domain Method
One popular way to circumvent this
mixed time/frequency domain problem is to
extend the full-wave finite-difference time
domain (FDTD) method to include lumped
circuit elements .However, for the simulation of
hybrid complex interconnect and circuit systems,
this method often suffers from the CPU
inefficiency and convergence problems. An
alternative way to address this mixed-domain
problem is to utilize the macro modeling
approach, in which a difficult and complex
system is modeled by an approximate but fairly
accurate system in order to facilitate the
simulation. An interconnect macro model
characterizes the behavior of an n-port
interconnect sub network embedded in a circuit
package containing microwave, RF, analogue,
and digital circuits. One macro modeling
approach is rooted in the interconnect
representation using frequency-domain sampling
data.
In Equation (6) aj ; bj ; cj ; dj ; ej ; fj ; gj and hj
are constants specific to element j. Note that this
expression for potential satisfies the Laplace
equation. For an element j, if (xi; yi; zi); are its
eight nodes, and the node potentials, j (xi; yi; zi);
are known, then Equation (7), can be re-written
in terms of these eight node potentials, and other
shape functions,Ni j (x; y; z);
By starting with the variational formulation of
the equations along with the boundary conditions
using Equations 6 and 7 in it, Equation 6 that
relates current at the eight nodes to the voltage at
the eight nodes can be obtained [10]
This paper presents a proposed accurate
and systematic approach for the transient
simulation of high-speed planar interconnect
system, which integrates the macro modeling
method based on the full-wave time-domain
method and rational function approximation with
the SPICE circuit simulation approach. The
FDTD method is employed to extract the
discrete frequency-sampling admittance Y
parameters of the sub network, comprising
interconnects with fairly complex geometry.
The macro model of the interconnect
sub network can then be created through a
rational function approximation approach by
using the vector fitting method
Extraction of Interconnect S-Parameters by
using 3D FDTD
The three-dimensional (3D) FDTD
algorithm is based on the discretization of
Maxwell’s differential equations by using a
central difference and staggering field
component arrangement in which the Maxwell’s
equations governing the electromagnetic fields in
the isotropic and inhomogeneous media are
given by
where the vectors E and H are the electric field
(volts/meter) and magnetic field [9][8]
amperes/meter), respectively. The constants and
are the respective electrical permittivity
(farads/meter) and magnetic permeability
(henrys/meter).
Crosstalk
Crosstalk noise between neighboring signal
wires can cause two major problems that affect
the operational integrity of IC designs:
1) Crosstalk delay changes the signal
propagation on some of the nets, reducing
achievable clock speed as illustrated in Figure 5
2) Crosstalk glitch causes voltage spikes on
some nets, resulting in false logic states being
captured in the registers
Figure 5: Crosstalk Effects at higher frequency.
View publication stats
Analysis and Validation
Validation Analysis and Validation of Voltage
Drop at Higher Frequency
1. The integral formulation of faraday’s law
corresponds to the voltage drop, generated from
time varying magnetic field.
2. Generation of Reflection and Transmission
coefficient using S-parameters.
Error Occurs
Signal levels(V)
VIH
Sampling window
No Error Occurs
Figure 6: Impact of IR Analysis on Timing
Sensitivity.
3. Impedance Matching is performed using
lattice bounce diagram.
4. Glitch occurs when a strong driver with a fast
edge rate causes a neighboring net with a weaker
driver to change its state.
5. IR drop lowers the supply voltage to the
affected cell, leading to larger gate and signal
delay that can consequently cause timing
degradation in the signal paths as well as clock
skew.
6. Lower power supply causes current which
reduces the noise margins and compromises the
signal integrity of the design
Future Scope:
As the frequency increases there is
increase in Power Dissipation with increase in
technology scaling. Well there is attempt to
investigate the effect of inductance and also
analyze the impact of time of flight in compared
to the lumped RC model at higher frequencies.
References
1) Q. J. Zhang, F. Wang, M.S. Nakhla, J.W.
Bandler', and R.M. Biernacki' “Signal Integrity
Optimization of High-speed VLSI Packages and
Interconnects”
2)http://www.intel.com/education/highered/signa
l/index.htm
3)Mick Grant, Design Engineer, “Signal
Integrity Considerations for High Speed Digital
Hardware” -White Paper Issue: 01, 11th
November 2002
4)Andrew B. Kahng, Sudhakar Muddu, Egino
Sarto,SiliconGraphics,Inc.
MountainView,A94039fmuddu,sartog@mti.sgi.c
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Strategies for High-Performance VLSI Designs”
Dieter Stoll,Fachhochschule
Konstanz(university of applied sciences)
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