2011 IEEE Student Conference on Research and Development
Transient Analysis for On-Chip High Speed VLSI
RLCG Global Interconnect for Unit Impulse Input
1
Vikas Maheshwari, 1Abhishek Sharma, 2Aurijoy Majumdar, 2Rajib Kar, 2Durbadal Mandal
1
Department of Electronics and Communication Engg.
Hindustan College of Science and Technology, Mathura, Farah -281122
2
Department of Electronics and Communication Engg.
National Institute of Technology, Durgapur-9, West Bengal, INDIA
1
maheshwari_vikas1982@yahoo.com, 2rajibkarece@gmail.com
Abstract—In paper, the time domain waveform is
approximated for calculation of delay time, peak time, settling
time, damping ratio and natural frequency for a second order
RLCG interconnect model. It can also be used for multiple
interconnect systems but higher order systems are ignored to
avoid complexity. The model is applied to a single resistance-
inductance-capacitance-conductance model which can also be
extended to multi-interconnect systems to analyze the rise time
and settling time for similar analysis. The model evaluates the
performance of a system which is expressed in terms of the
transient response for the unit impulse input because it is easy to
generate and evaluate the delay analytically. The transient
response of a system to a unit impulse input depends upon the
initial conditions. In this paper, a new interconnect model is
presented; the model is based on the time domain analysis with a
unit impulse input signal for on-chip high speed RLCG
interconnection network. On-chip inductance and conductance
are shown to have a profound effect on the high performance IC
design methodologies. In the proposed model, it is shown that
when the value of the shunt conductance (G) is increased, the time
at which the rise time, settling time and steady state condition is
reached, is increased. Hence, for high speed circuit one must
increase the value of G, so that the steady state condition is
reached as soon as possible. It is also shown that with the increase
in the value of G, the delay will reduce. The simulation results
performed in Cadence SPICE environment justify the efficacy of
the proposed model.
Keywords- Time Domain Analysis, Damping Ratio, Natural
Frequency, Delay Calculation, RLCG Interconnect, VLSI.
I. INTRODUCTION
In the past decades, the integrated circuits and systems have
become both larger in silicon area and faster in operation. As
integrated circuit’s feature size continues to scale well below
0.18 microns [1], active device counts are reaching hundreds
of millions. The amount of interconnect among the devices
tends to grow super linearly with the transistor counts, and the
chip area is often limited by the physical interconnect area. In
deep sub micrometer integrated circuits, interconnect delay
dominates gate delay. In the present day VLSI technology, the
wire inductance can no longer be ignored, due to higher signal
frequencies and longer wire lengths. Accurate and efficient
resistance-capacitance-inductance-conductance (RLCG)
interconnect models are, therefore, critical in the design of
high performance integrated circuits. The transient time is the
time between zero to the steady state value at which the
978-1-4673-0102-2/11/$26.00 ©2011 IEEE
system is under operating conditions. In this RLCG network,
we evaluate the delay by using an analytical approach; the
delay is directly evaluated by tplh/2. In this paper, we present
an accurate analytical delay estimate for distributed RLCG
interconnects. Generally in cases when high frequencies are
considered, no insulator can act like a perfect insulator (as
typically considered as ideal), thus there is always a
probability of leakage, and conductance is considered as a
measure of this leakage. We have made the following
contributions in this paper: We have proposed a closed form
expression for delay metric for on-chip VLSI interconnect
using distributed RLCG model. With the increase in speed of
high performance VLSI circuits, inductance and conductance
effect of interconnects are becoming more and more important
and can no longer be neglected. Under this circumstance, the
Elmore model [2] is inadequate since this model takes only the
resistance and capacitance effects into account. It is necessary
to use a second order model, which includes the effect of
inductance and conductance. There are several approaches
proposed to estimate the on-chip interconnect performance
characteristic; where the interconnect is modeled as distributed
RLCG segment [3-5].
The rest of the paper is organized as follows: basic theory
of transmission line when considered as a distributed RLCG
model is discussed in section 2. Section 3 discusses on the unit
impulse function which is considered as an input for the on-
chip interconnect delay calculation. Proposed model of RLCG
interconnection network is given in section 4. Simulation
results are shown in section 5 and finally section 6 concludes
the paper.
II. BASIC THEORY
A. Transmission Line Model
Defining the point at which an interconnect should be
treated as a transmission line and hence reflection analysis
applied has no consensus of opinion. A rule of thumb is when
the delay from one end to the other is greater than risetime/2
[6], the line is considered as electrically long. If the delay is
less than risetime/2, the line is said to be electrically short.
A transmission line can be described at the circuit level
using series inductance and resistance combined with shunt
capacitance and conductance. An infinitesimal unit length of
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the transmission line looks like the circuit in Figure 1. In The pulse for which the duration tends to zero and amplitude
Figure 1, tends to infinity is called impulse function. Impulse function is
R = Series Resistance per unit length also known as delta function,
A unit impulse can be defined as,
L = Series Inductance per unit length ;t≠0
⎡0
G = Shunt Conductance per unit length δ(t) = ⎢ (1)
⎣∞ ;t=0
C = Shunt Capacitance per unit length.
IV. PROPOSED DELAY MODEL
We have obtained an analytical delay model, based on the time
domain analysis RLCG interconnection lines, which considers
the effect of conductance. The analytical delay models
proposed for RLC interconnect reported in [8-9] do not
consider the effect of shunt conductance in interconnect
modeling. The exact transfer function of a widely used
interconnect model [10] is described in this section and a time
domain analysis of a typical on-chip signal is done and is
represented by the interconnection network which is being
Figure 1. RLCG Segment of a Transmission Line
evaluated for 0.18 μm technology. An interconnect model is
It is critical to model the transmission path when designing shown in Figure 2. An interconnect is represented by a
a high-performance, high-speed serial interconnect [7] system. distributed RLCG transmission line, where R, L, C and G are
The transmission path may include long transmission lines, the resistance, inductance, capacitance and conductance per
connectors, vias and delay from adjacent interconnect. Values unit length. The load of the interconnect [10] is modeled as a
for R, L, C, and G are extracted from a given geometry in 0.18 conductance.
micron technology as shown in Figure 2. By applying Kirchhoff’s voltage law in the network, we can
write,
1 (2)
V = i R + i sL + (i -i )
1 1 1 1 2 sC
1 1
-i . -(i -i ) =0
2 G 2 1 sC (3)
1
V =i .
2 2G (4)
By solving the above three equations we obtain the open loop
transfer function,
Figure 2. Equivalent circuit model for an RLCG distributed interconnect.
1
V (5)
III. IMPULSE FUNCTION G(s) = 2 = LC
V 2 ( RC + LG ) ( RG + 1)
In Figure 3, the first pulse has a width T and a height of 1/T 1 s + s+
LC LC
such that the area of the pulse is T×1/T=1. If we halve the
Consider the time response of second order system, in which
duration and double the amplitude we get the second pulse.
we consider the closed loop transfer function which can be
The area under the second pulse is also unity. Note that the
written as,
duration of the pulse approaches infinity but the area of the
pulse is unity. V G (s) ω 2 (6)
2= = n
V 1 + G ( s ) H ( s) s 2 + 2ζωns + ω 2
1 n

where ωn and ζ are the natural frequency and damping

ratio. So the characteristic equation for this transfer function
can be written as,
1 + G ( s) H ( s) = 0 (7)
For unity feedback as shown in Figure-4 and the unit
impulse input, the above equation can be written as,
Figure 3. Impulse Response Representation
1 + G ( s) = 0 (8)
Now by using (5) the characteristic equation can be written
as,

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 1 (9) results in an error of less than 3% compared to that of SPICE
1+ =0 simulation.
(RC + LG) (RG + 1 )
s2 + s+
LC LC
TABLE I. RLCG PARAMETERS FOR A MINIMUM-SIZED WIRES IN A
After simplifying the characteristic equation for a unity 0.18MICRON METER TECHNOLOGY AND THE DELAY MODEL PARAMETERS.
feedback system can be written as,
Parameter(s) Value/m
(RC + LG) (RG + 2 )
s2 + s+ =0 (10) Resistance(R) 120 kΩ/m
LC LC Inductance(L) 270 nH/m
Conductance(G) 15f pS/m
Now comparing the characteristic equation of second order Capacitance(C) 240 pF/m
system with unity feedback with (5), we obtain the values of
ω and ζ which are the natural frequency and damping ratio.
n
RG + 2
ω = (11)
n LC
RC + LG
ζ = LC (12)
RG + 2
2
LC
Figure 5. Sample Dimensions of Cross-sections of minimum sized wire in a
0.18µm technology

TABLE II. COMPARISON OF PROPOSED DELAY WITH SPICE DELAY

R L
(KΩ) (nH)
C G
(pF) (mS)
ωn ζ Proposed
delay
Spice
Delay
rad/sec Td (ns)) Ts (μs))
(1010 )
1.2 2.7 2.4 1.5 2.42 9.19 3.0 2.87
1.2 2.7 2.4 2.25 2.69 8.27 2.25 2.75
1.2 2.7 2.4 3 2.93 7.60 1.50 1.35
Figure 4. Block diagram of second order system 1.2 2.7 2.4 3.75 3.15 7.07 1.25 1.49

IV. EXPERIMENTAL RESULTS
The extracted values for the parameters R, L, C, and G are
given in Table 1. The sample dimension of cross-sections of
minimum sized wire in a 0.18µm technology is shown in
Figure 5. Substituting the values of RLCG for 0.18 micron
technology in the proposed delay model we obtain the various
parameters which are required to synthesize the
interconnection network. In this transient analysis, we consider
a closed loop system for a unit impulse input. Table 2 shows
the values of the R, L, G, C, ωn , ζ and delay (Td) by which we
obtain an closed loop response of a LTI system. These
parameters are very useful for analysis of any system and
evaluating the response of that system. This analytical model
evaluates the performance of high speed interconnection
network by calculating the delay. The delay is calculated by
evaluating the rise time of a linear time invariant system. This
model also evaluates the settling time, maximum overshoot,
and maximum amplitude of the LTI system.
ωn defines the natural frequency, ζ is the damping ratio, Td is
the delay obtained from proposed model and Ts is the proposed
model calculated using SPICE. The proposed delay model is
being compared with the delay obtained from SPICE model in
the Table 2. Table 2 shows that the proposed delay calculation
We have obtained an analytical delay model, based on the time
domain analysis RLCG interconnection lines, which considers
the effect of conductance. Table 3 shows that with the increase
in the value of G the delay will reduce. All these analysis are
being done with time domain parameters and by using the
values of RLCG in the network. We evaluate the rise time (Tr),
settling time (Ts) and it is shown in Table 3 that when the value
of G is increased, the rise time and settling time will reduce,
hence the delay , denoted by td, will also be reduced. Figure 5
shows the unit impulse response for a closed loop LTI system
for different values of ζ and ωn . Figures 7-10 show the spice
output for the given RLCG network for different values of G
keeping other parameter’s values constant. From which the
delay can be evaluated for the same parameters as shows in
Table -3.
Table 3 shows the delay calculated using Tp, Ts where Tp is
the time to reach the peak amplitude and ts is settling time. Td is
the delay obtained from the proposed model.

349
 TABLE III. RLCG PARAMETERS FOR A MINIMUM-SIZED WIRES IN A
0.18MICRON METER TECHNOLOGY AND THE TIME DOMAIN ANALYSIS
PARAMETERS

R L C G Peak Settling delay

(KΩ) (nH) (pF) (mS) amplitude time Td (ps)
time Tp (ps) Ts (ns)
1.2 2.7 2.4 1.5 14.3 2.98 3.07
1.2 2.7 2.4 2.25 12.0 2.41 2.67
1.2 2.7 2.4 3 11.9 2.04 2.47
1.2 2.7 2.4 3.725 11.2 1.76 1.98

Figure 8. A Spice model for delay calculation in RLCG network using

values R(KΩ)=1.2, L(nH)=2.7, C(pF)=2.4 and G(mS) =2.25 in a 0.18µm
technology.

Figure 6. A Spice model for delay calculation in RLCG network for the
values R(KΩ)=1.2, L(nH)=2.7,C(pF)=2.4 and G(mS) =1.5 in a 0.18µm
technology.

Figure 9. A Spice model for delay calculation in RLCG network using

values R(KΩ)=1.2 ,L(nH)=2.7,C(pF)=2.4 and G(mS) =3.0 in a 0.18µm
technology

Figure 7. A Spice model for delay calculation in RLCG network for the
values R(KΩ)=1.2, L(nH)=2.7,C(pF)=2.4 and G(mS) =1.5 in a 0.18µm
technology.

Figure 10. A Spice model for delay calculation in RLCG network using
values R(KΩ)=1.2, L(nH)=2.7,C(pF)=2.4 and G(mS) =3.725 in a 0.18µm
technology

350
In Figures 7-10, we evaluate the delay using spice for different
values of G. It can be analyze that the delay is reduced by for
large value of G.
V. CONCLUSION
We have obtained an analytical delay model shown in the
block diagram of the second order control system which
considers the effect of conductance. The resulting delay
estimates are significantly more accurate in comparison to
other delay model and it will evaluate the performance of this
interconnection network by increasing the value of
conductance the delay will reduce. The derived expression
along with the analysis can serve as a convenient tool for
delay estimation without much computation during design.
Simulation results demonstrate the validity and correctness of
our proposed model. It is also shown that when the value of G
is increased the time at which the rise time, settling time and
steady state condition is reached, is increased. So, for high
speed circuit, the value of G is as high as possible so that the
steady state condition is reached as soon as possible. It is also
demonstrated that with the increase of G the delay will reduce.
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