Professional Documents
Culture Documents
PowerElectronics
November, 2015
Revision Table
Version Date Author Revised by Approved by
PAGE 1 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
Revision History
Revision Date Author Log
3.0 Nov 2015 Antonio Created
Jiménez
PAGE 2 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
Table of contents
1 ABSTRACT .............................................................................................................. 4
2 GEPVG/GEPVE MODEL OVERVIEW .................................................................. 5
3 INVERTER MODEL ................................................................................................ 6
3.1 LOAD FLOW PARAMETERIZATION........................................................... 6
3.2 DYNAMIC MODEL ......................................................................................... 6
3.2.1 Converter Model ......................................................................................... 7
3.2.2 Control Model ............................................................................................ 9
3.2.3 Creation of references ............................................................................... 14
3.2.4 Protections ................................................................................................ 15
4 POWER PLANT CONTROLLER (PPC) MODEL ............................................... 16
5 MAIN PARAMETERS ........................................................................................... 20
6 TEST BENCH ......................................................................................................... 23
6.1 Test bench overview ........................................................................................ 23
6.2 TEST 0: INITIALIZATION ............................................................................ 25
6.3 TEST 1: INVERTER POWER COMMANDS ............................................... 26
6.4 TEST 2: PPC FREQUENCY CONTROL ....................................................... 28
6.5 TEST 3: PPC VOLTAGE CONTROL ............................................................ 31
6.6 TEST 4: PPC POI Q CONTROL .................................................................... 33
6.7 TEST 5: PPC POI PF CONTROL ................................................................... 35
6.8 TEST 6: FREQUENCY + VOLTAGE CONTROL ........................................ 37
7 ATTACHED FILES................................................................................................ 39
PAGE 3 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
1 ABSTRACT
The present report has the following main objectives:
Explain how to use the inverter models based on GEPVG/GEPVE: Descriptions, diagram
blocks, parameterization, etc…
Explain how to use the implemented PPC: Diagram blocks, descriptions,
parameterization, interconnection with GEPVE control model, etc…
¡An aggregated machine of the photovoltaic field is required in order to introduce the
implemented PPC! (1 aggregated inverter/PPC)
PAGE 4 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
The converter model injects real and reactive current into the network in response to
control commands and represents low and high voltage protective functions. The real
power signals are initialized to the generator output in the power flow.
Plant Controller functions: closed loop voltage regulation system (VRS) and reactive
power control.
Electrical Controller functions: reactive current regulation, active current regulation
and converter current limit.
The plant controller functions implemented within the control model (GEPVE) are not
usually used in the PE models and should be deactivated.
PAGE 5 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
3 INVERTER MODEL
3.1 LOAD FLOW PARAMETERIZATION
At Load Flow stage, the PV inverter is modeled as a conventional generator connected
to a 400V bus (no dynamic model is needed) using a transformer. The power (MVA) of
this generator must be equal to the device ratings.
The next table shows ratings for an inverter of 1.32MVA with a power factor range
until 0.8 lead – 0.8 lag.
The inverter will prioritize real power production over reactive power production to
ensure the overall inverter current limits are respected.
In case of using a different inverter model, previous table must be filled with
corresponding values obtained from Power Electronics Freesun HE inverter datasheet.
Converter model [GEPVG]: It injects active and reactive current into the grid in
response to control commands, as power signals that initially have the corresponding
values from the power flow.
Control model [GEPVE]: It sends active and reactive power commands to the converter
model. Its main function is the reactive power control which can be referenced from a
voltage regulation (VRS), from power factor control or directly reactive power
command.
Protections: under/over voltage protections and under/over frequency protections.
PAGE 6 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
The Low Voltage Power Logic (LVPL) reduces the systems stress during and
immediately following sustained faults by limiting the real current command with both
a cap and a ramp rate limit. When the voltage falls below the first and second limit
(VLVPL3 and VLVPL2), a calculated cap for the real power is applied, being zero if
the voltage keeps falling under the third limit (VLVPL1). In case of voltage recovery,
this means voltage over the first limit, the cap is substituted by a ramp rate limit (ramp
up) achieving the normal working.
The Low Voltage Active Current Management is the function that calculates the
previous mentioned cap to apply to the LVPL block.
The High Voltage Reactive Current Management suppresses reactive current injection
when the terminal voltage rises excessively.
PAGE 7 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
GEPVG
VARs # DESCRIPTION
L Active component of the injected current, pu
L+1 Reactive component of the injected current, pu
L+2 Vterm magnitude on previous iteration
L+3 Vterm angle on previous iteration
L+4 Overvoltage correction factor
[*] The rated power [MVA] of the machine must be set in CON(J)
PAGE 8 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
Electrical control
This part consists basically in the regulation of the active and reactive powers (from the
reference provided from the active power command and the reactive power control).
The reactive power part of the voltage dip response (LVRT) is carried out in the
reactive power branch when comparing the reactive signal converted to voltage with
Eterm. This generates a value to be canceled by the integrator KVI which leads to
remain delivering the maximum amount of reactive current. On the other hand, due to
(in case of voltage dip) the terminal voltage is under the lowest limit of the LVPL
(VLVPL1, at the converter model), the active power is limited to zero by the Low
Voltage Active Current Logic. At this point, when voltage increases back over the
highest limit of the LVPL (VLVPL3) a ramp rate limit (ramp up) is applied for the
active power recovering.
PAGE 9 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
PAGE 10 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
PAGE 11 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
GEPVE
VARs # DESCRIPTION
L Remote bus reference voltage
L+1 Q ref. if PFAFLG=0 & VARFLG=0
L+2 PF angle ref. if PFAFLG=1
L+3 Branch MW for Qdroop
L+4 Branch MVAr for Qdroop
L+5 Branch MVA for Qdroop
L+6 Auxiliary test signal
PAGE 12 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
L+7 Porder
[*] These parameters are not used if VARFLAG and PFAFLAG are set to 0
(recommended values).
PAGE 13 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
The active power reference is provided initially by the power flow although it can be
changed later by mean of introducing the command as a variable in the Control model
(GEPVG VAR[L+7]).
In order to introduce reactive power commands to the GEPVE model, PFAFLG and
VARFLAG must be set to 0.
If the interconnection with the PowerElectronics PPC is required, the VARFLG and
PFAFLG of the GEPVE model must be set to 0 since the PPC use VAR(L+7) and
VAR(L+1) of the GEPVE model in order to introduce the desired commands.
PAGE 14 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
3.2.4 Protections
The real inverter has the following protections:
Over voltage:
o FAST: it protects against large over voltage events with an instant trip.
o SLOW: it protects against small over voltage events retarding the trip a relatively
long time.
Under voltage: It consists in a limit for the voltage dip response time approaching to any
required voltage dip profile according to the number of arranged protections, this means,
the more protections, the more accurate will be the approximation to the profile.
Over frequency
o FAST: it protects against large over frequency events with an instant trip.
o SLOW: it protects against small over frequency events retarding the trip a
relatively long time.
Under frequency
o FAST: it protects against large under frequency events with an instant trip.
o SLOW: it protects against small under frequency events retarding the trip a
relatively long time.
All the protections are adjustable in the real inverter and can be set in the model by
using VTGDCAT (voltage) and FRQDCAT (frequency) psse protection models
(Dynamics data Other Models Miscellaneous).
A common aspect of all protections is the response time composition: the “Relay pickup
time” is the delay time the device retards the trip once the fault has been detected, while
the “Breaker time” is the time that the circuit breaker takes to open, so an “instant trip”
is consider with 0,0 seconds Relay pickup time and the standard Breaker time (0,1
seconds).
The Under Voltage protections, as it was mentioned previously, are set to define the
voltage dip profile so that, the more protections, the more accurate will be the
approximation to this profile.
Furthermore, for every protection, “model ICONS” must be filled accordingly to bus
numbers and machine ID used in the simulation performed. See an example below:
PAGE 15 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
PAGE 16 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
CON(J+7) CON(J+3)
INVERTER 0 CON(J+17)
QMX VAR(L+1)
CON(J+20) CON(J+16)
QMEAS [MVAr]
1/(1+sTQ) 1/Prate Inverter QCMD Calculation
VAR(L+7)
1-PREF ICON(I+4)
Δf [p.u.] + INVERTER VAR(L)
1/(1+sTF) Kf-p 1/(1+sTP) CON(J+2)
0
VAR(L+5)
PCMD [p.u.] INVERTER
CON(J+21) CON(J+15) -PREF + CON(J+22)
1
PCMD [p.u.]
VAR(CON(J))
PREF [p.u.]
CON(J+14) Inverter PCMD Calculation
Figure 6. PE_PPC Diagram Block
PAGE 17 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
PE_PPC
VARs # DESCRIPTION
L Inverter P command [p.u.] (DEBUG)
L+1 Inverter Q command [p.u.] (DEBUG)
L+2 Inverter Q command initialization [p.u.]
L+3 Measured Voltage at POI [p.u.]
L+4 Measured Voltage Angle at POI [Degrees]
L+5 Frequency Deviation at POI [p.u.]
L+6 Active Power at POI [MW] (flow1)
L+7 Reactive Power at POI [MVAr] (flow1)
L+8 Apparent Power at POI [MVA] (flow1)
PAGE 18 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
STATEs # DESCRIPTION
K Delay in POI voltage measurement
K+1 Voltage PI controller
K+2 Delay P command
K+3 Delay frequency measurement
K+4 Q PI controller
K+5 Delay in POI Q measurement
K+6 Delay Qmeas in Qdroop
[*] These parameters must be obtained for each plant and are the array locations of the
VAR(L+7) and VAR(L+1) in GEPVE model (see test-bench example).
[**] Parameters computed during initialization. No matter the value in the .dyr.
THE USER ONLY SHOULD SET THE DESIRED VALUES USING THE CONs.
DO NOT CHANGE THE VARs.
PAGE 19 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
5 MAIN PARAMETERS
Figure below shows an overview of the models within the .dyr file:
The main parameters that should be modified by the user are as follows:
CON(J): The user must set the inverter rated power [MVA] in CON(J) of the GEPVG
model.
PAGE 20 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
oIf ICON(M+4) is set to 0, the PPC frequency control will be disabled and the
user can set the desired PCMD in CON(J+2). Otherwise (ICON(M+4)=1), the
inverter P command will be interconnected with the frequency control.
o If ICON(M+5) is set to 0, the PPC POI voltage, Q and PF control will be disabled
and the user can set the desired QCMD in CON(J+3). Otherwise (ICON(M+5)=1),
the inverter Q command will be interconnected with the PPC POI voltage, Q or
PF control depending on the ICON(M+6) value.
o ICON(M+6) allow the user to choose the desired POI control:
ICON(M+6) = 0 POI voltage control
ICON(M+6) = 1 POI Q control
ICON(M+6) = 2 POI P.F control
CON(M+7), CON(M+8), CON(J+12), CON(J+13): The Kp_vc and Ki_vc could change
depending on the plant impedance.
CON(J+16): The user must set the inverter Prate (=CON(J) GEPVE).
CON(J) & CON(J+1): These are the most important CONs of the model and have
been used in order to interconnect the PPC with the GEPVE model.
These CONs must contain the global array locations of the GEPVE VAR(L+7) (CON(J))
and GEPVE VAR(L+1) (CON(J+1)). These values could change depending on the .dyr
used, and these can be obtained as follows:
Open PSSe Open .sld, .raw, .sav, etc… Open the desired .dyr
Dynamics List Model Storage Locations All models Go
The report (MLST) will be as follows (it will depend on the .dyr):
¡
In the example, the GEPVE model has 8 VARs (occupying positions between 6
and 13). Then, the VAR(L+1) global array location will be VAR(7) and the
VAR(L+7) global array location will be VAR(13).
Notice that if the .dyr file change (some models are included or deleted), the
global array locations of the GEPVE could change and this step should be
repeated.
PAGE 21 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
Warning
The following CONs are set during initialization (these values are dependents on
the load flow conditions). No matter the value within the .dyr file:
CON(J+2), CON(J+3), CON(J+4), CON(J+10), CON(J+11), CON(J+14)
PAGE 22 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
6 TEST BENCH
6.1 Test bench overview
This report includes several tests in order to show the successful response of the inverter
and PPC models.
The test bench (figure below) consists in one generator (bus 2) against the inverter (bus
1111). A typical 6% transformer has been included in order to simulate the real
behavior of the inverter in a real system.
Buses:
#2 Swing bus
#1110 Non-generator
PAGE 23 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
Branches:
Transformer:
Load:
The dynamic model of the generator is GENCLS with the following parameters:
All the results have been obtained with the attached files.
PAGE 24 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
PAGE 25 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
PAGE 26 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
PAGE 27 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
OVER-FREQUENCY
A change in the load has been applied in order to introduce an over-frequency deviation:
PAGE 28 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
Notice that, due to the over frequency event, the inverter reduces the output power
depending on the Kf-p value (CON(J+15)) as follows.
UNDER-FREQUENCY
PAGE 29 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
Figure 20. Inverter P[MW] & Q [MVAr] power output – under frequency
The inverter increases the active power injection until machine saturation.
PAGE 30 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
*The PPC frequency control has been disabled in order to test only the voltage control.
The following commands have been applied to CON(M+4) in order to test the voltage
regulation at POI:
PAGE 31 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
PAGE 32 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
PAGE 33 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
PAGE 34 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
PAGE 35 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
PAGE 36 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
Figure 33. Measured P [MW] & Q [MVAr] at POI - frequency + voltage control
PAGE 37 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
The change in Vref produces an over-frequency deviation, reducing the inverter active
power command.
PAGE 38 of 39
November, 2015
POWER ELECTRONICS Revision: 3.0
7 ATTACHED FILES
Test_bench.sld: It contains test-bench graph
Test_bench.sav: It contains the converted load flow case
Test_bench.dyr: It contains the dynamic load flow case
Dsusr.dll: It contains the library of the PE_PPC model (PSSE v33)
Pv_inverter_v33.dll: It contains the library of the GEPVG&GEPVE models.
PAGE 39 of 39
November, 2015