B-1 Appendix B: Reduction of Digital Logic

Principles of Computer Architecture

Miles Murdocca and Vincent Heuring

Appendix B: Reduction of Digital

Logic

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-2 Appendix B: Reduction of Digital Logic

Chapter Contents
B.1 Reduction of Combinational Logic and Sequential Logic
B.2 Reduction of Two-Level Expressions
B.3 State Reduction

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-3 Appendix B: Reduction of Digital Logic

Reduction (Simplification) of Boolean

Expressions
• It is usually possible to simplify the canonical SOP (or POS)
forms.
• A smaller Boolean equation generally translates to a lower gate
count in the target circuit.
• We cover three methods: algebraic reduction, Karnaugh map re-
duction, and tabular (Quine-McCluskey) reduction.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-4 Appendix B: Reduction of Digital Logic

Reduced Majority Function Circuit

• Compared with the AND-OR circuit for the unreduced majority
function, the inverter for C has been eliminated, one AND gate has
been eliminated, and one AND gate has only two inputs instead of
three inputs. Can the function by reduced further? How do we go
about it? A B C

Unreduced
A B C
Reduced

ABC

ABC
F
F

AB C

ABC

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-5 Appendix B: Reduction of Digital Logic

The Algebraic Method

• Consider the majority function, F. We apply the algebraic method
to reduce F to its minimal two-level form:

F = ABC + ABC + ABC + ABC

F = ABC + ABC + AB(C + C ) Distributive Property
F = ABC + ABC + AB(1) Complement Property
F = ABC + ABC + AB Identity Property
F = ABC + ABC + AB + ABC Idempotence
F = ABC + AC( B + B) + AB Identity Property
F = ABC + AC + AB Complement and Identity
F = ABC + AC + AB + ABC Idempotence
F = BC( A + A) + AC + AB Distributive
F = BC + AC + AB Complement and Identity

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-6 Appendix B: Reduction of Digital Logic

The Algebraic Method

• This majority circuit is functionally equivalent to the previous ma-
jority circuit, but this one is in its minimal two-level form:

A B C

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-7 Appendix B: Reduction of Digital Logic

Karnaugh Maps: Venn Diagram Rep-

resentation of Majority Function
• Each distinct region in the “Universe” represents a minterm.
• This diagram can be transformed into a Karnaugh Map.

ABC A

ABC’ AB’C’ AB’C

A’BC’ A’B’C

B C
A’BC A’B’C’

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-8 Appendix B: Reduction of Digital Logic

K-Map for Majority Function

• Place a “1” in each cell that corresponds to that minterm.
• Cells on the outer edge of the map “wrap around”

Minterm A B C F
AB
00 01 11 10
Index C 1
0 0 0 0 0
1 0 0 1 0
2 0 1 0 0 0 00 1
3 0 1 1 1 0-side 1-side
4 1 0 0 0
5 1 0 1 1
6 1 1 0 1 1A balance tips to the left1or 1 1
right depending on whether
7 1 1 1 1
there are more 0’s or 1’s.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-9 Appendix B: Reduction of Digital Logic

Adjacency Groupings for Majority

Function
AB
00 01 11 10
C
0 1

1 1 1 1

• F = BC + AC + AB

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-10 Appendix B: Reduction of Digital Logic

Minimized AND-OR Majority Circuit

A B C

• F = BC + AC + AB
• The K-map approach yields the same minimal two-level form as
the algebraic approach.
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-11 Appendix B: Reduction of Digital Logic

K-Map Groupings
• Minimal grouping is on the left, non-minimal (but logically equiva-
lent) grouping is on the right.
• To obtain minimal grouping, create smallest groups first.

AB AB
00 01 11 10 00 01 11 10
CD CD
1 2
00 1 00 1
1
4 5
01 1 1 1 01 1 1 1
2
11 1 1 1 11 1 1 1
3

10 1 10 1
3 4

F = A BC + ACD + F = BD + A BC + ACD +
ABC + AC D ABC + AC D
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-12 Appendix B: Reduction of Digital Logic

K-Map Corners are Logically Adjacent

AB
00 01 11 10
CD
00 1 1 1

01 1

11 1 1

10 1 1 1

F=BCD + B D + AB

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-13 Appendix B: Reduction of Digital Logic

K-Maps and Don’t Cares

• There can be more than one minimal grouping, as a result of
don’t cares.

AB AB
00 01 11 10 00 01 11 10
CD CD
00 1 d 00 1 d

01 1 1 01 1 1

11 1 1 11 1 1

10 d 10 d

F= BC D + BD F= A B D + B D

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-14 Appendix B: Reduction of Digital Logic

Five-Variable K-Map
• Visualize two 4-variable K-maps stacked one on top of the other;
groupings are made in three dimensional cubes.

AB AB
00 01 11 10 00 01 11 10
CDE CDE
000 1 100 1

001 1 1 101 1 1

011 1 1 111 1 1

010 1 1 110

F = A C D E + A B DE + B E

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-15 Appendix B: Reduction of Digital Logic

Six-Variable K-Map
• Visualize four 4-variable K-maps stacked one on top of the other;
groupings are made in three dimensional cubes.
ABC ABC
000 001 011 010 000 001 011 010
DEF DEF
000 1 100 1

001 101

011 1 1 111

010 1 1 110

ABC ABC
100 101 111 110 100 101 111 110
DEF DEF
000 1 100 1

001 101

011 111

010 110

G = B C EF + A B DE
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-16 Appendix B: Reduction of Digital Logic

3-Level Majority Circuit

• K-Kap Reduction results in a reduced two-level circuit (that is,
AND followed by OR. Inverters are not included in the two-level
count). Algebraic reduction can result in multi-level circuits with
even fewer logic gates and fewer inputs to the logic gates.

A B C

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-17 Appendix B: Reduction of Digital Logic

Map-Entered Variables
• An example of a K-map with a map-entered variable D.

AB
00 01 11 10
C
0 D

1 1 1

F = BC + ABCD

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-18 Appendix B: Reduction of Digital Logic

Two Map-Entered Variables

• A K-map with two map-entered variables D and E.
• F = BC + ACD + BE + ABCE

AB
00 01 11 10
C
0 D d E E

1 1 1

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-19 Appendix B: Reduction of Digital Logic

Truth Table with Don’t Cares

A B C D F
• A truth table repre-
sentation of a single 0 0 0 0 d
function with don’t 0 0 0 1 1
0 0 1 0 0
cares.
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 d
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 d

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-20 Appendix B: Reduction of Digital Logic

Tabular (Quine-McCluskey) Reduction

• Tabular reduction be- Initial setup After first After second
reduction reduction
gins by grouping
minterms for which F A B C D A B C D A B C D
is nonzero according 0 0 0 0 √ 0 0 0 _ * 0 _ _ 1 *
to the number of 1’s in 0 0 0 1 √ 0 0 _ 1 √ _ _ 1 1 *
each minterm. Don’t 0 0 1 1 √ 0 _ 0 1 √ _ 1 _ 1 *
0 1 0 1 √ 0 _ 1 1 √
cares are considered 0 1 1 0 √ _ 0 1 1 √ (c)
to be nonzero. 1 0 1 0 √ 0 1 _ 1 √
0 1 1 1 √ _ 1 0 1 √
• The next step forms a 1 0 1 1 √ 0 1 1 _ *
consensus (the logical 1 1 0 1 √ 1 0 1 _ *
form of a cross prod- 1 1 1 1 √ _ 1 1 1 √
1 _ 1 1 √
uct) between each pair (a) 1 1 _ 1 √
of adjacent groups for
(b)
all terms that differ in
only one variable.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-21 Appendix B: Reduction of Digital Logic

Table of Choice
• The prime implicants form a set that completely covers the func-
tion, although not necessarily minimally.
• A table of choice is used to obtain a minimal cover set.

Prime Minterms
Implicants
0001 0011 0101 0110 0111 1010 1101
0 00 _ √

* 0 11 _ √ √

* 1 01 _ √

0 __ 1 √ √ √ √

_ _1 1 √ √

* _ 1_ 1 √ √ √

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-22 Appendix B: Reduction of Digital Logic

Reduced Table of Choice

• In a reduced table of choice, the essential prime implicants and
the minterms they cover are removed, producing the eligible set.
• F = ABC + ABC + BD + AD

Set 1 Set 2
Eligible Minterms
Set 000_ 0__1
0001 0011 __11
X 0 0 0_ √

Y 0 _ _1 √ √

Z _ _ 11 √

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-23 Appendix B: Reduction of Digital Logic

Multiple Output Truth Table

• The power of tabular reduction comes into play for multiple func-
tions, in which minterms can be shared among the functions.

Minterm A B C F0 F1 F2

m0 0 0 0 1 0 0
m1 0 0 1 0 1 0
m2 0 1 0 0 0 1
m3 0 1 1 1 1 1
m4 1 0 0 0 1 0
m5 1 0 1 0 0 0
m6 1 1 0 0 1 1
m7 1 1 1 1 1 1

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-24 Appendix B: Reduction of Digital Logic

Multiple Output Table of Choice

F0(A,B,C) = ABC + BC
F1(A,B,C) = AC + AC + BC
F2(A,B,C) = B
Min- F0(A,B,C) F1(A,B,C) F2(A,B,C)
terms
Prime
Implicants m0 m3 m 7 m 1 m 3 m4 m 6 m 7 m 2 m3 m6 m7

F0 * 0 00 √

F1 * 0 _1 √ √

F1 * 1 _0 √ √

F2 * _ 1_ √ √ √ √

F1,2 1 1_ √ √ √ √

F0,1,2 * _ 1 1 √ √ √ √ √ √

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-25 Appendix B: Reduction of Digital Logic

Speed and Performance

• The speed of a digital system is governed by:
• the propagation delay through the logic gates and
• the propagation delay across interconnections.
• We will look at characterizing the delay for a logic gate, and a
method of reducing circuit depth using function decomposition.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-26 Appendix B: Reduction of Digital Logic

Propagation Delay for a NOT Gate

• (From Hamacher et. al. 1990)

Transition Time
+5V (Fall Time)
10%
A NOT gate 50%
input changes (2.5V)
from 1 to 0
90%
0V
Propagation Delay

(Latency)
Transition Time
+5V (Rise Time)
90%
The NOT gate
output changes 50%
from 0 to 1 10% (2.5V)

0V
Time

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-27 Appendix B: Reduction of Digital Logic

MUX Decomposition
1 00
1 0000
0 01 BC+BC
0 0001 0 10
0 0010 1 11
1 0011
0 0100
1 0101
1 0110 00
0 0111
B C 01
0 1000 F
0 F
1 1001 10
0 1010
11
0 1011
0 1100 0 00
0 1101 1 01
0 1110
1 1111 1 10 B C+ B C A D
0 11

A B C D
B C

F( ABCD) = ABC D + ABCD + ABC D + ABCD + ABC D + ABCD

= ( BC + BC ) AD + ( BC + BC ) AD + ( BC + BC )
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-28 Appendix B: Reduction of Digital Logic

OR-Gate Decomposition
• Fanin affects circuit depth.
A BCD AB CD AB C D

A+B+C+D
Initial high fan-in gate

(A + B) + (C + D)
Balanced tree

Associative law of Boolean algebra:

A + B + C + D = (A + B) + (C + D) (( A + B) + C) + D
Degenerate tree

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-29 Appendix B: Reduction of Digital Logic

State Reduction
• Description of state machine M0 to be reduced.

Input X
Present state 0 1

A C/0 E/1
B D/0 E/1
C C/1 B/0
D C/1 A/0
E A/0 C/1

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-30 Appendix B: Reduction of Digital Logic

Distinguishing Tree
• A next state tree for M0.
(ABCDE)
0 1

(CDA)(CC) Next states (EEC)(BA)

(ABE)(CD) Distinguished states (ABE)(CD)
0 1 0 1

(CC)(C)(CC) (BA)(E)(BB) (AA)(C)(DC) (CC)(B)(EE)

(AB)(E)(CD)* (AB)(E)(CD) (AB)(E)(CD) (AB)(E)(CD)*
0 1 0 1

(DC)(A)(DD) (EE)(C)(EE) (CC)(C)(CC) (EE)(B)(AB)

(AB)(E)(CD) (AB)(E)(CD)*
0 1

(CC)(C)(CC) (AB)(E)(AA)
(AB)(E)(CD)
0 1

(CD)(A)(CC) (EE)(C)(EE)

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-31 Appendix B: Reduction of Digital Logic

Reduced State Table

• A reduced state table for machine M1.

Input X
Current state 0 1

AB: A' B'/0 C'/1

CD: B' B'/1 A'/0
E: C' A'/0 B'/1

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-32 Appendix B: Reduction of Digital Logic

The State Assignment Problem

• Two state assignments for machine M2.

Input X Input X Input X

P.S. 0 1 S0S1 0 1 S 0S 1 0 1
A B/1 A/1 A: 00 01/1 00/1 A: 00 01/1 00/1
B C/0 D/1 B: 01 10/0 11/1 B: 01 11/0 10/1
C C/0 D/0 C: 10 10/0 11/0 C: 11 11/0 10/0
D B/1 A/0 D: 11 01/1 00/0 D: 10 01/1 00/0

Machine M2 State assignment SA0 State assignment SA1

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-33 Appendix B: Reduction of Digital Logic

State Assignment SA0

• Boolean equations for machine M2 using state assignment SA0.
X X X
0 1 0 1 0 1
S0S1 S0S1 S0S1
00 00 1 00 1 1

01 1 1 01 1 01 1

11 11 1 11 1

10 1 1 10 1 10

S0 = S0S1 + S0S1 S1 = S0S1X + S0S1X Z = S0S1 + S0X

+ S0S1X + S0S1X + S0S1X

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-34 Appendix B: Reduction of Digital Logic

State Assignment SA1

• Boolean equations for machine M2 using state assignment SA1.

X X X
0 1 0 1 0 1
S0S1 S0S1 S0S1
00 00 1 00 1 1

01 1 1 01 1 01 1

11 1 1 11 1 11

10 10 1 10 1

S0 = S 1 S1 = X Z = S1 X + S0 X

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-35 Appendix B: Reduction of Digital Logic

Sequence Detector State Transition

Diagram 0/0
0/0
D

B 1/0
0/0 0/0
E
1/0

A 1/1 0/0

0/0
F 1/1
1/0
C 0/1

Input: 011011100
G
Output: 0 0 1 1 1 1 0 1 0 1/0
Time: 0 1 2 3 4 5 6 7 8 1/0
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-36 Appendix B: Reduction of Digital Logic

Sequence Detector State Table

Input X
Present state 0 1

A B/0 C/0
B D/0 E/0
C F/0 G/0
D D/0 E/0
E F/0 G/1
F D/0 E/1
G F/1 G/0

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-37 Appendix B: Reduction of Digital Logic

Sequence Detector Reduced State

Table

Input X
Present state 0 1

A: A' B'/0 C'/0

BD: B' B'/0 D'/0
C: C' E'/0 F'/0
E: D' E'/0 F'/1
F: E' B'/0 D'/1
G: F' E'/1 F'/0

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-38 Appendix B: Reduction of Digital Logic

Sequence Detector State Assignment

Input X
Present state 0 1
S2S1S0 S2S1S0Z S2S1S0Z
A': 000 001/0 010/0
B': 001 001/0 011/0
C': 010 100/0 101/0
D': 011 100/0 101/1
E': 100 001/0 011/1
F': 101 100/1 101/0

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-39 Appendix B: Reduction of Digital Logic

Excitation Tables
• In addition to the D flip-flop, the S-R, J-K, and T flip-flops are used
as delay elements in finite state machines.
• A Master-Slave J-K flip-flop is shown below.

J
Q
J Q
CLK
K Q
Q
K

Symbol
Circuit

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-40 Appendix B: Reduction of Digital Logic

Sequence Detector K-Maps

S2S1 S2S1
00 01 11 10 00 01 11 10
S0X S0X
• K-map re- 00 1 d 1 00 d
duction of 01 1 d 1 01 1 d 1
next state
11 1 1 d 1 11 1 d
and output
functions for 10 1 d 10 d
sequence S 0 = S 2 S1 X + S 0 X S1 = S2S1X + S2S0X
detector. + S2S0 + S1X
S2S1 S2S1
00 01 11 10 00 01 11 10
S0X S0X
00 1 d 00 d

01 1 d 01 d 1

11 1 d 1 11 1 d

10 1 d 1 10 d 1

S2 = S2S0 + S1 Z = S2S0X + S1S0X + S2S0X

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-41 Appendix B: Reduction of Digital Logic

Clocked T Flip-Flop
• Logic diagram and symbol for a T flip-flop.

1 J Q Q
T T
K Q Q

Circuit Symbol

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-42 Appendix B: Reduction of Digital Logic
X

Sequence
Detector CLK
D Q
S0
Q

Circuit
D Q
S1
Q

D Q
S2
Q

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-43 Appendix B: Reduction of Digital Logic

Excitation Tables
• Each table
Qt Qt+1 S R Qt Qt+1 D
shows the set-
tings that must S-R 0 0 0 0 D 0 0 0
be applied at the flip-flop 0 1 1 0 flip-flop 0 1 1
inputs at time t 1 0 0 1 1 0 0
in order to 1 1 0 0 1 1 1
change the out-
puts at time t+1. Qt Qt+1 J K Qt Qt+1 T

J-K 0 0 0 d T 0 0 0
flip-flop 0 1 1 d flip-flop 0 1 1
1 0 d 1 1 0 1
1 1 d 0 1 1 0

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-44 Appendix B: Reduction of Digital Logic

Serial Adder
Time (t) 4 3 2 1 0 4 3 2 1 0 Time (t) No carry Carry state
state
01100 X Z 11010
Serial xi yi 01/1 11/0 01/0
01110 Y
Adder
Cin Cout
00/0 A B 10/0
zi
10/1 00/1 11/1

• State transi- Input XY

tion diagram, Present state 00 01 10 11

state table, A A/0 A/1 A/1 B/0

B A/1 B/0 B/0 B/1
and state as-
signment for Next state Output
a serial adder.
Input XY
Present
state (St) 00 01 10 11
A:0 0/0 0/1 0/1 1/0
B:1 0/1 1/0 1/0 1/1

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-45 Appendix B: Reduction of Digital Logic

Serial Adder Next-State Functions

• Truth table showing next-state functions for a serial adder for D,
S-R, T, and J-K flip-flops. Shaded functions are used in the ex-
ample.
Present
State (Set) (Reset)
X Y St D S R T J K Z

0 0 0 0 0 0 0 0 d 0
0 0 1 0 0 1 1 d 1 1
0 1 0 0 0 0 0 0 d 1
0 1 1 1 0 0 0 d 0 0
1 0 0 0 0 0 0 0 d 1
1 0 1 1 0 0 0 d 0 0
1 1 0 1 1 0 1 1 d 0
1 1 1 1 0 0 0 d 0 1

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-46 Appendix B: Reduction of Digital Logic

J-K Flip-Flop Serial Adder Circuit

X
J Q
Y
CLK S
K Q
X
Y

X
Y

Y
Z

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-47 Appendix B: Reduction of Digital Logic

D Flip-Flop Serial Adder Circuit

X
Y

X DQ
S
Q
Y
CLK

X
Y

Y
Z

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-48 Appendix B: Reduction of Digital Logic

Majority Finite State Machine

1/0
0/0 D
0/0 00_
B
1/0 01_
0/0 0__
___ E
Input History
0/0 1/1
A
0/0 1/1

1/0 1__ F
0/0 10_
Input: 0 1 1 1 0 0 1 0 1 C
1/0 11_
Output: 0 0 1 0 0 0 0 0 1
0/1 G
Time: 0 1 2 3 4 5 6 7 8 1/1

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-49 Appendix B: Reduction of Digital Logic

Majority FSM State Table

• (a) State table for majority FSM; (b) partitioning; (c) reduced state
table.

Input X Input X
P.S. 0 1 P.S. 0 1
A B/0 C/0 A: A' B'/0 C'/0
B D/0 E/0 P0 = (ABCDEFG) B: B' D'/0 E'/0
C F/0 G/0 P1 = (ABCD)(EF)(G) C: C' E'/0 F'/0
D A/0 A/0 D: D' A'/0 A'/0
P2 = (AD)(B)(C)(EF)(G)
E A/0 A/1 EF: E' A'/0 A'/1
F A/0 A/1 P3 = (A)(B)(C)(D)(EF)(G)
G: F' A'/1 A'/
G A/1 A/1 P4 = (A)(B)(C)(D)(EF)(G) √ 1
(a) (b) (c)

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-50 Appendix B: Reduction of Digital Logic

Majority FSM State Assignment

• (a) State assignment for reduced majority FSM using D flip-flops;
and (b) using T flip-flops.

Input X Input X
P.S. 0 1 P.S. 0 1
S2S1S0 S2S1S0Z S2S1S0Z S2S1S0 T2T1T0Z T2T1T0Z
A': 000 001/0 010/0 A': 000 001/0 010/0
B': 001 011/0 100/0 B': 001 000/0 010/0
C': 010 100/0 101/0 C': 010 110/0 111/0
D': 011 000/0 000/0 D': 011 011/0 011/0
E': 100 000/0 000/1 E': 100 100/0 100/1
F': 101 000/1 000/1 F': 101 101/1 101/1

(a) (b)

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 B-51 Appendix B: Reduction of Digital Logic

Majority FSM Circuit

0 000 x 000 x 000 0 000

0 001 x 001 x0 001 0 001
1 010 1 010 x 010 0 010
0 011 1 011 1 011 0 011
D Q D Q D Q Z
0 100 T 0 100 T 0 100 T x 100
0 101 2
Q 0 101 1
Q 1 101 0
Q 1 101
0 110 0 110 0 110 0 110
0 111 0 111 0 111 0 111

CLK

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring