QUESTION BANK

SRI INDU COLLEGE OF ENGG & TECHOLOGY

Prepared
QUESTION BANK on Rev1:
(Regulation :R22) Page: 1 of 5
Department of COMPUTER SCIENCE AND ENGINEERING
Sub. Code & Title (R22ECE2112) DIGITAL ELECTRONICS
Academic Year: 2023-24 Year/Sem./Section II B.TECH I-SEM
Faculty Name & Designation JYOTHI DAIDA , Asst. Professor

UNIT-I: BOOLEAN ALGEBRA AND LOGIC GATES:

BT Course
Multiple Choice Questions Level Outcom
e
In boolean algebra, the OR operation is performed by which
properties?
a) associative properties
#1C-1 b) commutative properties II CO1
c) distributive properties
d) all of the mentioned

The expression for Absorption law is given by

a) A + AB = A
#1C-2 b) A + AB = B I CO1
c) AB + AA’ = A
d) A + B = B + A
According to boolean law: A + 1 = ?
a) 1
#1C-3 b) A III CO1
c) 0
d) A’
A(A + B) = ?
a) AB
#1C-4 b) 1 I CO1
c) (1 + AB)
d) A
DeMorgan’s theorem states that
a) (AB)’ = A’ + B’
#1C-5 b) (A + B)’ = A’ * B III CO1
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B
Complement of the expression A’B + CD’ is
a) (A’ + B)(C’ + D)
#1C-6 b) (A + B’)(C’ + D) II CO1
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)
Simplify Y = AB’ + (A’ + B)C.
#1C-7 I CO1
a) AB’ + C
 b) AB + AC
c) A’B + AC’
d) AB + A
The octal number (651.124)8 is equivalent to
a) (1A9.2A)16
#1C-8 b) (1B0.10)16 V CO1
c) (1A8.A3)16
d) (1B0.B0)16
What is the addition of the binary numbers 11011011010 and 010100101? a)
0111001000
#1C-9 b) 1100110110 I CO1
c) 11101111111
d) 10011010011
Perform binary subtraction: 101111 – 010101 = ? a)
100100
#1C-10 b) 010101 IV CO1
c) 011010
d) 011001
100101 × 0110 = ?
a) 1011001111
#1C-11 b) 0100110011 V CO1
c) 101111110
d) 0110100101
The logical sum of two or more logical product terms is called
a) SOP
#1C-12 b) POS IV CO1
c) OR operation
d) NAND operation
A code converter is a logic circuit that CO1
a) Inverts the given input
#1C-13 b) Converts into decimal number VI
c) Converts data of one type into another type
d) Converts to octal
The primary use for Gray code is CO1
a) Coded representation of a shaft’s mechanical position
b) Turning on/off software switches
#1C-14 c) To represent the correct ASCII code to indicate the angular position of a shaft I
on rotating machinery
d) To convert the angular position of a shaft on rotating machinery into
hexadecimal code
Code is a symbolic representation of
a) Discrete information
#1C-15 b) Continuous information IV CO1
c) Decimal information into binary
d) Binary information into decimal
#Filling The Blank Questions
#1F-1 The expression Y=AB+BC+AC shows the operation I CO1
#1F-2 2’s complement of 11001011 is VI CO1
#1F-3 1’s complement of 1011101 is II CO1
On subtracting (01010)2 from (11110)2 using 1’s complement, we get CO1
#1F-4 III
#1F -5 On addition of 28 and 18 using 2’s complement, we get V CO1
#1F- 6 How many truth table entries are necessary for a four-input circuit------- VI CO1
The canonical sum of product form of the function y(A,B) = A + B is CO1
#1F -7 I
#1F -8 A variable on its own or in its complemented form is known as a II CO1
#1F-9 Canonical form is a unique way of representing I CO1
#1F-10 There are Minterms for 3 variables (a, b, c) IV CO1
#1F-11 One way to convert BCD to binary using the hardware approach is CO1
I
#1F-12 Reflected binary code is also known as II CO1
#1F-13 Earlier, reflected binary codes were applied to I CO1
#1F-14 The binary representation of BCD number 00101001 (decimal 29) is CO1
I
#1F-15 The expression Y=AB+BC+AC shows the operation. III CO1
#Match The Following Questions
Match The Following Questions

A. 10101010 1. 128

#1M-1 B. 11110000 2. 240 V CO1

C. 10001000 3. 170

D. 10000000 4. 136
Match The Following Questions
A) ABC+ABC+AB’C 1. A’+BC
B) A’BC’+ABC+BC 2. A(B+C)
#1M-2 II CO1
C) A’BC+AB’C+ABC’+ABC 3. BC’
D) A’B’+A’B+ABC 4.
AB+BC+AC
Match The Following Questions
A) COUNTING 1. ROM
B) DECODING 2. MULTIPLEXER CO1
#1M-3 IV
C) DATA SELECTING 3. DEMULTIPLEXER
D) CODE CONVERSION 4. REGISTER

#1M-4 Match The Following Questions

A) 1.AND GATE VI CO1

B) 2. OR GATE
 3. NOT GATE
4. NOR GATE
C)

D)

#1M-5 Match The Following Questions

A) 50 1.110010

B) 60 2. 111100 I CO1
C) 35 3. 100011
D) 65 4. 1000001

#5 MARKS QUESTIONS
What are the rules for Excess-3 addition? Add two decimal numbers 123 and 658
#1D-1 I COI
in Excess-3 code?
A) simplify the logic function
i) F (A, B, C, D) = AB+AC+C+AD+ABC+ABC
#1D-2 IV CO1
ii) F (A, B, C, D) = AC+ABC+BC

Minimize the following Boolean expressions. VI CO1

i. B'C'D+(B+C+D)'+B'C'D'E
#1D-3
ii. AB+(AC)'+AB'C(AB+C)
iii. A'B'C'+A'BC'+AB'C'+ABC'iv.A+B+A'B'C
Write the minterms and maxterms for the following functions
#1D-4 I CO1
i) F=∑m(1,4,6,7,9)
ii) F=πm(3,5,7,11,14)
#1D-5 Explain the postulates of Boolean algebra II CO1
#1D-6 Draw the logic gate diagram for the expression [( A+ B).C ] D by using NAND V CO1
gate ?
#1D-7 State and prove Demorgan’s theorems I CO1
Justify with your answer Why are NAND and NOR gates known asuniversal
#1D-8 gates V CO1

Translate the following A616 = ( )10

i. 12668 = ( )10
#1D-9 II CO1
ii. 101000112 = ( )10
iii. 37210 =( )16
Design EX-OR gate and EX-NOR using NAND and NOR gates
#1D-10 VI CO1
#1D-11 State and prove consensus theorem? I CO1
#1D-12 Explain Boolean algebra laws and rules? II CO1
#1D-13 State Duality Theorem? I CO1
#1D-14 Change the given SOP into POS form f(A,B,C,D)=∑m( 0,2,4,6, 8,10,12,14) III CO1
#1D-15 Draw the logic diagram of NOR- NOR implementation of Y = (A'+C')(B'+C')(A'+B')'? I CO1
#1D-16 Design XOR gate by using NAND Y = A'B+B'A II CO1
#1D-17 Draw the logic diagram of Y = AC+ABC+A'BC+AB+D IV CO1

#UNIT-II: GATE-LEVEL MINIMIZATION:

BT Course
#Multiple Choice Questions Level Outcome
The minterms in a karnaugh map are marked with a

A) y
#2C-1 B) x I CO2
C) 0
D) 1

A Karnaugh map (K-map) is a theoretical form of representing

#2C-2. a)Circuit diagram b)Block diagram I CO2

c)Logic diagram d)Venn diagram

A Karnaugh map (K-map) is a theoretical form of representing

#2C-3. a)Circuit diagram b)Block diagram I CO2

c)Logic diagram d)Venn diagram

Which of the following is NOT considered for forming groups in K-map?

#2C-4. I CO2
a) Rolling b) Diagonal c) Vertical d) Horizontal

The one input NOR and NAND gate behaves like a

#2C-5. A) converter III CO2

B) inverter
C) reflector
D) differentiator
 The NOR function is the dual of

A) AND function
#2C-6. B) OR function I CO2
C) XOR function
D) NAND function

What value is to be considered for a “don’t care condition”?

a) 0
#2C-7. b) 1 I CO2
c) Either 0 or 1
d) Any number except 0 and 1
Minimum number of 2-input NAND gates required to implement the function
F= A+AB’+AB’C Is Equal To
A) Zero
#2C-8. B) 1 IV CO2
C) 4
D) 7

The Karnaugh map is used to

a) minimize the number of flip-flop in a digital circuit
b) minimize the number of gates only a digital circuit CO2
#2C-9. I
c) minimize the number of gates and fan-inof a digital circuit
d) design gates

Which of the following is equivalent to AND-OR

realization? a)NAND-NOR realization
#2C-10. b) NOR-NOR realization IV CO2
c) NOR-NAND realization
d)NAND-NAND realization
A three -input NAND gate is to be used as an inverter which one of the
following measures will achieve better result
a) The two input not used are kept open
#2C-11 III CO2
b) The two input not are connected to ground (o level)
c) The two inputs not used are connected to logic (1 level)
d) None of the above
Which of the following is equivalent to NAND-NAND
realization? a)AND-OR realization
#2C-12 b) NOR-NOR realization I CO2
c) NOR-NAND realization
d)NAND-NAND realization
#2C-13 Which of the following is equivalent to NAND-NOR realization?
a) inverted-input OR gate, inverted-input AND gate
b) AND-OR realization CO2
VI
c) NOR-NOR realization
d) NAND-NAND
#2C-14 How many cells have 5 variable k-map
A) 16 Cells
B) 8 Cells III CO2
C) 32 Cells
D) 4 Cells
#2C-15 How many cells have 4 variable k-map
E) 16 Cells
F) 8 Cells III CO2
G) 32 Cells
H) 4 Cells
#Filling The Blank Questions
#2F-1 The Karnaugh map is used to II CO2
The minterms in a karnaugh map are marked with a---------------
#2F-2 III CO2

What value is to be considered for a “don’t care condition-------------------

#2F-3 I CO2

Which of the following is equivalent to AND-OR realization

#2F-4 I CO2

#2F-5 The NOR Function is the dual of --------------------------------- VI CO2

#2F-6 How many cells have 5 variable k-map V CO2
#2F-7 How many cells have 4 variable k-map_------------------------ IV CO2
#2F-8 How many types of Degenerative form-------------------------------- II CO2
Which of the following is equivalent to NAND-NOR realization---------------
#2F-9 II CO2

#2F-10 What is the output of Ex-or gate--------------------------- II CO2

#2F-11 The product of sums form is a method (or form) of simplifying -------------- CO2
#2F-12 Hence, the function can be written in product-of-sums form as-------------- IV CO2
#2F-13 exclusive or equivalent gate is equal---------------------------------gate V CO2
#2F-14 The map method is also known as the-------------------------map I CO2
#2F-15 What is meant by pair------------------------------------------ I CO2
#Match The Following Questions
Match The Following Questions
a) exclusive or gate 1. A’+B’
#2M-1 b) Nand gate 2. A’B’+AB I CO2
c) Nor gate 3. AB’+A’B
d) Exclusive nor gate 4. A’B’
Match The Following Questions
a) 2-variable map 1.32 cells
#2M-2 b) 3-variable map 2.16 cells II CO2
c) 4-variable map 3.8 cells
d) 5-variable map 4.4 cells
 Match The Following Questions
a) AND-OR realization 1. AND-OR
b) NAND-NOR realization 2. NANA-NAD
#2M-3 c) NOR-NAND realization 3. OR-AND III CO2
d) NAND-NAND realization 4. inverted-input OR gate, inverted-input AND
gate

#2M-4 Match The Following Questions CO2

a) EXLUSIVE -OR 1.A’B’
b) NAND 2.A’+B’ III
c) NOR 3.A’B+AB’
d) DON’T CARE 4. X
#2M-5 Match The Following Questions CO2
a) NAND 1.32 CELLS
b) 5-VARIABLE 2.16 CELLS III
c) 4-VARIABLE 3.A’B+AB’
d) EXCLUSIVE -OR 4.A’B’

#5 MARKS QUESTIONS
#2D-1. What is don’t care condition? 1 CO2
#2D-2 Draw the Boolean expression for K-map f (A, B, C) =∑ (0, 2, 5) ? VI CO2
#2D-3 What is meant by pair and quads? 1 CO2
#2D-4 Reduce the expression by using K-map Y = ∑M (1,5,6,7,11,12,13,15) ? I CO2
#2D-5 Draw a logic diagram using only two input NAND gate to implement the following CO2
VI
expression ( AB + A'B')( CD' + C'D )
#2D-6 What is Karnaugh map? 4-variable k- map? I CO2
#2D-7 Reduce the SOP expression by using 5 variable K-map F(A,B,C,D) =∑M II CO2
(0,2,4,6,9,11,13,15,17,21,25,27,29,31) ?
#2D-8 Discuses about the product of sum?Simplify the expression Y = (A'+B'+C+D) II CO2
(A'+B'+C'+D)(A'+B'+C'+D')(A'+B+C+D)(A+B'+C'+D)
#2D-9 Find the reduce sop form the given expression F(A,B,C,D) = II CO2
∑M(5,6,7,12,13)+∑d(4.9.14,15) ?
#2D-10 Discuses about the OR-OR Implementation? II CO2
#2D-11 Discuses about the NAND-NOR Implementation? II CO2
#2D-12 What is meant by two level implementation? Types of two level implementation? I CO2
#2D-13 Simplify the function using tabular method (o)r QUINE- MCCLUSKEY method I CO2
f(A,B,C,D) = ∑(0,2,3,6,7,8,10,12,13)?
#2D-14 Explain about the f( A,B,C,D) = ΠM (0,2,3,8,9,12,13,15) ? II CO2
#2D-15 Simplify the function using tabular method (o)r QUINE- MCCLUSKEY method Y II CO2
=A'BC'D'+A'BC'D+ABC'D'+ ABC'D+ AB'C'D+A'B'CD'?

#UNIT-III: COMBINATIONAL LOGIC:

BT Course
#Multiple Choice Questions Level Outcom
e
 Code conversion circuits mostly uses

A) AND-OR gates
#3C-1 B) AND gates I CO3
C) OR gates
D) XOR gates

Full Adder combinational circuits has 3 inputs and

A) 2 outputs
#3C-2 B) 1 output I CO3
C) 3 outputs
D)None

Designing combinational circuit involves

A) 4 steps
#3C-3 B) 5 steps VI CO3
C) 6 steps
D) 8 steps

Half adder circuits requires two binary

A) Inputs
#3C-4 B) Outputs I CO3
C) Digits
D) Both a and b

Circuits that employ memory elements in addition to gates is called

A) combinational circuit
#3C-5 B) sequential circuit II CO3
C) combinational sequence
D) series

When both inputs are 1, the output of XOR is

A) 1
#3C-6 B) 0 II CO3
C) x
D) 10

Half subtractor is used to perform subtraction of

A) 2 bits
#3C-7 B) 3 bits I CO3
C) 4 bits
D) 5 bits

Dual of the NAND function is

A) AND function CO3

#3C-8 I
B) OR function
C) NOR function
D) NAND function
 2 to 4 line decoder will have

A) 2enables
#3C-9 B) 3enables I CO3
C) 4enables
D) 8enables

All the comparisons made by comparator is done using

A) 1circuit
#3C-10 B) 2circuits III CO3
C) 3circuits
D) 4circuits

If two numbers are not equal then the binary variable will be

A) 0
#3C-11 B) 1 I CO3
C) a
D) b

One that is not the outcome of magnitude comparator is

A) a>b
#3C-12 B) a-b I CO3
C) a<b
D) a=b

#3C-13 Which of the following logic expressions represents the logic diagram shown? CO3

III

a) X=AB’+A’
B
b) X=(AB)’+A
B
c) X=(AB)’+A’
B’
d) X=A’B’+A
B
#3C-14 The device sh own here is most likely a CO3

a) Comparator
b) Multiplexer
 c) Inverter
d) Demulti plexer
#3C-15 What type of log ic circuit is represented by the figure shown below? CO3

VI

a) XOR
b) XNOR
c) AND
d) XAND
#Filling The Blank Questions
#3F-1 An eight-line multiplexer must have as inputs . I CO3
The device that generates a coded output from a single active numeric input line
#3F-2 II CO3
is
#3F-3 In HDL, the operation of the DEMUX is exactly described using a . I CO3
#3F-4 How many outputs are on a BCD decoder--------------------------- III CO3
#3F-5 What is the function of an enable input on a multiplexer chip-------------------- I CO3
#3F-6 How many inputs will a decimal-to-BCD encoder have--------------------------- VI CO3
The largest truth table that can be implemented directly with an 8-line-to-1-line
#3F-7 I CO3
MUX has .
#3F-8 A 2 bit binary multiplier can be implemented using---------------------- III CO3
The minimum number of 2 to 1 multiplexers required to realize a 4 to 1
#3F-9 I CO3
multiplexer is
What are the minimum number of 2 to 1 multiplexer required to generate a 2-
#3F-10 II CO3
input AND gate and a 2- input EX-OR gate-------------------
#3F-11 Full adder circuit can be implement by I CO3
#3F-12 In a 4-bit full adder ,how many half adders and OR gates required-------------- VI CO3
#3F-13 Realization of full adder using HA and----------------Gate III CO3
#3F-14 JK FF is called a-------------------flip-flop I CO3
#3F-15 Which one of the following will give the sum of full adder as output--------- IV CO3
#Match The Following Questions
Match The Following Questions
A. BCD to 7 segment decoder 1.sequential circuit
#3M-1 I CO3
B. 4-to-1 MUX 2.combinational circuit
C. 4 bit shift register 3.neither sequential nor combinational circuit
A) Full adder 1. VLSI
#3M -2 B) Magnitude compactor 2. SSI I CO3
C) Programmable logic array 3. MSI
Match The Following Questions
#3M -3 II CO3
a) multiplexer 1.2^n:n
 b) encoder 2.n:2^n
c) decoder 3. 2n × 1
d) demultiplexer 4.1x2^n
#3M -4 Match The Following Questions CO3
a) full adder 1.combinatinal circuit
b) shift register 2.sequential circuit I
c) flip flop 3. 0 or 1
d) mux 4. 2x1

#5 MARKS QUESTIONS
Design 32×1 Multiplexer using 8×1 Multiplexers and 2 to 4 decoder. VI CO3
#3D-1

#3D-2 Build the full adder using two half adders and logic gates with truth table? III CO3
what is multiplexer? Design 8 to 1 mux using two 4 to 1 mux? VI CO3
#3D-3
#3D-4 what is comparator? Design &implement a 2-bit comparator using logic gates? I CO3
#3D-5 Define combinational circuit? I CO3
#3D-6 List the applications of multiplexer and demultiplexer I CO3
#3D-7 Compare decoder and Demultiplexer? IV CO3
#3D-8 Draw the truth table of Half Sub tractor? VI CO3
Construct the following functions using Multiplexer
#3D-9 F1 = m (2, 3, 6, 8, 12) III CO3
F2 = m (1, 3, 5, 6, 7, 8, 10)
#3D-10 Design Octal to Binary Encoder using OR gates? VI CO3
#3D-11 Explain about the Encoder and Decoders? I CO3
#3D-12 Explain about Multiplexer and Demultiplexer ? I CO3
#3D-13 Construct a FULL-Subtractor circuit and write a HDL program module for the same? II CO3
#3D-14 Write the discusses b/w synchronous and asynchronous sequential circuits? I CO3
#3D-15 What is edge triggering? define +ve and -ve edge triggering? II CO3

#UNIT-IV: SEQUENTIAL LOGIC:

BT Course
#Multiple Choice Questions Level Outcome
In synchronous circuits, the present state is determined by

A) unclocked flip-flops
#4C-1. B) clocked flip-flops I CO4
C) flip-flops
D) latches

Unclocked flip-flops are known as CO1

#4C-2. I
 A) Latches
B) register
C) Transition tables
D) clocked flip-flop

Transition table consists of

A) squares
#4C-3. B) rectangles I CO4
C) circles
D) oval

The change in state occurs during

A) pulse transition
#4C-4. B) outputs III CO4
C) clock pulses
D) inputs

Shift registers are used for

A) shifting
#4C-5 B) rotating I CO4
C) adding
D) both a and b

Enable input of the shift register is known as

A) load
#4C-6 B) store V CO4
C) reset
D) strobe

The shift register has an Integrated circuit with the number

A) 74195
#4C-7 B) 74123 II CO4
C) 74124
D) 74154

When J and complement of K are 1, flip-flop QA after the shift is equal to

A) 1
#4C-8 B) 0 VI CO4
C) reset
D) defined

State box has a shape of

A) square
#4C-9 B) rectangle I CO4
C) rhombus
D) pentagon
 Which one of the following is not the element of the ASM chart?

A) state box
#4C-10 B) decision box I CO4
C) data box
D) conditional box

Sequential operations in digital system are described by

A) map
#4C-11 B) ASM chart I CO4
C) flowchart
D) graph

Which of these flip – flops cannot be used to construct a serial shift register?
a) D – flip flop
#4C-12 b) SR flip – flop II CO4
c) T flip – flop
d) JK flip – flop
What kind of operation occurs in a J – K flip flop when both inputs J and K are
equal to 1?
a) Preset operation
#4C-13 I C04
b) Reset operation
c) Clear operation
d) Toggle operation
#4C-14 C04
A Johnson counter, constructed with N flip-flops, has how many unique
states?
a) N
b) 2N I
c) 2N
d) N2

#4C-15 A type of shift register in which the Q or Q output of one stage is not C04
connected to the input of the next stage is .
a) parallel in/serial out
b) serial in/parallel out III
c) serial in/serial out
d) parallel in/parallel out

#Filling The Blank Questions

A Johnson counter, constructed with N flip-flops, has how many unique states-----
#4F-1 I CO4
A 4-bit ring counter is loaded with a single 1. The frequency of any given output is
#4F-2 II CO4
.
#4F-3 Shifting a binary number to the left by one position is equivalent to . III CO4
#4F-4 A gated D latch does not have . IV CO4
 The maximum possible number of states in a clocked sequential circuit having 5 flip
#4F-5 I CO4
flops is
#4F-6 An R-S latch is ---------------------------------- II CO4
#4F-7 Synchronous counters are-------------------------than the ripple counters II CO4
A switch -trail ring counter is made by using a single D flip-flop the resulting circuit
#4F-8 II CO4
is a
The present output qn of an edge triggered JK flipflop is logic 0.if J=1 then
#4F-9 V CO4
Qn+1
Which one of the following equations satisfies the JK flip-flop truth
#4F-10. I CO4
table
#4F-11 State transition table and state transition diagram form part of the design steps CO4
I
is the case of
#4F-12 The characteristic equation of an SR flip-flop is given by IV CO4
#4F-13 The race around condition exists in JK flip-flop if---------------------- III CO4
#4F-14 Which of the following flip-flop cannot be converted to D-type (delay) flip-flop-- CO4
VI
#Match The Following Questions
A. Ripple Up Counter 1.Division
B. Synchronous Down Counter 2. Multiplication
#4M-1 III CO4
C. Shift Left Register 3. To Create Delay
D. Shift Right Register 4. Transient States
CO4
Match The Following Questions
A)Siso 1.Serial In Parallel
#4M-2 Out II
B) Sipo 2.Parallel In Parallel Out
C) Pipo 3.Parallel In Serial Out
D) Piso 4.Serial In Serial Out
#4M-3 Match The Following Questions CO4
a) T-FF 1.DELAY
b) D-FF 2.TOGGLE VI
c) JK -FF 3.SET-RESET
d) SR-FF 4. JACK KILBY
#4M-4 Match The Following Questions CO4
a) latch 1.level triggering
b) flip-flop 2. Edge triggering IV
c) register 3. Memory element
d) counter 4. Store 1 bit information
#4M-5 Match The Following Questions CO4
a) up counter 1. the last flip-flop fed to the input of the first
b) down counter 2. Cascaded arrangement V
c) ripple counter 3. 9 to 0
d) ring counter 4. 0 to 9

#5 MARKS QUESTIONS
 A) What is flip-flop? 1 CO4
#4D-1.
B) Define synchronous sequential circuit?
#4D-2. Write the Excitation table for JK flip flop? 1 CO4
#4D-3. Sketch the logic diagram of D flips flop? III CO4
Write the excitation table and characteristic equation for T flip flop? III CO4
#4D-4.
#4D-5. Distinguish between latch and flip flop? IV CO4
#4D-6. Write the truth table of SR flip flop? I CO4
#4D-7. Differentiate between ring counter & ripple counter? IV CO5
#4D-8. What are the applications of shift register? I CO5
#4D-9. What is a shift register? I CO5
#4D-10 What is sequential machine? I CO5
#4D-11 Explain about D Flip -Flop Can Be Made From J k Flip-Flop ? I CO4
#4D-12 Difference Between Moore Model And Melay Model? II CO4
#4D-13 Steps In Synchronous Sequential Circuit Design? II CO4
#4D-14 What Is State Assignment And Rules For State Assignment? I CO4
#4D-15 Explain about the Parallel In Serial Out Shift Register? I CO4

#UNIT-V: MEMORIES AND ASYCHRONOUS SEQUENTIAL LOGIC:

BT Course
#Multiple Choice Questions Level Outco
me
Asynchronous circuits are useful in application where the input signals may

A) change at any time

#5C-1. B) never change I CO5
C) both a and b
D) continuously change

The table that is not a part of the asynchronous analysis procedure is

A) transition table
#5C-2. B) state table I CO5
C) flow table
D) excitation table

That is the significant capacity/s of memory elements utilized in the sequential

circuits?

A) storage of binary information CO5

#5C-3. II
B) specify the state of sequential
C) both a and b
D) state machine

n the asynchronous circuit, the changes occur with the change of

#5C-4. IV CO5
A) input
B) output
 C) clock pulse
D) time

The complexity of the asynchronous circuit is involved in timing problems of

A) inputs
#5C-5 B) outputs V CO5
C) clock pulses
D) feedback path

A Condition occurs when an Asynchronous sequential circuit changes two or

more binary states variables is known as

A) deadlock condition CO5

#5C-6 II
B) Running condition
C) Race condition
D) livelock

Time delay device is the memory element of

A) Unclocked flip-flops
#5C-7 B) clocked flip-flops VI CO5
C) synchronous circuits
D) asynchronous circuits

Asynchronous sequential logic circuit not uses

A) inputs
#5C-8 B) outputs II CO5
C) clock pulses
D) time

The analysis of Asynchronous sequential circuits are used to obtain

A) a table
#5C-9. B) a diagram III CO5
C) graph
D) flowchart

In the design procedure of the asynchronous circuit, the flow of the table

A) increased to maximum states

#5C-10. B) reduced to minimum states I CO5
C) changed
D) remain same

Which of the following is not a type of memory? CO5

a) RAM
#5C-11 b) FPROM VI
c) EEPROM
d) ROM
#5C-12 The chip by which both the operation of read and write is performed CO5
II
a) RAM
b) ROM
 c) PROM
d) EPROM
#5C-13. RAM is also known as CO5
a) RWM
b) MBR I
c) MAR
d) ROM
#5C-14. If a RAM chip has n address input lines then it can access memory locations upto CO5
a) 2(n-1)
b) 2(n+1) III
c) 2n
d) 22n
#5C-15. The n-bit address is placed in the BR CO5
a) MAR
b) M VI
c) RAM
d) ROM
#Filling The Blank Questions
How many address bits are needed to select all memory locations in the 2118
#5F-1 I CO5
16K × 1 RAM
#5F-2 The storage element for a static RAM is the . II CO5
The condition occurring when two or more devices try to write data to a bus
#5F-3 III CO5
simultaneously is called .
#5F-4 A 64-bit word consists of .byte IV CO5
How many 2K × 8 ROM chips would be required to build a 16K × 8 memory
#5F-5 I CO5
system
#5F-6 ROM is made up of I CO5
#5F-7 Why are ROMs called non-volatile memory--------------------- II CO5
In ROM, each bit is a combination of the address variables is called
#5F-8 II CO5

#5F-9 PAL refers to III CO5

#5F-10 Outputs of the AND gate in PLD is known as V CO5
#5F-11 The inputs in the PLD is given through VI CO5
#5F-12 PLA contains CO5
I
#5F-13 PLA is used to implement II CO5
#5F-14 A PLA is similar to a ROM in concept except that I CO5
#5F-15 The difference between a PAL & a PLA is III CO5

#Match The Following Questions

Match The Following
A) RAM 1. Programmable Read-Only Memory
#5M-1 B) ROM 2.Random access memory II CO5
C) EEPROM 3. Read-Only Memory
D) PROM 4. Electrically Erasable Programmable Read Only
 Memory
Match The Following
A) DRAM 1. hard disk
#5M-2 B) SRAM 2. chip I CO5
C) RAM 3. a capacitor
D) ROM 4. A transistor

A) PROM 1. programmable
#5M-3 B) PAL 2. programmable AND gate &programmable OR III CO5
C) PLA 3. programmable AND array and fixed OR array
D) PLD 4. permanent and cannot be changed
#5M-4 Match The Following
A) Static hazard 1. output changes for two adjacent inputs
B) Dynamic hazard 2. input changes and the output to change I CO5
C) Essential hazard 3. unequal delays along two or more paths
D)RAM 4. main memory
#5M-5 Match The Following
A) error detection and correction 1. Parity Check and Cyclic Redundancy Check
(CRC).
B) memory decoder 2. addresses are used to identify the specific I CO5
memory location
c) Latch 3. circuits that store a single bit of information
d) RAM 4. non-volatile memory

#5 MARKS QUESTIONS
#5D-1. What is memory decoding? I CO5
#5D-2 What is Sequential (or simple) programmable logic device (SPLD) I
CO5

#5D-3 What is hazard? What are the various types of hazard that may be encountered II CO5
in acombinational logic? Explain in detail how hazards are eliminated?
#5D-4 Discuss About Binary Cell In Detail? II
CO5

#5D-5 Race -free state assignment hazard? I

CO5

#5D-6 The distinguish between a PAL & a PLA is? VI

CO5

#5D-7 Explain about programmable array logic?

CO5

#5D-8 Explain about programmable logic array? II

CO5

#5D-9 Discuss about error detection and correction II

CO5

#5D-10 Compare the read only memory(ROM) and random access memory(RAM)? III
CO5

#5D-11 Discuses about state reduction table? II

CO5
#5D-12 Define static hazard, Dynamic hazard AND Essential Hazard? I
CO5

#5D-13 Explain about circuits with latches and types of latches? II

CO5

#5D-14 State assignment to modified flow table and Multiple row assignment? I
CO5

#5D-15 Compare static Hazard and dynamic hazard? III

CO5