Institut für Integrierte Systeme

Integrated Systems Laboratory

Sample Solution Written Exam in VLSI I:

From Architectures to VLSI Circuits and FPGAs
227-0116-00L
Department of Information Technology and Electrical Engineering

6. Semester, Majors (Core Courses)

Dr. H. Kaeslin, Dr. N. Felber, Prof. Dr. W. Fichtner

Tuesday, 11. August 2009, 14:00–17:00

ETF C1

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• Please read through the problems first, then start solving them.

• For multiple choice questions, a variable number of statements can be correct including
all and none. Please indicate explicitly, when no statement is correct.

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is not necessary to solve them to obtain the highest grade.

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Figure 1: Percentage distribution of achievable points.

Chapter Nr.: 1 2 3 4 5 Sum

Achievable points: 151/2 50 19 37 21 1421/2

Achieved:

Good luck!

ii
 1 Introduction to Microelectronics . . . . . . . . . . . . . . . . . (151/2 points)
Problem 1: Concepts and terminology
(a) Name three quantities that are used to measure circuit size? (11/2)

(b) In the UMC L130 CMOS technology used in the VLSI 1 exercises, the 2-input (1)
AND gate occupies 5 cell units (cu), the 2-input NAND gate 4 cu, the standard
D-type flip-flop 20 cu, and the inverter 3 cu. If 600’000 cu are used by a CMOS-
Design (fabricated with the same technology), what is its hardware complexity in
gate equivalents (GE)?

Problem 2: Design flow in digital VLSI

(a) Fill in the missing items into the boxes of the Y-chart with the missing perspective- (3)
names, the levels of abstraction and the transitions from one perspective to the
other.

design

levels of abstraction

perspective start perspective

input/output system
mapping
subtasks hardware
subsystems
data moves ALUs,
and operations registers
truth tables, gates, latches,
state graphs flip-flops
transfer transistors,
functions wires

goal
mask polygons,
detailed layout

standard cells,
macro cells

placement
and routing
design
floorplan,
partitioning

chip or board

perspective

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VLSI I Exam Summer 2009
 (b) On which part of the VLSI design flow where the practical exercises of the VLSI 1 (1/2)
lecture based on? Select the correct answer.
A. Front-end design B. Back-end design

(c) Select for each statement whether it is true or false.

i) Logic simulation, timing verification and electrical rule check (ERC) are used (1/2)
to validate gate-level schematics or net lists.
A. True B. False

ii) Design for test (DFT) allows the improvement of the controllability and ob- (1/2)
servability of the inner circuit nodes without adding auxiliary circuitry.
A. True B. False

iii) In the floor planning step, each cell is assigned to a specific location. After (1/2)
that the metal wires, carrying the electrical signals between the cells, are
defined.
A. True B. False

iv) Layout versus schematic (LVS) verifies the conformity of the layout with ge- (1/2)
ometric rules given by the technology used.
A. True B. False

Problem 3: Field-programmable logic

(a) Encircle the correct characteristic in each cell of the table. (3)

Configuration Non- Reconfi- Unlimited Radiation

technology volatile gurable endurance tolerance

SRAM yes / no in / out yes / no good / poor

of circuit

EPROM yes / no in / out yes / no good / poor

of circuit

EEPROM yes / no in / out yes / no good / poor

of circuit
(b) The organization of hardware resources of field-programmable logic can be di-
vided into two classes: complex programmable logic devices (CPLD) and field-
programmable gate arrays (FPGA).
Select for each statement whether it is true for CPLDs, for FPGAs or for both.
i) This class(es) consist of many simple programmable logic devices. (1/2)
A. CPLD B. FPGA

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VLSI I Exam Summer 2009
ii) The logic AND-operation between two 10-bit input vectors can be realized in (1/2)
general with:
A. CPLD B. FPGA

iii) Which class of devices is better suited to realize a prototype for the upcoming (1/2)
WirelessHD standard?
A. CPLD B. FPGA

iv) Look-up tables and switch boxes can be found in (1/2)

A. CPLD B. FPGA

v) What is the difference between a fine-grained FPGA architecture and a coarse- (1)
grained FPGA architecture?

vi) The following figures, Fig. 1, Fig. 2, and Fig. 3, each shows a logic cell of (11/2)
an FPGA family. Please note for each logic cell whether it is a fine-grained
architecture or a coarse-grained architecture.
The adaptive logic module cell shown in Fig. 1 belongs to a
A. fine-grained architecture B. coarse-grained architecture

The VersaTile cell in Fig. 2 of an Actel FPGA belongs to a

A. fine-grained architecture B. coarse-grained architecture

The Virtex-4 slice in Fig. 3 of a Xilinx FPGA belongs to a

A. fine-grained architecture B. coarse-grained architecture

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VLSI I Exam Summer 2009
Figure 1: An adaptive logic module of a Altera FPGA

Figure 2: A logic VersaTile cell of an Actel FPGA.

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VLSI I Exam Summer 2009
Figure 3: A Virtex-4 slice of a Xilinx FPGA

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VLSI I Exam Summer 2009
 2 From Algorithms to Architectures . . . . . . . . . . . . . . . . (50 points)
Problem 1: Decide whether the following statements are correct. Give a short explanation for your
decision.
(a) The user interface of a mobile phone is better implemented using dedicated hard- (11/2)
ware instead of general purpose hardware to meet the stringent low-power require-
ments.

(b) The video decoder of a DVD player is preferably implemented using ASIPs rather (11/2)
than dedicated hardware if the flexibility to quickly support new encoding stan-
dards is more important than area and power efficiency.

(c) A data dependency graph does not allow any circular paths of weight zero. (11/2)

(d) The AT-product can not be significantly reduced when the architecture is trans- (11/2)
formed using iterative decomposition.

(e) Coarse-grained pipelining can reduce the power consumption of a circuit. (11/2)

(f) Even for very small memories the area can be significantly reduced when the (11/2)
implementation is changed from registers to on-chip DRAM.

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VLSI I Exam Summer 2009
Problem 2: The goal of this exercise is develop a few architectures of the CORDIC algorithm. This
algorithm is used to calculate trigonometric functions. The result is calculated iter-
atively by performing pseudo-rotations (not length preserving) on the vector
(x, y).
z keeps track of the angle, which is refined in each step by αi = di tan−1 2−i , di ∈
{−1, 1}. The more iterations are executed, the more precise the result becomes.

One CORDIC iteration is defined as follows:

x(i + 1) = x(i) − di 2−i y(i)

y(i + 1) = y(i) + di 2−i x(i)
z(i + 1) = z(i) − di tan−1 2−i

The coefficients ci = tan−1 2−i can be stored in a look-up table (LUT).

One example operation is rotation. To rotate (x(0), y(0)) by the angle z(0), one has
to choose di = sign(z(i)) = ±1, such that z → 0 (see Fig. 4).

y ( x(i), y(i) )

αi

( x(i+1), y(i+1) )

Figure 4: Example of one pseudo-rotation.

Fig. 5 shows the blocks required to build these architectures. One of them is a barrel
shifter, which performs an arithmetic shift by the number of bits configured at its
control input. Thus, it multiplies or divides by powers of two.

Area tpd
Register 100 µm2 0.1 ns
Multiplexer 200 µm2 0.2 ns
MUX add/sub barrel shifter Add/sub 800 µm2 1 ns
Barrel shifter 800 µm2 1 ns
LUT c LUT 200 µm2 0.2 ns
Constant 0 µm2 0 ns
register LUT constant

Figure 5: Basic building blocks with area and speed figures.

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VLSI I Exam Summer 2009
(a) Iterative architecture
i) Draw a block diagram of the iterative algorithm. In each clock cycle, one (4)
CORDIC iteration should be computed. The control path (including the cal-
culation of di ) can be neglected. Use only blocks given in Fig. 5. x(0), y(0), z(0)
are the inputs of your circuit and x(N ), y(N ), z(N ) the outputs after N iter-
ations.

ii) Calculate area, maximum frequency, and latency of this architecture for N=3 (2)
iterations (all timing parameters not given in Fig. 5 are negligible).

iii) Assume one pipeline stage is introduced in all loops. Can this help to improve (2)
the throughput? Explain!

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VLSI I Exam Summer 2009
(b) Fully parallel architecture
i) The iterations can also be unrolled such that feedback loops are no longer (4)
present. Draw the unrolled architecture for N=3 iterations. As before, use
blocks from Fig. 5 and neglect all control signals.

ii) One of the combinational blocks in the unrolled architecture can be signifi- (3)
cantly simplified in hardware compared to the iterative implementation. Iden-
tify this block and give new area and propagation delay estimations for this
block.

iii) Calculate area, maximum frequency, and latency of the unrolled architecture (2)
for N=3 iterations. (If the previous task was not solved, use the original
values for area and propagation delay of all blocks).

iv) How can the throughput of the new architecture be raised 3 times without (2)
large area overhead? Name the architecture transformation and describe the
changes.

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VLSI I Exam Summer 2009
(c) If area efficiency is the most important goal and latency is no issue, an iterative bit- (5)
serial architecture is the best solution. Draw a block diagram of such a CORDIC
architecture. Assume 8 bit word-width for all data signals and N=3 iterations.
Data are fed LSB first. Use the iterative architecture as a starting point and,
instead of the add/sub block, use the serial add/sub block in Fig. 6 that already
includes a register for the carry-bit and its correct handling. Again, the control
signals can be neglected.

add/sub

rst
Figure 6: Bit-serial adder

(d) Bonus question: Rotation is not the only function of the CORDIC. Find a rule (2)
for the calculation of di such that z approaches the angle between the vector (x, y)
and the x-axis (i.e. z → tan−1 (y/x)).

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VLSI I Exam Summer 2009
Problem 3: Consider the data dependency graph in Fig. 7. The input x[n] is real valued. Use
f (x) = x2 .

x[n]

c0 c1 c2 c3

f(x) f(x) f(x) f(x)

y[n]
max max max

Figure 7: DDG

(a) Find a mathematical expression describing the DDG above. (1)

(b) A possible hardware implementation is the isomorphic architecture. Describe how (2)
this architecture is obtained from a DDG.

(c) How can the ’max’ operations be reordered to shorten the critical path? Which (2)
algebraic property of this function is used?

(d) Commutativity and distributivity of multiplications allow to reduce the total num- (3)
ber of multiplications in this circuit. Draw the modified DDG.

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VLSI I Exam Summer 2009
(e) Re-timing can shorten the critical path of the circuit in Fig. 7. Perform a re- (2)
timing of all three registers and draw the resulting DDG. Which operation must
be performed before re-timing is possible?

(f) Does re-timing have an effect on latency? (1)

(g) What is a systolic DDG? Which transforms must be performed on the DDG in (4)
Fig. 7 to obtain a systolic DDG? Draw the resulting DDG.

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VLSI I Exam Summer 2009
 3 Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (19 points)
Problem 1: Testbenches and test cases.
(a) Why is it dangerous for VLSI designers to define critical test cases for functional (1)
verification of their own designs?

(b) Why is a hard-coded testbench often ill-suited for functional verification? When (1)
can a hard-coded testbench nonetheless be useful?

(c) What is the advantage of file-based over golden-model-based testbenches? (1)

(d) Consider the testbench setup in Fig. 8.

acqui
golden expout(1)
appli
model
for k = 1:2
expout(2) result = true;
stimuli if out(k) ~= expout(k) report
result = false;
out(1) end
design
appli under test end
out(2)

Figure 8: Testbench setup.

i) What type of testbench is it? (11/2)

ii) The response and actual response comparison is (pseudo-)coded in the figure. (1)
What is the problem with this comparison function (acqui)?

iii) Briefly describe a strategy to detect such flaws in the testbench. (1)

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VLSI I Exam Summer 2009
Problem 2: Verification example.
Have a look at the VHDL code in Listing 1.
(a) Draw an RTL block diagram, using flip-flops with active low reset, positive edge- (11/2)
triggered clock input, and an enable signal.

(b) Provide a lower bound for the number of clock cycles for exhaustive verification (2)
(formula and numerical value). Does this bound hold with equality (in general)?
Explain your reasoning.

(c) i) Considering the inputs of the circuit, how can you reduce the verification (1)
effort while still verifying most of the functionality?

ii) For non-exhaustive verification in general, how can you make sure to detect (1)
functional bugs?

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VLSI I Exam Summer 2009
(d) Draw a timing diagram with multiple clock cycles and indicate the simulation (2)
events with respect to the clock signal. With an arrow, indicate the correspondence
of one data stimuli (InputxDI) application event with its response acquisition.

(e) For the rest of this exercise, assume that the reset and enable signals are logically
high (’1’), and can therefore be omitted.
i) Draw a state transition diagram. (2)

ii) Find a minimum-length input sequence to ensure exhaustive verification. (2)

iii) In one sentence, formulate a general condition for exhaustive verification using (1)
state-diagram terms (edges and vertices).

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VLSI I Exam Summer 2009
 4 Modelling Hardware with VHDL . . . . . . . . . . . . . . . . . . (37 points)
Problem 1: Hardware synthesis
(a) Several computer languages exist for modelling digital hardware on register trans- (1)
fer level. Which languages do you know? Please name at least two.

(b) Which of the following statements are correct? Mark the correct statements with (2)
a cross.
A. VHDL does not need a special concept for handling time as it describes
hardware that is synthesized into gates.

B. VHDL provides statements to describe circuit hierarchy.

C. VHDL can only be used to describe digital circuits.

D. Concurrency can be expressed in VHDL.

E. VHDL instances are always tied to some fixed input word width.

F. Timing-related VHDL constructs do not impose target requirements for

the synthesis process.

Problem 2: (a) Mark the correct statements below regarding bidirectional buses with a cross. (11/2)
A. The data-type for bidirectional buses must be std_ulogic or
std_ulogic_vector.
B. It is not possible to drive a signal from multiple processes unless a res-
olution function is defined.
C. To model a bidirectional bus in VHDL, each driving input to the bus
can be described by a conditional signal assignments and is set to ’0’
when not enabled.
D. It is not possible to use variables to describe a bidirectional bus.
(b) When does a process statement exhibit sequential behavior? Mark the correct (11/2)
statements below with a cross.
A. When the process fails to assign a value to its output signals for every
possible combination of values of its inputs.
B. When a signal representing a clock (e.g., ClkxCI ) is present in a process
statement.
C. When the label of the process statement contains the keyword memzing.
D. When a process statement includes variables that get assigned no value
before being used.
E. When a process includes multiple wait on statements.

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VLSI I Exam Summer 2009
(c) Initialization and reset mechanism.
i) Mark the correct statements. (1)
A. Initialization of a signal in the signal declaration part and a signal
assignment in the reset clause of a sequential process lead to the
same implementation result.
B. Signal initialization is for simulation purposes only.
C. A hardware reset mechanism brings a circuit into a predetermined
state at any time.
ii) A register RegxDP with the following properties is to be designed. The clock (3)
signal is called ClkxCI.
• An asynchronous active-low reset mechanism. The reset value of the register
is all zero. The name of the reset signal is RstxRBI.
• A synchronous load that sets the Register RegxDP to all ones when LoadxSI
is asserted.
• A synchronous enable EnaxEI that makes the signal RegxDN to the new
register content when enabled.
• The load signal LoadxSI has priority over the enable signal EnaxEI.
Assume that all signals are correctly declared. Write the VHDL process state-
ments for this register specification.

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VLSI I Exam Summer 2009
Problem 3: Binary-to-BCD conversion
In Listing 2, the top-level entity of a binary-to-BCD converter is shown. In binary
coded decimal (BCD) format, a decimal number is represented as a sequence of 4-bit
BCD digits. A binary-to-BCD conversion circuit converts a binary number to the BCD
format. For example, the binary number ”0010 0000 0000” becomes ”0101 0001 0010”
(i.e., 51210 ) after conversion.
(a) Draw the high-level block diagram of the binary-to-BCD conversion circuit for (4)
N = 3. Only Listing 2 needs to be considered. For the moment, the instantiated
component Digit can be regarded as black box. Your block diagram shall visualize:
• the names and hierarchy of the entities
• the connectivity of the blocks and the word width of the signals
• the contribution of each block to the signal BcdOutxDO.
• the breakdown of the signal ModVecxD

(b) Listing 3 describes the entity “Digit”.

i) How many concurrent processes can you find in Listing 3? (1)

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VLSI I Exam Summer 2009
 ii) Reformulate the process statement from line 38 to line 46 as selected signal (2)
assignment.

iii) Please describe at least three major differences between the process statement (2)
and a concurrent/selected/conditional signal assignment.

(c) Now, we consider both Listing 2 and Listing 3 and we choose N = 3.

i) How many flip-flops do you expect when synthesizing this BCD-conversion (1)
circuit?

ii) How many clock cycles does it take to convert a 12-bit BCD number (N = 3) (2)
and what is the latency of this circuit?

iii) Bonus question: do not spend to much time on this question. (2)
In a first version of the BCD-converter, the process statement in Listing 3,
line 24–51 was replaced by the process statement given in Listing 4. Can you
explain why the simulation with the process from Listing 4 was not working as
expected, while with the current version of the entity “Digit”, the simulation
result was correct?

iv) Rewrite the process statement of Listing 4 (line 1 to line 11) without using (2)
the process statement construct. You are allowed to use as many new signals

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VLSI I Exam Summer 2009
 as you might need. Please declare them properly.

Problem 4: State machines and testbenches.

(a) A finite state machine (FSM) can be described in a single process statement or
distributed over two or more concurrent processes.
i) Which way is preferred and leads to better results? Why? (2)

ii) Draw a diagram/schematic/skeleton of the preferred coding scheme for a syn- (3)
chronous Mealy machine. It shall visualize:
• the number of processes used
• registers and combinational operations
• input, output, and clock

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VLSI I Exam Summer 2009
 (b) What is a testbench good for? Mark the correct answer(s). (1)
A. It applies stimuli to the design under test.
B. It reports the maximum clock frequency of the design under test.
C. A testbench must be synthesizable in order to verify the timing of the
final circuit.
D. Assertion statements can be used in a testbench to report potential
design flaws.

Problem 5: Event-driven simulation.

(a) What are the three steps involved in an event-driven simulation? Explain them (3)
with a few words.

(b) Explain the difference between a signal and a variable with respect to the event (2)
queue.

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VLSI I Exam Summer 2009
 5 The Case for Synchronous Design . . . . . . . . . . . . . . . . . (21 points)
Problem 1: Warm up.

(a) Describe two disadvantages of synchronous circuit operation. (2)

(b) What are the two guiding principles of synchronous design? (2)

Problem 2: Clocking disciplines and hazards.

Mark all the correct answers.

(a) Which clocking disciplines allow for an arbitrary slow clock frequency? (1)
A. Synchronous edge-triggered clocking
B. Self-timed
C. Ad hoc asynchronous
(b) Where are hazards allowed? (1)
A. On the write line of an asynchronous RAM
B. On the synchronous preset port of flip-flop registers
C. On the state signal of a FSM in a synchronous design
D. On all signals in a self-timed design
(c) Which statements regarding self-timed clocking are correct? (1)
A. Hazard-suppression logic is not necessary.
B. A global signal is necessary to control the handshake signal.
C. Self-timed clocking helps to avoid problems at the circuit interfaces.
D. It is possible to achieve a better performance than worst-case with self-
timed clocking.

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VLSI I Exam Summer 2009
Problem 3: Synchronous design

ClkxC Block B

Block A

means level sensitive

means single edge triggered

Figure 9: Circuit extracted out of a larger design.

(a) Mark the clocking discipline of the circuit extract in Fig. 9 (1)
A. Synchronous edge-triggered clocking
B. Asynchronous clocking
C. Clock-as-clock-can
D. Self-timed clocking
(b) Explain the functionality of block A in Fig. 9 and explain potential problems with (3)
this design.

(c) Bonus question: Give an alternative solution that avoids this problem by only (2)
altering block A only.

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VLSI I Exam Summer 2009
(d) Describe an alternative solution with the same functionality that also avoids the (2)
aforementioned problem and is obtained by a modification in block B.

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VLSI I Exam Summer 2009
Problem 4: Fig. 10 shows a sequential circuit. All non zero timing parameters are marked in Fig. 10
(e.g., neglect the propagation delay of the multiplexer).

tsk,clk
ClkxC
RstxRB
tsk,rst

tpd c1 , tcd c1

tpd tpd
tsu , tho tsu , tho

tpd c2 , tcd c2

Figure 10: Sequential circuit with timing parameters.

(a) Explain the additional functionality required to assure correct execution of this (3)
circuit under all circumstances? Consider the circuit in Fig. 10 as a top-level
entity that is directly connected to an external quartz oscillator and reset button.
Draw a block diagram of the additional functionality.

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VLSI I Exam Summer 2009
(b) Given the added functionality. What is the maximum value for tsk,rst ? (Assume (1)
that the setup time for the reset pin of the employed flip-flop registers is zero.)

(c) What is the minimum clock period for this circuit? (2)

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VLSI I Exam Summer 2009
 Listings

1 library i e e e ;
2 use i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
3 use i e e e . numeric_std . a l l ;
4
5 entity f b c i r c u i t i s
6
7 port (
8 InputxDI : in std_logic ;
9 OutputxDO : out std_logic ;
10 ClkxCI : in std_logic ;
11 RstxRBI : in std_logic ;
12 EnablexSI : in std_logic ) ;
13
14 end f b c i r c u i t ;
15
16 architecture r t l of f b c i r c u i t i s
17
18 s i g n a l Reg1xDP , Reg1xDN : s t d _ l o g i c ;
19 s i g n a l Reg2xDP , Reg2xDN : s t d _ l o g i c ;
20
21 begin −− r t l
22
23 p_seq : process ( ClkxCI , RstxRBI )
24 begin −− p r o c e s s p_seq
25 i f RstxRBI = ’ 0 ’ then −− a s y n c h r o n o u s r e s e t ( a c t i v e low )
26 Reg1xDP <= ’ 0 ’ ;
27 Reg2xDP <= ’ 0 ’ ;
28 e l s i f ClkxCI ’ e v e n t and ClkxCI = ’ 1 ’ then
29 i f EnablexSI = ’ 1 ’ then
30 Reg1xDP <= Reg1xDN ;
31 Reg2xDP <= Reg2xDN ;
32 end i f ;
33 end i f ;
34 end process p_seq ;
35
36 Reg1xDN <= InputxDI xor Reg2xDP ;
37 Reg2xDN <= Reg1xDP ;
38
39 OutputxDO <= Reg2xDP ;
40
41 end r t l ;

Listing 1: Feedback circuit.

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VLSI I Exam Summer 2009
 1 l i b r a r y IEEE ;
2 use IEEE . s t d _ l o g i c _ 1 1 6 4 . a l l ;
3
4 entity BCDConv i s
5 generic (N : p o s i t i v e ) ; −− number o f d i g i t s
6 port ( ClkxCI : in s t d _ l o g i c ;
7 RstxRBI : in s t d _ l o g i c ;
8 InitxSI : in s t d _ l o g i c ; −− i n i t i a l i s e c o n v e r s i o n
9 ModInxDI : in s t d _ l o g i c ; −− c a r r y i n from o u t s i d e
10 ModOutxDO : out s t d _ l o g i c ; −− c a r r y o u t
11 BcdOutxDO : out s t d _ l o g i c _ v e c t o r ( 4 ∗N −1 downto 0 ) −− BCD r e s u l t
12 );
13 end ;
14
15 architecture RTL of BCDConv i s
16
17 component D i g i t
18 port (
19 ClkxCI : in std_logic ;
20 RstxRBI : in std_logic ;
21 InitxSI : in std_logic ;
22 ModInxDI : in std_logic ;
23 ModOutxDO : out std_logic ;
24 BcdOutxDO : out s t d _ l o g i c _ v e c t o r ( 3 downto 0 ) ) ;
25 end component ;
26
27 s i g n a l ModVecxD : s t d _ l o g i c _ v e c t o r ( 1 to N+1);
28
29 begin
30
31 g1 : f o r I in 1 to N generate
32 c1 : D i g i t
33 port map (
34 ClkxCI => ClkxCI ,
35 RstxRBI => RstxRBI ,
36 InitxSI => InitxSI ,
37 ModInxDI => ModVecxD( I +1) ,
38 ModOutxDO => ModVecxD( I ) ,
39 BcdOutxDO => BcdOutxDO( I ∗4−1 downto I ∗4 −4));
40 end generate ;
41
42 ModOutxDO <= ModVecxD ( 1 ) ;
43 ModVecxD(N+1) <= ModInxDI ;
44
45 end ;

Listing 2: Top-level unit of the BCD converter.

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 1 l i b r a r y IEEE ;
2 use IEEE . s t d _ l o g i c _ 1 1 6 4 . a l l ;
3
4 entity D i g i t i s
5 port ( ClkxCI : in std_logic ;
6 RstxRBI : in std_logic ; −− a s y n c h r o n o u s r e s e t ( a c t i v e low )
7 InitxSI : in std_logic ; −− i n i t i a l i s e t h e BCD c o n v e r s i o n
8 ModInxDI : in s t d _ l o g i c ; −− modulus i n from l e s s s i g n i f i c a n t d i g i t
9 ModOutxDO : out s t d _ l o g i c ; −− modulus o u t t o more s i g n i f i c a n t d i g i t
10 BcdOutxDO : out s t d _ l o g i c _ v e c t o r ( 3 downto 0 ) −− BCD o u t p u t
11 );
12 end ;
13
14 architecture RTL of D i g i t i s
15 s i g n a l BcdInternxDP , BcdInternxDN : s t d _ l o g i c _ v e c t o r ( 3 downto 0 ) ;
16 s i g n a l NextModOutxS : std_logic ;
17 begin
18
19 −− C a l c u l a t e t h e s h i f t i n t h e BCD r e g i s t e r . Numbers b e t w e e n
20 −− 0 and 4 i n c l u s i v e a r e d o u b l e d , by s h i f t i n g by 1 .
21 −− Numbers from 5 t o 9 i n c l u s i v e g e t mapped t o 10 , 12 , 14 ,
22 −− 16 , 1 8 . This g i v e s an modout o f 1 ( i . e . a c a r r y t o t h e
23 −− n e x t d i g i t ) , and t h e v a l u e s 0 , 2 , 4 , 6 , 8 .
24 BCDdoubler : process ( BcdInternxDP , ModInxDI )
25 begin
26 case BcdInternxDP i s
27 when " 0000 " =>
28 BcdInternxDN ( 3 downto 1 ) <= " 000 " ;
29 when " 0001 " =>
30 BcdInternxDN ( 3 downto 1 ) <= " 001 " ;
31 when " 0010 " =>
32 BcdInternxDN ( 3 downto 1 ) <= " 010 " ;
33 when " 0011 " =>
34 BcdInternxDN ( 3 downto 1 ) <= " 011 " ;
35 when " 0100 " =>
36 BcdInternxDN ( 3 downto 1 ) <= " 100 " ;
37 when " 0101 " =>
38 BcdInternxDN ( 3 downto 1 ) <= " 000 " ;
39 when " 0110 " =>
40 BcdInternxDN ( 3 downto 1 ) <= " 001 " ;
41 when " 0111 " =>
42 BcdInternxDN ( 3 downto 1 ) <= " 010 " ;
43 when " 1000 " =>
44 BcdInternxDN ( 3 downto 1 ) <= " 011 " ;
45 when " 1001 " =>
46 BcdInternxDN ( 3 downto 1 ) <= " 100 " ;
47 when others =>
48 BcdInternxDN ( 3 downto 1 ) <= ( others => ’ − ’ ) ;
49 end case ;
50 BcdInternxDN ( 0 ) <= ModInxDI ;
51 end process ;

Sourcecode continues on next page.

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52 −− i f t h e numbers a r e g r e a t e r than 5 , we s h o u l d g e n e r a t e a
53 −− c a r r y o u t ( modulus o u t ) t o t h e n e x t d i g i t .
54 ModOutGen : process ( BcdInternxDP )
55 begin
56 case BcdInternxDP i s
57 when " 0101 " | " 0110 " | " 0111 " | " 1000 " | " 1001 " =>
58 NextModOutxS <= ’ 1 ’ ;
59 when others =>
60 NextModOutxS <= ’ 0 ’ ;
61 end case ;
62 end process ;
63
64 −− When I n i t i s h i g h , we f o r c e ModOut t o 0
65 ModOutxDO <= NextModOutxS and ( not I n i t x S I ) ;
66 BcdOutxDO <= BcdInternxDP ;
67
68 p_ShiftReg : process ( ClkxCI , RstxRBI )
69 begin −− p r o c e s s p _ S h i f t R e g
70 i f RstxRBI = ’ 0 ’ then −− a s y n c h r o n o u s r e s e t ( a c t i v e low )
71 BcdInternxDP <= ( others => ’ 0 ’ ) ;
72 e l s i f ClkxCI ’ e v e n t and ClkxCI = ’ 1 ’ then −− r i s i n g c l o c k e d g e
73 i f I n i t x S I = ’ 1 ’ then
74 BcdInternxDP <= ( others => ’ 0 ’ ) ;
75 BcdInternxDP ( 0 ) <= ModInxDI ;
76 else
77 BcdInternxDP <= BcdInternxDN ;
78 end i f ;
79 end i f ;
80 end process p_ShiftReg ;
81 end ;

Listing 3: Digit entity of the BCD converter.

1 BCDdoubler : process ( BcdInternxDP , ModInxDI )

2 variable v_BcdInterTmp : s t d _ l o g i c _ v e c t o r ( 3 downto 0 ) ;
3 begin
4 i f u n s i g n e d ( BcdInternxDP ) < 5 then
5 BcdInternxDN ( 3 downto 1 ) <= BcdInternxDP ( 2 downto 0 ) ;
6 else
7 v_BcdInterTmp := s t d _ l o g i c _ v e c t o r ( u n s i g n e d ( BcdInternxDP ) −5);
8 BcdInternxDN ( 3 downto 1 ) <= v_BcdInterTmp ( 2 downto 0 ) ;
9 end i f ;
10 BcdInternxDN ( 0 ) <= ModInxDI ;
11 end process ;

Listing 4: Digit entity of the BCD converter.

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