Performance analysis of MC DS CDMA for various techniques using

CADENCE
A.K.Gnanasekar1 and Dr.V.Nagarajan2
1Research Scholar , Adhiparasakthi Engineering College, India
2Professor and Head, Department of Electronics and Communication Engineering,
Adhiparasakthi Engineering College, India.
Email: kgnanshek@gmail.com
Abstract: Multi carrier direct sequence CDMA (MC-
DS CDMA) is now trending fourth generation high
speed wireless communications as it can provide
reliable communication over a challenging fading
environment .Also it is capable of improving the
system performance by toning down the intersymbol
interference (ISI).In this paper we have analyzed the
performance of MC DS CDMA with Nagakami
fading channel and hybrid concatenated code model
based on parameters like memory, execution time,
number of transient steps required for the execution
and power consumed. CADENCE is used for
synthesis of the system.
Keywords –MC-DS-CDMA, Nagakami fading
channel, Hybrid Concatenated code
I. INTRODUCTION
In recent years, with the ease of internet access,
the need for wireless communication technology has
been increased. The demand for higher data rate and
improved reliability is going high day by day. A
variant of CDMA system that combines the
advantages of both Orthogonal Frequency Division
Multiplexing (OFDM) – a multi carrier transmission
technique and Direct Sequence CDMA which is term
as MC-DS-CDMA provides higher data rate for
wireless transmission.
MC CDMA schemes spread the data stream in
two ways. One spreads the original data stream using
a given spreading code, and then modulates a
different subcarrier with each chip (in a sense, the
spreading operation in the frequency domain), and
other spreads the serial-to-parallel (S/P) converted
data streams using a given spreading code, and then
modulates a different subcarrier with each of the data
stream (the spreading operation in the time domain).
In direct sequence CDMA systems, a narrow
band message signal is multiplied with a spreading
signal whose bandwidth is usually very large. Upon
this multiplication operation the narrow band
message signal will be converted in to a wide band
signal. All the users in a DS CDMA system use the
same carrier frequency at a same time and transmit
simultaneously. Every user will have individual
spreading signal, which will be orthogonal to the
spreading signals of other users. Correlation
operation is being carried out by the receiver to detect
the message to a given user. The sequences from
other users appear as noise due to de-correlation
Multi carrier direct sequence CDMA suitable for
high speed wireless communications, should be
highly spectral efficient for supporting multiple user
access and also meet the increasing demands for high
bit rate, coverage bandwidth and power efficiency.
Multi access interference (MAI) and multipath fading
severely affect the performance and degrade the
quality of received signal.MC DS CDMA system
should be able to overcome the channel impairments.
In this paper the performance of the MC-DS-
CDMA system is analyzed with different techniques.
This paper is organized as follows: the MC-DS-
CDMA system model is described in Section II.
Simulation results and analysis are provided in
Section III. Section IV describes the performance
analysis of MC-DS-CDMA in Nakagami fading
channel and Concatenated Coding model. Finally, the
main conclusions of the paper and its application are
stated in Section V.
II. SYSTEM MODEL
The MC-DS-CDMA signal is generated by serial-
to-parallel converting data symbols into sub-streams
and applying DS-CDMA on each individual sub-
stream. The serial-to-parallel converted data stream is
multiplied with the spreading sequence, and then the
chips belonging to the same symbol modulate the
same subcarrier. Here the spreading is done in the
time domain. Thus this MC-DS-CDMA technique
plays vital role in uplink transmission of wireless
communication than any other access. Thus, with
MC-DS-CDMA, each data symbol is spread in
bandwidth within its sub-channel.
Fig 2.1. MC-DS-CDMA Transmitter Block Diagram

MC-DS-CDMA receiver receives the

transmitted signal as a summation of i number of
users. At first it demodulates the received signal by
the same carrier frequency of each signal and then the
signals multiply with the specific codes given by the
receiver code generator. Then we get the signal of i th
user which is same for transmitter and receiver. After Fig:3.1 Serial to Parallel Converter Design in
that low pass filter removes the high frequency Transmitter Side
portions of the signal. Finally, the P/S converter
presents the actual digital data signal.

Fig:3.2 Serial to Parallel Converter output

Fig 2.2.MC-DS-CDMA Receiver Block Diagram

III. SIMULATION RESULTS AND ANALYSIS

Simulation output is to be obtained by using

CADENCE in analog design. In this Multi Carrier
Direct Sequence CDMA transmitter block was
designed. For the transmitter modulation scheme
given below shows the analog design of the BPSK Fig:3.3 Analog design of BPSK modulator
modulator for both Nakagami fading channel and
Concatenated Coding models. The current and
voltage measurements are shown by figures 3.1 to 3.6
which are should be used on the transmitter
block of BPSK modulator. Where maximum of 1.8 v
should be given to each vpulse of the source input.

The inputs are given to each resistance and

transistors and assign the vpulse as 1.8 v and choose
the transient response model and give the required
parameters. After to select the schematic of vdc or
any other parameter and simulate the circuit. Fig:3.4 Transient response of BPSK modulator
 CPU ELAPSED
CONDITION TIME TIME
Initial condition solution
999 us 410.08 us
time
Intrinsic transient
2 ms 2.4950 ms
analysis time
Total time required for
5.999 ms 11.4231 ms
transient analysis
Time accumulated
226.964 ms 955.202 ms
Fig:3.5 Simulation of power output BPSK
Next the analog design of channel model is
designed and the simulation output of channel model
was obtained at 5 ns the output should be determined.
The time required for this channel has 3.27ms.
Table4.2 shows the CPU and ELAPSED time
required for channel model. The time accumulated for
CPU has 253.96 ms and 940.988 ms for usage time.

Table4.3 gives the DC analysis of CPU and

ELAPSED time. The total time required for CPU has
821.875ms and usage time has 850.942 ms. The time
accumulated for 1.02684 s for CPU and 1.67693 s for
Fig:3.6 . Analog design of Channel model usage time. The peak memory used as 29.8 Mbytes.
IV. PERFORMANCE ANALYSIS Table: 4.2 CPU time and ELAPSED time required
for channel model of transient analysis
Output for serial to parallel converter is obtained
at the input pin Vin and Vin2 and at the output pin CPU ELAPSED
vout and vout1.The schematic is designed in 27℃ CONDITION TIME TIME
because the designing temperature is very important Initial condition solution 1.999ms 1.055ms
time
in case of chip design if the temperature was very
Intrinsic transient
high then the fault will occur in the designing of chip 7.999 ms 8.135 ms
analysis time
and the device will get failure. In ordered to obtain Total time required for
the proper result the design should be done in the 12.997ms 17.987 ms
transient analysis
particular temperature. Time accumulated
253.96ms 940.988 ms
The serial to parallel output was
obtained from the time of 3.1 ns to 98.55 ns and
absolute voltage and current obtained is 1µv and
1pA.Number of transient steps required for the
Table:4.3 CPU time and ELAPSED time required
transmission of data is 54. The serial to parallel
for channel model of DC analysis
output was obtained from the
time of 3.1 ns to 98.55 ns. The number of accepted CPU ELAPSED
transient steps is 54. Peak resident memory CONDITION TIME TIME
used=33.1 Mb. Table4.1 Shows the CPU time and Total time required for
821.875ms 850.942 ms
elapsed time required at particular condition for serial DC analysis
to parallel converter. Time accumulated
1.02684s 1.67693s
Table:4.1 CPU time for serial to parallel converter
 V. CONCLUSION Cognitive Radio Femtocell System”, IEEE Transactions On
VehicularTechnology, VOL. 61, NO. 1, pp.166-184

In this paper, by designing a MC-DS-CDMA

system in virtuoso environment using cadence the A.K.Gnanasekar received B.E degree in Electronics and
Communication Engineering from Madras University,
good accuracy of the design is obtained and several India. He received M.E degree in medical electronics
different parameters can be determined. Such as, the from Anna University, India. He was pursuing Ph.D in
memory required, execution steps required, CPU time AnnaUniversity, Chennai, India. He has three and half
and elapsed time required The performance of MC- years of working experience in industry. He is working as
Associate professor in Jawahar Engineering
DS-CDMA transmitter block was analyzed using College,Chennai, India having teaching experience more
Analog design. From this result we can conclude that than 20 years. He is a senior member in ISTE, IASCIT,
the information to be encoded and transmit over the IAENG and fellow in IETE. He published 33 papers in
channel and decode the original information .It can be national and international conferences, journals. His
research interest includes wireless communication, VLSI,
used for the mobile application. This work can be mobile communication, medical electronics, signal
further enhanced by undergoing the process of processing and image processing.
implementation. Application, The 4G mobile system
is the future mobile system through which a higher Dr.V.Nagarajan received B.E degree from Madras
University, India. He received M.Tech degree from
data rate service will be provided. It is the integration Pondicherry Engineering College, India. He received his
of other wireless systems, including GSM, UMTS Ph.D in Pondicherry Engineering College, India. He has
and WiMAX. working experience of about 18 years. He is a chief
member in IEEE, MISTE, IETE, IASTE, and IAE. He
published more than 60 papers in national and
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