STM32以太网外设

The OSI model 2

Application layer

TCP-IP Protocol Suite

Other Protocols Presentation Layer

Session Layer

TCP / UDP Transport Layer

IP Network Layer

Data Link Layer : STM32

Media Access Control
Manage communication
Ethernet

(MAC) Ethernet
between network entities:

Physical layer Physical Layer:

(PHY) Transport the data on the physical support
Ethernet Block Diagram 3
 Ethernet Block Diagram 4

DMA MAC PHY

Intereface
 Ethernet Block Diagram 5

DMA MAC PHY

Intereface
 Physical Layer Interface 6

• Supports both Media Independent Interface (MII) and Reduced Media

Independent Interface (RMII).
• RMII is a lower pin count alternative, which targets multi-port applications
and low cost design:
• Internal loopback on the MII for debugging.
• MDC/MDIO for the PHY configuration

RMII
interface
Select
Media External
Access Control PHY
MAC 802.3 MII
MDC

MDIO
 Physical Layer Interface
TX _CLK 7
TXD[3:0]
• MII = 18 pins TX_ER
TX_EN
• 8 data pins

STM324x7
RX _CLK

802.3 MAC
• 6 control pins RXD[3:0]
External
RX_ER
• 2 Clock signals RX_DV
PHY

• 2 for PHY configuration CRS

COL
• TX_ER(optional, rarely used， MDC
STM32 don’t have this pin) MDIO

PHY_CLK
Selected in SYSCFG_PMC
• RMII = 10 pins TXD[1:0]
TX_EN
• 4 data

STM324x7
RXD[1:0]

802.3 MAC
• 3 control RX_ER
External
• 1 for the clock CRS_DV
PHY
MDC
• 2 for PHY configuration MDIO
• RX_ER(optional on switches) REF_CLK

PHY_CLK
 Ethernet Interface Block Diagram (1/4) 8

• One 25Mhz external crystal (internal oscillator)

• The internal PLL to generate HCLK (Core, peripherals…)
• Connected to the MCO to provide the 25Mhz to the PHY

MII 15 pins
MII+MDC
Ethernet = 18 pins
MAC 10/100
MDC/MDIO 2 pins

XTAL
HCLK
25MHz OSC PLL
25MHz MCO XT1
25MHz PHY
STM32F107/2x7/4x7
 Ethernet Interface Block Diagram (2/4)
• One 50Mhz external oscillator 9

• This 50Mhz output clock is provided to the MAC & the PHY

• One 25Mhz external crystal (internal oscillator)

• The internal PLL to generate HCLK (Core, peripherals…)

• RMII interface
• 7 pins for the communication between the MAC & PHY
• 2 pins for the MDC (PHY control)
• 1 pin for the 50Mhz clock input

Ethernet
RMII 7 pins
RMII+MDC
MAC 10/100
1 pin +clock
50MHz = 10 pins
MDC/MDIO 2 pins
XTAL
25MHz OSC HCLK
PLL

STM32F107/2x7/4x7 XT1/XT2
OSC
50MHz 50MHz PHY
 Ethernet Interface Block Diagram (3/4) 10

• One 50Mhz external oscillator

• Connected to the PLL to generate HCLK (Core, peripherals…)
• This 50Mhz output clock is provided to the MAC & the PHY

Ethernet
RMII 7 pins
RMII+MDC
MAC 10/100
1 pin +clock
50MHz = 10 pins
MDC/MDIO 2 pins

HCLK
OSC PLL
50MHz STM32F107/F4x7 XT1/XT2
50MHz PHY
 Ethernet Interface Block Diagram (4/4)
• One 25Mhz external crystal (internal oscillator) 11

• The internal PLL to generate HCLK (Core, peripherals…)

• Connected to the MCO to provide the 25Mhz to the PHY
• The PHY then generate the 50MHz clock reference clock

• RMII interface
• 7 pins for the communication between the MAC & PHY
• 2 pins for the MDC (PHY control)
• 1 pin for the 50Mhz clock input

Ethernet
RMII
MAC 10/100
50MHz Clk
MDC/MDIO
XTAL
25MHz OSC PLL
HCLK
Clk_out 50MHz
25MHz
XT1 25MHz PLL
STM32F107/2x7/4x7
PHY
PHY Registers 12

• The PHY Registers are :

• Initialized by the Bootstrap configuration
• Can be accessed by the MCU (providing that the PHY Address is correct)

• There are 3 types of Registers :

• Basic
• Extended
• Vendor Specific

• How to change PHY when using ST’s driver

Example LAN 8742A 13
Read the Auto-negotiation’s result of DP83848C (1/3)
14
Read the Auto-negotiation’s result of LAN8742A (2/3)
15
How to change PHY when using ST’s driver (3/3) 16

• So when you change from PHY to another, the user have to update
this value depending on the used external PHY.

• In file “stm32f7xx_hal_conf.h”

/* The DP83848 PHY status register */

#define PHY_SR ((uint16_t)0x10) /* PHY status register Offset */

#define PHY_SPEED_STATUS ((uint16_t)0x0002) /* PHY Speed mask

#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /* PHY Duplex mask */

Media Access Control(MAC) 17

MAC
 Media Access Control 18
• Operation modes and PHY support
• 10/100Mbps data rate
MAC 802.3
• Full-duplex and half-duplex operations
• MII and RMII interface to external PHY MAC Control
Registers
• Offload processing
• Preamble and start-of-frame data (SFD) Offload PTP
insertion or deletion Processing IEEE1588
• Checksum checking of IPv4 header and
TCP, UDP, or ICMP payload PMT MMC
• Calculates and inserts IPv4 header and TCP,
UDP, or ICMP payload checksums
• Low power mode
• Remote wakeup packet and AMD Magic
Packet™ detection
• Processing control
• MAC address filtering
• IEEE 802.3-2002 standard
• IEEE 1588-2008/PTPv2 support
• Supports network statistics with RMON/MIB
counters (RFC2819/RFC2665)
 MAC 802.3 Operation : the frame format 19

8 368 to 12000 bits 32

56 bits 48 bits 48 bits 16bits
bits / 46 to 1500 bytes bits
Destination Source Length
Preamble SFD Data FCS
Address Address / Type

Start of Frame
Destination
Checksum
MAC Address
TCP-IP
Source Stack data
MAC Address
 Offload features
Ethernet datagram management overview

• Ethernet datagram offload processing

Preamble & SFD Destination MAC (DA) Source MAC (DA) VLAN Eth Type Payload… CRC
1 2 3 4 5 6 7

1. Preamble and Start-of-Frame tag automatic insertion(Rx) or deletion (Tx)

2. Destination MAC address filtering
3. Source MAC address filtering
4. VLAN tag detection of received frame
5. Checks frame type and size (Rx) or Insert field (Tx)
6. Ethernet payload Checksum computation and insertion (Tx) or checking
(Rx) for:
• IPv4 header
• TCP/UDP/ICMP payload
7. Datagram CRC computation (Tx) and checking (Rx)

20
 Automatic CRC and pad generation 21

When the number of bytes received from the application falls below 60
(DA+SA+LT+Data),zeros are appended to the transmitting frame to make
the data length exactly 46 bytes to meet the minimum data field
requirement of IEEE 802.3.

2KB
MAC 802.3 External
RX FIFO PHY

DP@TDES0= 0
DC@TDES0=0
DA SA LT Data Preamble&SFD DA SA LT Data Pad CRC

<46bytes 46bytes
 Checksum Offload 22

• The Ethernet MAC implements checksum offload feature for

IPv4, ICMP, TCP and UDP protocols.
• Checksum offload engine supports:
• Checksum calculation and insertion for the transmit path.
• Error detection for the receive path.

• Checksum offload feature can be enabled only with Store-

and-Forward mode.
TDES1

Transmit:

Receive:

ETH_MACCR
 Implement in code(1/2) 24

• How to enable this feature

• Enable the receive checksum offload by setting the IPCO bit in the
ETH_MACCR register
• Enable checksum calculation and insertion when transmit by setting
CIC bits in TDES1
• Only one step needed to do: fill the initial parameters in
low_level_init()

• Dropping of TCP/IP checksum error frames?

by setting DTCEFD bit in the ETH_DMAOMR register.
Default dropping it.
 Implement in code(2/2) 25

• Check the status IP datapram header error

and payload error during
reception

IP datapram header error

and payload error during
transmission
 Precision Time Protocol (IEEE1588) : What is it
26

• It is a protocol designed to synchronize real-time clocks of

the devices of a network

• Synchronization is done with the most accurate clock

found in a packet-based network: called the Grand
Master Clock.

• Accuracy is
09:10
09:00 09:01
09:00

09:00
Grand
09:05
09:00 09:30
09:00
Master
Clock
09:00

26
 Precision Time Protocol (IEEE1588) : How it works 27
Comparing the transmission of messages

• From the master clock point of view

• From the slave clock point of view

Master Clock Slave Clock Master Clock Slave Clock
8 8
10 10
9 9
11 11
10 10
12 12
11 11
13 13

Propagation delay Clocks Offset

27
 Precision Time Protocol (IEEE1588) : How it works 28
Master Clock
8 Slave Clock
t1 10 Computation done PTP
by the slave
9
11
A = t2 - t1 = Delay + Offset
10 t1 A 12 B = t4 - t3 = Delay - Offset

11 Delay = (A + B)/2
t2 13 Offset = (A - B)/2
12
t4 14
13 This allow the Master
t3 B 15 and the slave to be
14 synchronized with a
t4
16 sub-µsecond precision
15
17
Propagation delay
16
Clocks Offset
28
 Precision Time Protocol : Time stamping 29

Time stamp is capture by hardware

• As soon as the reception is complete

• When the start of frame is output on the MII

Frames receive with PTP feature Frames transmit with PTP feature

The DMA returns the time The DMA returns the time
DMA stamp to the Application in the DMA stamp to the Application in the
RX descriptor TX descriptor

MAC The MAC captures the time MAC The MAC captures the time
stamp as soon as the frame stamp when the Tx Frame’s
PTP reception is complete PTP SFD is output on the MII
IEEE1588 IEEE1588

MII The MAC detects a MII

frame at MII level
Tx Frame
Rx Frame
 IEEE 1588
Precision Timing Protocol - PTP

• PTP Objective
• Synchronize all nodes in a local network area (LAN)
with very high accuracy (<1us) by use of HW time
stamping Master Synchronization Master
Time Ref Time Ref
• PTP protocol define synchronization messages
between nodes and routers.
Path1 Path2 Path1 Path2
delay1 delay2 delay1 delay2
• STM32F7 MAC features
PTP SYNC
• MAC is compliant with PTPv2 (IEEE1588-2008)
messages Slave1 Slave2 Slave1 Slave2
Time1 Time2 Time Ref Time Ref
• Accurate timing reference is based on hardware
counter
• 64 internal bits (32 bits for second and 32 bits for
nanosecond counter)
• Counter accuracy on HCLK is down to ~ 5 ns (@
200MHz)
• Export timing reference through output pulse-per-
second (PPS) signal
30
 Low-power modes 31

Mode Description

Run Active.

Sleep Active. Peripheral interrupts cause the device to exit Sleep mode.

The Ethernet peripheral is able to detect frames while the system is in the Stop
Stop
mode, provided that the EXTI line 19 is enabled.

Standby Powered-down. The peripheral must be reinitialized after exiting Standby mode.
 Power Management 32

Remote wakeup frame detection

• Power down mode state

• Application and Tx clock are switched-off
• PHY, MII interface and MAC Rx remain
active
MAC Rx
Full
Active
DMA/MTL
MAC Tx
MII PHY Network • All packets but wake-up ones are
dropped

Power
Off
MAC Rx
MII PHY Network
• Wake-up
Down Off
• Wake-up is controlled by the network
• Wake-up packets are
• AMD Magic packet
• User defined
• Wakeup frame detection is an event that
can wakeup the system from STOP mode
 Ethernet Block Diagram 33

DMA MAC PHY

Intereface
 Ethernet Block Diagram : FIFO & DMA 34

• The MAC core has two FIFOs, of 2KB each one, with a configurable
threshold.

• Two modes for popping data towards the MAC, for frames transmission &
for frames reception:

Dedicated DMA

2KB
AHB Master

Media
BusMatrix

RX FIFO
Interface

Ethernet Access Control

AHB Bus

DMA
2KB MAC 802.3
TX FIFO
 Ethernet Block Diagram : FIFO
35

• Two modes for popping data towards the MAC, for frames
transmission:
• Threshold mode: as soon as the threshold level is reached.
• Store-and-Forward mode: a complete frame is stored into the FIFO.

Ethernet 2KB External

SRAM MAC 802.3
DMA RX FIFO PHY

Threshold Threshold mode

DATA

DATA DATA

Transfer complete Store-and-Forward mode

DATA
DATA DATA
 Ethernet Block Diagram : FIFO
36

• Two modes for popping data towards the DMA, for frames reception:
• Cut-through mode: as soon as the threshold level is reached.

• Store-and-Forward mode: a complete frame is received into the FIFO.

Ethernet 2KB External

SRAM MAC 802.3
DMA RX FIFO PHY

Cut-through mode
Threshold DATA

DATA DATA

Store-and-Forward mode Transfer complete

DATA

DATA DATA
 Ethernet Block Diagram : FIFO 37

• Transmission
• TSF: Transmit store and forward
• TTC: Transmit threshold control
• ST: Start/stop transmission

• Reception
• RSF: Receive store and forward
• RTC: Receive threshold control
• SR: Start/stop receive

ETH_DMAOMR
 DMA Controller 38

• Independent DMA engines for transmit and receive.

• Round-robin or fixed-priority arbitration between transmit and receive
engines.
• Dual-buffer (ring) or linked-list (chained) descriptor chaining.
• Comprehensive status reporting for normal operation and transfers with
errors.
• Interrupt control for transmit and receive.

2KB
AHB Master

Media
AHB Bus

BusMatrix

RX FIFO
Interface

Ethernet Access Control

DMA
2KB MAC 802.3
TX FIFO
 DMA Controller: Descriptors structure (1/2) 39

• DMA transfers are managed by descriptors.

• Descriptors are configured by the user and located in the

SRAM.

• Multiple descriptors are prearranged in two structures:

• Ring structure.
• Chain structure.
 DMA Controller: Descriptors structure (1/2)
40
• Each descriptor is formed by four 32bit-words:
• TDES0 : Control and Status information.
• TDES1 : Counts.
• TDES2 : (First) Buffer address
• TDES3 : Ring mode: Second Buffer address.
Chain mode: Next Descriptor address.
Basic address of
transmit descriptor
ETH_DMATDLAR
Transmit
descriptor

Basic address of
receive descriptor
ETH_DMARDLAR

Receive
descriptor
 DMA Controller: Descriptors Structure (2/2) 41
Chain mode Ring mode

• Each descriptor points to one buffer. • Each descriptor can point to a maximum of
two buffers.
• Each descriptor include the next
descriptor address. • Configurable descriptor skip length

• hold the status of the transmitted or • The last descriptor point back to the first
received packet. entry.

=1 =0
TCH@TDES0
Single frame/ Multiple descriptors Chain mode
43
Bit28: First Segment : 1
Bit29: Last Segment : 0
Control / Status
First Buffer DMA
Buffers Count
Start of Frame
Buffer1 Address
Next Desc Address
… Bit28: First Segment : 0 First Buffer

Bit29: Last Segment : 0

Second Buffer
Control / Status
Second Buffer
DMA
Buffers Count
Last Buffer
Buffer1 Address

… Next Desc Address

Bit28: First Segment : 0 End of Frame
Bit29: Last Segment : 1

Control / Status
TX FIFO
Last Buffer
Buffers Count
DMA

Buffer1 Address
Next Desc Address

*Bit8/Bit9 used for Rx

SRAM
 Single frame/ Multiple descriptors Ring Mode
44

Bit28: First Segment : 1

Bit29: Last Segment : 0

Control / Status
First Buffer DMA Start of Frame
Buffers Count
Buffer1 Address
… DMA First Buffer
Buffer2 Address

Second Buffer Second Buffer

Descriptor
skip length Bit28: First Segment : 0
… Bit29: Last Segment : 1
Last Buffer

Last Buffer Control / Status

DMA End of Frame
Buffers Count
Buffer1 Address
TX FIFO
Buffer2 Address

SRAM
 DMA Descriptor Init 45

low_level_init

HAL_ETH_DMATxDescListInit

HAL_ETH_DMARxDescListInit

ethernetif.c

Set basic transmit

descriptor address
 Interrupts

• Ethernet MAC Interrupts are split in three

categories
• DMA Normal Interrupts
• Good transmission or reception
Normal • DMA Abnormal Interrupts
IT
• Rx FIFOs overflow
• Tx FIFO underflow
• Process stopped
• MAC Interrupts
• PMT: Set when a wakeup packet is received
• MMC: Set when there is a MMC counter event
• TST: Set when target time is reached
Abnormal
IT
• All interrupts can be masked

46
 Ethernet over STM32 Family
MCU Core Ethernet controller is compliant with the following standards

STM32F107 Cortex-M3 • IEEE 802.3-2002 for Ethernet MAC

• IEEE 1588-2002 standard for precision networked clock synchronization
• AMBA 2.0 for AHB Master/Slave ports
• RMII specification from RMII consortium

STM32F2 Cortex-M3 • IEEE 802.3-2002 for Ethernet MAC

• IEEE 1588-2008 standard for precision networked clock synchronization
• AMBA 2.0 for AHB Master/Slave ports
• RMII specification from RMII consortium

STM32F4 Cortex-M4 • IEEE 802.3-2002 for Ethernet MAC

• IEEE 1588-2008 standard for precision networked clock synchronization
• AMBA 2.0 for AHB Master/Slave ports
• RMII specification from RMII consortium

STM32F7 Cortex-M7 • IEEE 802.3-2002 for Ethernet MAC

• IEEE 1588-2008 standard for precision networked clock synchronization
• AMBA 2.0 for AHB Master/Slave ports
• RMII specification from RMII consortium

47
 Demo ST Provide 48

F107 F207/ F4x7/ F7*

F217 F4x9
LwIP_HTTP_Server_Netconn_RTOS Y Y Y
LwIP_HTTP_Server_Socket_RTOS Y Y Y
LwIP_HTTP_Server_Raw Y Y Y
LwIP_IAP Y Y Y
LwIP_StreamingServer Y
LwIP_TCP_Echo_Client Y Y Y Y
LwIP_TCP_Echo_Server Y Y Y Y
LwIP_TFTP_Server Y Y Y
LwIP_UDPTCP_Echo_Server_Netconn Y Y Y
_RTOS
LwIP_UDP_Echo_Client Y Y Y Y
LwIP_UDP_Echo_Server Y Y Y Y

*except WLCSP180 package

stm32f7xx_hal_eth.c Implement by code
——Ethernet Init
49

GPIO init HAL_ETH_MspInit, call from HAL_ETH_Init

MII or RMII
HAL_ETH_Init, call from low_level_init
selection

MAC and DMA

ETH_MACDMAConfig, call from HAL_ETH_Init
config

PHY init HAL_ETH_Init , call from low_level_init

Initialize Tx/Rx low_level_init, call from ethernetif_init

Descriptors list
 Two Rx Mode 50

Polling Mode
(Standalone)
Interrupt Mode
(RTOS)
 Polling Rx Mode 51

The ethernet_input() function implementation differs between

standalone and RTOS modes

Main() void ethernetif_input(struct netif *netif)

{ {
…… err_t err;
While(1) struct pbuf *p;
{
ethernetif_input(&gnetif); /* move received packet into a new pbuf */
…… p = low_level_input(netif);
}
} /* no packet could be read, silently ignore this */
if (p == NULL) return;

/* entry point to the LwIP stack */

err = netif->input(p, netif);

if (err != ERR_OK)
{
LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input
error\n"));
pbuf_free(p);
p = NULL;
}
}
 Interrupt Rx Mode 52

Packet received

void ETH_IRQHandler(void) void ethernetif_input( void const * argument )

{ {
ETHERNET_IRQHandler(); struct pbuf *p;
} struct netif *netif = (struct netif *) argument;

for( ;; )
{
if (osSemaphoreWait( s_xSemaphore,
TIME_WAITING_FOR_INPUT)==osOK)
{
do
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
{
{
p = low_level_input( netif );
osSemaphoreRelease(s_xSemaphore);
if (p != NULL)
}
{
if (netif->input( p, netif) != ERR_OK )
{
pbuf_free(p);
Release }
semaphore }
}while(p!=NULL);
}
}
}
Transmission Flow

53
Reception Flow

54
Thanks