This Study Resource Was: Using Signal and Sensitivity List

Using Signal and Sensitivity List
1. Objective(s):
The activity aims to demonstrate the procedures on how to simulate the
signal sensitivity statement in Model Sim.
2. Intended Learning Outcomes (ILOs):
The students shall be able to:
2.1 Test the step-by-step procedure in running the use of signal
statement VHDL codes to Model Sim.
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3. Discussion:
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ModelSim PE Student Edition is a free download of the industry-leading
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ModelSim HDL simulator for use by students in their academic coursework
(www.mentor.com).
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Figure 3.1. Model Sim Environment

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This application can be downloaded through the website but the license
must request individually by sending it to your email.
Signal Statement reversely said as input variable but, in this case, signals
serve the process of the architecture and were written between the
architecture and begin. The sensitivity list is inputs needed inside the
process of the architecture.
This study source was downloaded by 100000817485283 from CourseHero.com on 09-09-2021 02:23:32 GMT -05:00
https://www.coursehero.com/file/90446343/e-x-e-r-c-i-s-edocx/
4. Resources:
Computer System with internet access
Model Sim Installer capacity is 345MB while it needs 400MB space
memory to your OS drive
5. Procedure:
1. Install notepad++, must add the VHDL .dll plugins
2. Open the notepad++, create a new file
Copy the following codes:
entity T06_SignalTb is
end entity;
architecture sim of T06_SignalTb is

signal MySignal : integer :=0; --declarative region of the
VHDL code
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begin
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process is
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variable MyVariable: integer :=0; --a signal can only be
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declared a certain place within
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--the VHD file and this is between the architecture is tag and the begin.
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begin
report "***Process begin***";
MyVariable := MyVariable + 1;
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MySignal <= MySignal + 1; --is a signal that’s why it uses the

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arrow equal sign instead of colon equal

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report "MyVariable=" & integer 'image(MyVariable) & ",

MySignal=" & integer 'image(MySignal); -- this throw a report statement
so we can observe their value in the simulator
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Wait for 10 ns;

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MyVariable := MyVariable + 1;
MySignal <= MySignal + 1;
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report "MyVariable=" & integer 'image(MyVariable) & ",

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MySignal=" & integer 'image(MySignal);
Wait for 10 ns; --process iterate every 10 nanoseconds

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end process;
end architecture;
3. Change the file name by adding 6 to T06_SignalTb6 then save as
T06_SignalTb6.vhd
4. Open Model Sim
5. Open the created T06_SignalTb6.vhd existing file to the Model Sim
project.
6. Compile T06_SignalTb6 until the green check appears which means no
error.
8. Once there is no error after compiling the vhd file click simulate.
9. Collapse the work library and choose the T06_SignalTb6 file you just
simulated then click ok.
10. Since there are no declared signal go on and hit the run icon beside the
100 ns, you can see Fig. 5.1.
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Figure 5.1 Working Program

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Figure 5.2 Transcript Window
Learnings:
Notice that the program process iterates every 10 nanoseconds as
“wait for 10 ns” was written in VHDL codes. Also signal needs to drag
from the object area to the wave first column after clicking the simulate
button. Thus, the signal increments every 10 ns while printing the signal
value and “***Process begin***” while the variable is continuously
updated every report statement.
11. Try the next code using the sensitivity list
entity T09_SensitivityListTb is
end entity;
architecture sim of T09_SensitivityListTb is
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signal CountUp : integer :=0; --counter
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signal CountDown : integer :=10; --counter
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begin
process is
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begin rs e
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CountUp <= CountUp + 1; --increment the countup signal
CountDown <= CountDown - 1; --decrement the countdown signal
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wait for 10 ns; --remember no process can be left without the wait
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statement
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end process;
the process is -- process triggered using wait on

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begin
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if CountUp = CountDown then --the program will evaluated on

this part
report "Process A: Jackpot!";
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end if;
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wait on CountUp, CountDown; --but will pause until either of the

signals change and loop back to the evaluated process
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end process;
--equivalent process using sensitivity list

process (CountUp, CountDown) --write here the signals you want
the process to be sensitive
begin
if CountUp = CountDown then
report "Process B Jackpot!";
end if;
end process;
end architecture;
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Figure 5.3 While Loop Program

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Figure 5.4 Transcript of While Loop Program

Learnings:
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The code inside the process will be executed once, then the program
will wait at the beginning of the process until either of the two signals
change if the signals are equal the printout will appear but the process will
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always be triggered by changes to the signals listed in this sensitivity list.

The list process is now logically equivalent to the previous one and the
sensitivity list is equivalent to the process with the wait on the statement
at the end.
12. For Std_logic codes
library ieee;
use ieee.std_logic_1164.all;
entity T10_StdLogicTb is
end entity;
architecture sim of T10_StdLogicTb is

signal Signal1 : std_logic := '0'; --initial value of Signal1 is 0
signal Signal2 : std_logic;
signal Signal3 : std_logic;
begin
process is
begin
wait for 10 ns; --remember no process can be left without the wake
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statement
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Signal1 <= not Signal1;
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end process;
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end architecture;
13. The Output has U and there is no message in the transcript area.
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Figure 5.5 Output
Figure 5.6 Transcript of Std_logic codes
Learnings:
Notice that when you use std_logic the initial 0 value of the variable
Signal1 was enclosed with a single(‘’) quote. Table 1 represents the signal
wire status in the logic circuits. Also, when std_logic was used you need to
include the library IEEE; and use IEEE.std_logic_1164.all;
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Table 1. Meaning of each Std_Logic Signal
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14. Added codes for Std_logic codes after the end process;
Process is
begin
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Signal2 <= ‘Z’;

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Signal3 <= ‘0’;

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Wait;
End process;
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Figure 5.7 Output With High Impedance
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Figure 5.8 Transcript Window for High Impedance
6. Activity
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6.1 Create Exercise No. 5-1 by referring to step number 11 above.

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After running it without errors, paste the screenshot of the codes

and the Modelsim Waveform in the next row below. Differentiate
the codes “Using Signal” and the codes “Using Sensitivity List”.
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What makes it different? (This part is intended to submit in

Assignment 3.1 but you can submit the same document to
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the Assignment tasks)

6.2 Create Exercise No. 5-2 by referring to step number 12 above.
After running it without errors, paste the screenshot of the codes
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and the Modelsim Waveform in the next row below. Differentiate

the codes “Using Signal” and the codes “Using Std_logic”. What
makes it different? (This part is intended to submit in
Assignment 3.2 but you can submit the same document to
the Assignment tasks)
Questions:
Add another process that when the variable reaches to “1” it will
print “the device is on” from Activity 6.1 and run it, explain the
added process.
______________________________________________________________________
_____
______________________________________________________________________
_____
Add a loop statement that prints each bit from Activity 6.2 and run it,
explain the added process.
___________________________________________________________________________
VHDL codes (paste here the screenshot of the VHDL codes from answered
questions for Activity 6.1 and Activity 6.2)
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Output (paste here the screenshot of the output waveform of the edited
Activity 6.1 and Activity 6.2 coming from the questions)
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Conclusion:
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Assessment:
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Using Signal and Sensitivity List

Figure 3.1. Model Sim Environment

architecture sim of T06_SignalTb is

MySignal <= MySignal + 1; --is a signal that’s why it uses the

arrow equal sign instead of colon equal

report "MyVariable=" & integer 'image(MyVariable) & ",

Wait for 10 ns;

report "MyVariable=" & integer 'image(MyVariable) & ",

MySignal=" & integer 'image(MySignal);

Wait for 10 ns; --process iterate every 10 nanoseconds

Figure 5.1 Working Program

11. Try the next code using the sensitivity list

architecture sim of T09_SensitivityListTb is

the process is -- process triggered using wait on

if CountUp = CountDown then --the program will evaluated on

wait on CountUp, CountDown; --but will pause until either of the

--equivalent process using sensitivity list

Figure 5.3 While Loop Program

Figure 5.4 Transcript of While Loop Program

always be triggered by changes to the signals listed in this sensitivity list.

12. For Std_logic codes

architecture sim of T10_StdLogicTb is

Figure 5.5 Output

Signal2 <= ‘Z’;

Signal3 <= ‘0’;

Figure 5.8 Transcript Window for High Impedance

6.1 Create Exercise No. 5-1 by referring to step number 11 above.

After running it without errors, paste the screenshot of the codes

What makes it different? (This part is intended to submit in

the Assignment tasks)

and the Modelsim Waveform in the next row below. Differentiate

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