ECE 3544:

Digital Design I
1: TESTING IN MODELSIM
CH A PT E R 5 .1 – 5 .4 , 5. 7

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What you should know…
The fundamentals of Verilog structural modeling using primitive gates.

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What you might not know…
How to use Verilog models to simulate and test logic circuits.

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Disclaimers
While I make every effort to properly format the code that you see in class,
PowerPoint sometimes takes liberties with the formatting of the code sections
you will see in lecture during the semester.
As the course develops, you’ll receive coding guidelines. Follow those
guidelines; don’t blindly mimic what’s on the PowerPoint slides.
Not all of the code you will see is synthesizable! This is really important!

Synthesizable Not synthesizable!

SYN SYN

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Simulation: The Story So Far…
Your introduction to logic circuit design involved using Quartus to implement,
simulate, and test circuits.

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Simulation: The Story So Far…

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Simulation: The Story So Far…

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But What REALLY Happened?

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But What REALLY Happened?

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But What REALLY Happened?
Actually, there are two stories worth telling.
◦ The schematic was converted into a Verilog model.
◦ But the waveform was also converted into a Verilog model!

As your introduction to logic circuit design developed, you eventually cut out
the middle-man by writing Verilog models to describe a schematic.
In this course, we are going to do the same thing with simulation and testing.

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wire and reg Type
Generally speaking, a wire represents an internal connection between
devices.
Entities of wire type assume the value of some currently-driven element of
the system. A wire-type entity cannot store values – it is memoryless.
By default, inputs and outputs have wire type. However, an entity can be
declared as a wire without being an input or an output.

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wire and reg Type
Despite the name, a reg-type entity is not the same as a hardware register.
(Even though we will have to use reg-type entities to describe hardware
registers, we can also use them to describe combinational outputs.)
If an entity is the target of procedural code – that is, if a procedure assigns a
value to an entity – then the entity must be typed as a reg.
In practice, Verilog uses reg-type entities to describe variables. A reg-type
entity stores the value assigned to it until another value is assigned to it.

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wire and reg Type
As with other Verilog data types, a reg can be a scalar or a vector.
reg Declaration
◦ Scalar: reg q;
◦ Vector: reg [1:0] state;
reg [15:0] count;

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Processes in Verilog
Verilog treats a digital system as a set of independent, communicating
processes. A continuous assignment is a one-line process.
Verilog also has constructs for describing more complex processes using
sequential programming statements. These constructs are called procedures.
Procedures come in two kinds: the initial block and the always block.

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Procedures in Verilog
Code within procedures operate sequentially inside the block – that is,
between begin and end keywords.
However, all of the procedural blocks in a model operate concurrently with
each other. This is consistent with structural modeling and continuous
assignments

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The initial block
An initial block describes a procedure whose start corresponds to the start
of simulation time (t = 0) and whose statements proceed forward in simulation
time.
The statements in an initial block are executed once. (Loops do exist in Verilog,
but once a loop contained within some initial block has terminated, the
procedure doesn’t go back.)
In general, models represented by initial blocks are not synthesizable.
However, they are very useful for the purpose of applying stimulus values to
synthesizable models.

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Timing Control
Without any kind of timing control, all of the statements in a series of
assignments would be executed at the same simulation time – that is, during
the current time step.
◦ If this were to happen, a simulation could never move forward in time, as
an infinite series of statements could be performed in zero simulation time.
We have two ways to make a process or procedure take longer than zero time
to execute:
◦ Delay control: Delays an assignment by a specific amount of time. Delays
are not synthesizable, but are useful for modeling and testing
◦ Event control: Delays an assignment until a specific event or set of events
occurs. Event control is synthesizable if done with care.

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Delay Control
There are two ways to delay an assignment to a target variable.
In intra-assignment delay, we sample the right-hand side expression now and
then assign that value to left-hand side target at some later time.
◦ Example: out = #25 ~a;

In inter-assignment delay, we wait for some amount of time some before

sampling the RHS expression and immediately assigning it to the LHS target.
◦ Example: out = 1’b0;
#25 out = 1’b1;

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Test Benches
A test bench is a “data recorder circuit” whose purpose is to test other circuits.
The test bench itself is not a synthesizable circuit.

module tb_module();
(appropriate declaration of ports)
(instance of the module under test) SYN

initial begin
(initial values) SYN
(stimulus values)
end

endmodule

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Test Benches: Example
Test benches use inter-assignment
delay in initial blocks to simulate the
passage of time – again, relative to
the start of simulation time.
The timescale directive indicates the
amount of time that corresponds to
one time step (#1) and the smallest
unit of time that the simulation can
resolve.
(From here, let’s look at Modelsim!)
`timescale 1ns/1ns
SYN
module tb_adder1bit();
reg a, b, c_in;
wire sum, c_out;
adder1bit dut1(a, b, c_in, sum, c_out);
initial begin
{a, b, c_in} = 3’b000;
#20 {a, b, c_in} = 3’b001;
#20 {a, b, c_in} = 3’b010;
#20 {a, b, c_in} = 3’b011;
#20 {a, b, c_in} = 3’b100;
#20 {a, b, c_in} = 3’b101;
#20 {a, b, c_in} = 3’b110;
#20 {a, b, c_in} = 3’b111;
#20;
end
endmodule
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Simulation Using Modelsim

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Simulation Using Modelsim

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Simulation Using Modelsim

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Summary
In Verilog, procedures represent complex processes that are modeled by a
sequence of statements.
In any Verilog procedure, the target variable must be declared as a reg.
Verilog test benches are written as procedures using initial blocks. Even
though initial blocks are not generally synthesizable, we can use test
benches to provide stimulus values to synthesizable models.
You will receive more guidance in making and using test benches in a project-
level assignment whose purpose is to gain familiarity with the Modelsim tools.

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Coming Up Next…
Next topic
CMOS Logic Gates
Reading Assignment
Chapter 14: Sections 1 – 3, 4, 6.3

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