Advanced i-PVD Barrier Metal Deposition Technology for 90nm Cu Interconnects
K.-C. Park, I.-R. Kim, B.-S. Suh, S.-M. Choi, W.-S. Song, Y.-J. Wee, S.-G. Lee, J . 4 . Chung*,
J.-H. Chung*, S.-R. Hah*, J.-H. A h * * , K.-T. Lee**, H.-K. Kang, and K.-P. Suh
Advanced Process Development Project, System LSI Division, Samsung Electronics Co., Ltd.
San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do, KOREA 449-71 I
*Cu Group, System LSI Division, Samsung Electronics Co., Ltd.
**Technology Development Project, System LSI Division, Samsung Electronics Co., Ltd.
ABSTRACT
An advanced i-PVD(ionized physical vapor deposition)
barrier metal deposition technology has been developed for
90nm Cu interconnects. The feature of this technology is to
re-sputter the thick bamer metal at the contactitrench
bottom, which was deposited by i-PVD, and attach the re-
sputtered barrier metal to the sidewall. By using this
technology, it is possible to obtain relatively thin bottom
and thick sidewall coverage and thus a more conformal
deposition. This technology is shown to be very effective in
both lowering via resistance and improving reliabilities of
90nm Cu interconnects embedded in SiOC-type low-
k(kz2.9) inter-metal dielectric.
INTRODUCTION
Thin and continuous barrier metal is essential for the Cu
interconnects. The TaNiTa bi-layer deposited by ionized
physical vapor deposition(i-PVD) is being widely used for
this use in 130nm Cu interconnects. Its extendibility to
90nm Cu interconnects, however, is limited because of
insufficient sidewall coverage, irrespective of very high
bottom coverage. It is favorable, therefore, if we can re-
sputter some amount of material from the bottom and attach
the re-sputtered material to the sidewall.
We report this kind of barrier metal deposition
technology, named as advanced I-PVD(AiPVD). AiPVD
consists of two steps of deposition and re-sputtering, as
illustrated in Fig. I . The first step is to deposit the material
in an exactly same way as the i-PVD process. The second
step is to re-sputter the thick material at the contactitrench
bottom by applying a substrate bias power. In this step,
target DC power is also applied but reduced in order to
make the re-sputter rate higher than the deposition rate. The
re-sputtered material from the bottom is re-deposited to the
sidewall and thus the sidewall thickness is increased.
EXPERIMENTAL
Cu dual damascene structures with fluorosilicate glass
(FSG, kz3.7) and/or SiOC-type low-k(k=2.9) were used for
the evaluations of via chain resistance, thermal stability,
electro-migration (EM) and bias-thermal-stress (BTS)
reliability. The thermal stability was evaluated by
measuring the via resistance shift(VRS) after 400°C and 2
hours anneal. Cu EM and BTS tests were conducted at
around 280°C, 2 MAicm' and 35OoC, 0.8MVicm. The dual
damascene structures were observed by cross-sectional
TEM and EDAX was used for composition analysis during
TEM observation.
RESULTSAND
DISCUSSION
A . AiP VD Process Development
An example of barrier metal deposition profile of AiPVD
is shown in Fig. 2 as compared to that of I-PVD. Fig. 2
clearly shows that AiPVD results in relatively thin bottom
and thick sidewall coverage and thus a more conformal
deposition of barrier metal.
Fig. 3 shows the via chain resistance variation with the
re-sputtered thickness after TaNiTa deposition. The
resistance decrease with the re-sputtered thickness is due to
the decrease of the bamer metal thickness at via bottom.
Via resistance, however, does not further decrease when the
barrier material is fully removed from the bottom. This
saturated value of resistance was well matched with the
simulated value under the condition that no barrier metal
exists. TEM and EDAX analyses also identified the
formation of the Cu-to-Cu direct contact at the via-to-metal
interface.(Fig. 4)
In addition to the low via resistance, AiPVD process has
another advantage that a sputter clean prior to barrier metal
deposition does not have to be executed. This is because via
cleaning can be done by some amount of excessive re-
sputtering after barrier metal is completely removed. The
drawback of sputter pre-clean can be clearly seen in Fig. 5.
In the case that sputter pre-clean is performed, the re-
deposited Cu on via sidewall causes the poor adhesion and
thus leads to voids at the via bottom sidewall. Consequently.
this sputter clean prior to bamer metal deposition degrades
the thermal stability of via.(Fig. 6)
Although Cu-to-Cu direct contact via(DCV) structure can
give the lowest contact resistance, this structure may show
a serious problem when via is not fully overlapped on metal
layer. Because the barrier layer does not exist on non-
overlapped area, Cu may easily diffuse through this area. In
this sense, there should be some amount of barrier material
even at via bottom. Therefore, the barrier metal-should not
be fully removed by re-sputtering, or an additional Ta layer
needs to be deposited after DCV formation.
In the case of the partial re-sputtering of the barrier metal,
however, it should be cautious that the thermal stability of
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 via deteriorates if TaNiTa bi-layer is deposited and the re-
sputtering stops inside the TdN layer. In this case, Cu-TaN-
Cu contact is made at via bottom, which makes the thermal
stability worse than even the case that re-sputtering is not
involved.(Fig. 7) In order to avoid this detrimental situation,
therefore, TdN needs to be fully removed at the via bottom
in the case that TaN is used.
Considering the above discussions, four-step AiPVD
process seems to be favorable in the case that TaN is used.
The first and second step is to deposit TaN layer and fully
remove it from the via bottom, respectively. The third and
fourth step is to deposit Ta layer and partially re-sputter it.
Finally, in the case of the four-step AiPVD process, the
deposited and re-sputterd Ta thickness at the third and
fourth step were optimized in the 90nm Cu interconnect
with SiOC IMD. No sputter pre-clean was used in this case.
Fig. 8 shows the via resistance and its shift as a function of
the Ta thickness remaining at via bottom. It is easy to
understand that the via resistance is a function of the Ta
thickness at via bottom. However, it is unexpected that the
Yia resistance shift also depends on the Td thickness. This
indicates that the thermal stability is improved as the Ta
thickness decreases. As mentioned above, however, there
should be some amount of barrier metal at via bottom
which can prevent the Cu diffusion, considering the case
that the via is not fully overlapped on metal layer. Therefore,
it is concluded that the Td thickness should be minimized as
far as it can prevent the Cu diffusion.
CONCLUSION
An advanced barrier metal deposition technology, named
as AiPVD, was developed for 90nm Cu interconnects with
SiOC(k=2.9) IMD. It showed a perfect stacked via yield
and minimal via resistance shift after 400°C. 2hours anneal.
AiPVD process also showed a significantly improved BTS
reliability due to the thick barrier metal at the sidewall of
trench and via. Consequently, AiPVD process is expected
to be a strong candidate for below 90nm Cu interconnects
until a CVD or ALD barrier metal solution is supplied.
REFERENCES
(I) K . Ueno, M . Suzuki. A. Matsumoto. K . Motoyama. T. Tonegawa. N.
Ita, K. Anta. Y. Tsuchiya. T. Wake. A. Kuho. K . Sugai. N. Cda. H.
~~.~
Mivamoto.
, ~. Proc. IEDM. 26X20001.
and S . Saita.
( 2 ) K. Matoyama. J. Fagurt. 1. Katsuki. 6. Chung. T. Tonegawa and H .
Miyamoto. Prac. IITC. 268(2002).
(3) W.S. Song. C.S. Lee. K.C. Park, B.S. Suh. J.W. Kim, S.Y. Kim. Y.J.
-
Wee. S.M. Choi. H.-K. Kane. S.U. Kim, K.P. Suh. VLSl Technology .
.
Digest of Technical Papers 2002 Symposlum. ?22(?002)
Ta'

B. Pr0ce.s.s Integrufion ofAiP VD Fig. I Schematic diagram represenring the two-step AiPVD process
Two kinds of four-step AiPVD processes were applied to
MI-M4 integration with FSG IMD, as compared to the case
of TaN/Ta deposition by i-PVD. As shown in Fig. 9,
AiPVD processes show lower via resistances and better
distributions.(Cu-Td-Cu means the case that the Ta is
partially removed from the via bottom at the fourth step and
Cu-to-Cu means the case that the Ta is fully removed.)
AiPVD process was also successfully implemented to 90nm
Cu dual damascene interconnects with low-k(SiOC, kz2.9)
IMD. MI-to-M4 stacked via resistance and MC-to-M4
vertical structure were shown in Fig. IO, indicating the
Fig. 2. XTEM images showing barrier metal deposition profiles along
perfect stacked via yield and void-free Cu filling.
- TaNlTa 25nm was deposited by i-PVD while
0.2um via. In the left figure.
in the right figure some amount orre-sputtering was done after deposition.
C. EM and BTS Reliability Assessment
1.1, I
AiPVD did not show a big difference of electro-
migration(EM) resistance in the case that Ta remains at via
bottom, although the DCV structure showed an improved
performance, like other reports.( 1,2)
However, a great improvement of BTS lifetime was
found even with a small amount of re-sputtering, both in
line-to-line and via-to-via test structures.(Fig. I I) Details
about test structures are found in Ref. (3). These much 0.5 I I
longer failure times are explained as the thickness increase r& 1 6 2b
Re-sputtered ThickneWA)
of trencwvia sidewall, as seen in Fig. I , cures the defects Fig. 3. Via chain resistance with the resputtered lhickness. showing that
near the trench stop layer in the case of line and the CMP the via resistance does not further decrease when Cu-lo-Cu direct contact
canping layer in the case of via, respectively.(see Ref. 3) via is formd(0.2pm via, FSG IMD)

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 0 50 100 150 0 50 1W 150
Fig. 4. XTEM image showing the bottom of direct contact via.(left) EDAX Ta Thickress (A) Ta Ridmess (A)
analysis. performed at the whitesircled area of the left figure, does not
show any trace of Ta at that re@on.(right) Fig. 8. Chain via resistance with Ta thickness at via bottom and its shift
after anneal. showing that the via resistance shiti depends on the Ta
thicknessat via hottom.(O.l5pm via. S i x IMD)

Fig. 5. XTEM images showing the via bottoms. In the left figure. sputter 1 1.5 2 2.5 3 3.5
clean was done prior to barrier mctal deposition. while no prr-dean was Rc (cim&ia)
performed in the right figure. In the right, via cleaning was executed by an
excessive re-sputtering of via bottom after hanier metal is fully removed Fig. 9. Vial-3 stacked via resistance. Cu-to-Cu direct contact shows the
lowest resistance and best distributian.(O..?pm via. FSG IMD)

"-.I-
99.9
2 9 9
95

g 50 .
0 30'
2 15 aPreclean 0
4 5 ' 0Preelean X
5 1 ' +Preclean qhn)
0.1 ~ +Preclean X(Ann)
0.01 I I
0.4 0.5 0.60.7 0.8 0.9 1 1.1 1.2 2 3 4 5 6
Rc (ohmlvia) Rc ( o M a )
Fig. 6. Via resistance distribution of 0.2pm via chain before and after
400°C. .?hours anneal, showing that sputter clean prior to barrier metal Fig. 10. Vial-3 stacked via resistance and MC-trrM4 XTEM image..
deposition degrades thc thermal stability o f via. Single damascene was used at via3lM4 level.(O.lSpmvia. SiOC IMD)
99 I I 99, I

0 & +lh
100
0.1 1 10 100 1o(I 0.1 1 10 100 1000
Re-sputtered Thickness(A) Time(a.u.) Time(a.u )

Fig. 7. An example o f via resistance Shih with re-sputtered thickness aHer Fig. I I. Line-to-lindleft, 0.2pmlO.2pn) and via-to-via("ght. O..?pml
TaN/Ta bi-layer deposition. showing that an inappropriate re-spurrering 0.2," BTS test results. showing at least one order of magnitude
can cause a via resistance shifi due to the Cu-TaN-Cu contact formation. improvement of lifetime by AiPVD.

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