LESSON 7 – Logic Instructions

NEG Instruction – the NEG (Negate) instruction converts the specified operand to its 2’s complement
equivalent and the result returned to the operand location. This is, in effect, reversing the sign of an integer.
Format: NEG D
Action D 0 – [D]
Destination Example
register NEG AX
MM NEG byte ptr [BX]
Pointers:
1. Attempting to negate an operand having a value of zero causes no change to the operand and
resets the carry flag (CF = 0).
2. Attempting to negate an operand having a value of either 80H or 8000H causes no change to
the operand and sets the overflow flag (OF = 1).
3. Segment registers cannot be used as the destination operand. Therefore, the instruction NEG
CS is invalid.
4. If the destination operand is a memory location, the prefix byte ptr or word ptr should appear
after the NEG instruction to denote the data size of the destination operand.
Example:
Determine the value of AL and the value of the flags (assume all flags are initially 0) following
the instruction sequence:
MOV AL, 05H
NEG AL
AL contains:
0000 0000
- 0000 0101
1111 1011 = FBH = -5
The flags are affected as follows:
CF = AF = SF = 1 PF = ZF = OF = 0
CMP Instruction – the CMP (Compare) instruction subtracts the source operand from the destination operand.
It then discards the result but it updates the values of all the status flags.
Format: CMP D, S
Action: [D] – [S]

Destination Source Example

register register CMP BX.CX
register MM CMP CX, BETA
MM register CMP BETA, DX
register immediate CMP SI, ABCDH
MM immediate CMP byte ptr [BX], 34H
Pointers:
1. The CMP instruction does not allow both source and destination operands to be memory
locations (no memory to memory comparison). CMP [BX], BETA is invalid.
2. Both source and destination operands should be of the same data size. Therefore, the
instruction CMP AX, CL is invalid.
3. As with the MOV instruction, if the destination operand is a memory location and the
source operand is immediate data, the prefix byte ptr or word ptr should appear after the
CMP instruction to denote the data size of the immediate operand.
Example:
Perform the indicated operation. Each instruction is dependent of one another. Assume the
following register contents and assume that all flags are initially 0:
AX = 0015H BP = 0002H CS = 3000H
 BX = 0019H SP = 0035H DS = 2000H
CX = 0012H DI = 0017H SS = 2000H
DX = 001BH SI = 001EH ES = 4000H
CMP AX, BX
CMP [SI], DI
Answer:
CMP AX, BX
AX = 0015H 0000 0000 0001 0101
BX = 0019H 0000 0000 0001 1001
1111 1111 1111 1100
The result is discarded.
Flags: SF= 1 ZF = 0 PF = 1 CF = 1 AF = 1 OF = 0
CMP [SI], DI
First determine the operand located in the memory.
Physical Address = DS * 10H + SI
Physical Address = 20000H + 001EH
Physical Address = 2001EH
[2001EH] – 75H
[2001FH] – 89H
[SI] – 8975H 1000 1001 0111 0101
DI – 0017H 0000 0000 0001 0111
1000 1001 0101 1110
Flags: SF= 1 ZF = 0 PF = 1 CF = 0 AF =1 OF = 0
Program Tracing Example:
Trace the following program. Assume the following: all flags and registers (unless specified otherwise)
are initially zero, DS = 2000H, SS = 2001H, the label ALPHA = 001CH.
MOV AX, ALPHA
MOV SP, AX
ADD BX, AX
SUB BX, 9F79H
XCHG BX, BP
SBB AX, CX
ADC AX, 0029H
ADD AL, CL
DAA
NEG AX
LEA SI, ALPHA
MOV DX, [SI]
Solution:
1. The instruction MOV AX, ALPHA simple loads the contents of the memory location whose
offset is ALPHA to AX.
Physical Address = DS * 10H + ALPHA
= 2000H + 001CH
= 2001CH
Since [2001CH] = 18H and [2001DH] = 00H, the contents of AX will be 0018H. The flags are
not affected (all flags are still zero).
2. The instruction MOV SP, AX copies the contents of AX to SP, SP will therefore be equal to
0018H. Flags are not affected.
3. The instruction POP BX transfers the contents of the top of the stack to register BX.
Top of the Stack = SS * 10H + SP
= 20010H + 0018H
= 20028H
 Since [20028H] = 91H and [20029H] = 9FH, the contents of BX will be 9F91H. The new
contents of SP will be SP + 2 = 001AH. Flags are not affected.
4. The instruction ADD BX, AX adds the contents of BX to the contents of AX and stores the
results in BX.
AX = 0018H
+ BX = 9F91H
9FA9H
The new contents of BX will be 9FA9H. The Flags will be:
SF= 1 ZF = 0 PF = 1 CF = 0 AF =0 OF = 0
5. The instruction SUB BX, 9F79H will subtract 0020H from the contents of register BX.
BX = 9FA9H
- 9F79H
0030H
The new contents of BX will be 0030H. The Flags will be:
SF= 0 ZF = 0 PF = 1 CF = 0 AF =0 OF = 0
6. The instruction XCHG BX, BP will just exchange the contents of register BX and BP.
Since BP = 000H and BX = 0030H, the new contents will be BP = 0030H and BX = 000H. The
flags are not affected and will remain as (from previous instruction).
SF= 0 ZF = 0 PF = 1 CF = 0 AF =0 OF = 0
7. The instruction MOV CX, [BP] moves the contents of the memory location whose offset is
pointed to by BP to CX. Since BP is used, the SS register is addressed instead of DS.
Top of the Stack = SS * 10H + BP
= 20010H + 0030H
= 20040H
Since [20040H] = AEH and [20041H] = F3H, the new contents of CX will be F3AEH. The flags
are not affected and will remain as (from previous instruction).
SF= 0 ZF = 0 PF = 1 CF = 0 AF =0 OF = 0
8. The instruction SUB AX, CX will subtract the contents of CX and the carry flag from AX and
stores the results to AX.
AX = 0018H
- CX = F3AEH
- CF = 0
0C6AH
The new contents of AX will be 0C6AH. The Flags will be:
SF= 0 ZF = 0 PF = 1 CF = 0 AF =1 OF = 1
9. The instruction ADD AX, 0029H adds the contents of the hexadecimal number 0029H and
the carry flag to AX and stores the results to AX.
AX = 0C6AH
+ 0029H
+ CF = 1
0C94H
The new contents of AX will be 0C94H. The Flags will be:
SF= 0 ZF = 0 PF = 0 CF = 0 AF =1 OF = 0
10. The instruction ADD AL, CL will add the contents of AL to CL and stores the results in AL.
AL = 94H
+ CL = AEH
42H
The new contents of AL will be 42H. The Flags will be:
SF= 0 ZF = 0 PF = 1 CF = 1 AF =1 OF = 1
11. The instruction DAA means that the previous addition should be treated as a BCD
addition.
Since the result of the previous addition is an invalid BCD number (AF = 1), the DAA
instruction will adjust the result.
 AL = 42H
+ 06H
48H
The new contents of AL will be 48H. The Flags will be:
SF = 0 ZF = 0 PF = 1 CF = 0 AF =0 OF = X
12. The instruction NEG AX will simply perform 2’s complement on the contents of AX.
The content of AX is 0C48H. The two’s complement of 0C48H is F3B8H.
The new contents of AX will be F3B8H. The flags will be:
SF= 1 ZF = 0 PF = 1 CF = 0 AF =0 OF = 0
13. The instruction LEA SI, ALPHA will load the effective address or offset represented by the
label ALPHA to register SI.
Since ALPHA is 001CH, the new contents of SI will be 001CH.
The flags are not affected and will remain as (from previous instruction):
SF= 1 ZF = 0 PF = 1 CF = 0 AF =0 OF = 0
14. The instruction MOV DX, [SI] simply moves the contents of the memory location whose
offset is pointed to by SP to DX.
Physical Address = DS * 10H + SI
= 20000H + 001CH
= 2001CH
Since [2001CH] = 18H and [2001DH] = 00H, the contents of DX will be 0018H. The flags are
not affected and will remain as (from previous instruction):
SF= 1 ZF = 0 PF = 1 CF = 0 AF =0 OF = 0

Logic instructions include the logic operations AND, OR, XOR and NOT. Also included in this group is the TEST
instruction. The TEST instruction is somewhat similar to the CMP instruction where flags are modified but the
operands are not altered.

I. AND Instruction – the Logical AND instruction logically ANDs the source and the destination operands
and stores the result in the destination operand.
Format: AND D, S
Action: [D] + [S] D
Destination Source Example
register register AND BX, CX
register MM AND DX, [BP + SI]
MM register AND BETA, CX
register immediate AND BX, 0015H
MM immediate AND byte ptr BETA, 12H
Pointers:
1. The AND instruction does not allow both source and destination operands to be memory
locations (no memory to memory AND). Therefore, the instruction AND SET, FILE is invalid.
2. Both source and destination operands should be of the same data size. The instruction AND
AH, BX is therefore invalid.
3. The destination operand cannot be immediate data. Therefore, the instruction AND 1800H,
CX is invalid.
4. CP and OF are always 0 after execution while AF is undefined.
5. As with the MOV instruction, if the destination operand is a memory location and the source
operand is immediate data, the prefix byte ptr or word ptr should appear after the AND
instruction to denote the data size of the immediate operand.
6. The AND instruction can be used to clear out or zero out certain bits in a byte or word. In order
to do this, simply logically AND a bit mask pattern and the byte or word concerned. A bit mask
 pattern contains a pattern of 1’s and 0’s. A 0 in a bit position will cause that bit position to be
zeroed out, while a 1 in a bit position will not change the value.
Example:
MOV AL, 05H
MOV BL, FEH
AND AL, BL

AL = 05H
BL = FEH

AL = 0 0 0 0 0 1 0 1
BL = 1 1 1 1 1 1 1 0 (mask)
AL = 0 0 0 0 0 1 0 0

bit 0 is zeroed out, the rest of the bits remain the same.
Flags: CF, OF, PF, ZF, SF, are all equal to 0. AF is undefined.
II. OR Instruction – the Logical OR instruction logically ORs the source and the destination operands and
stores the result in the destination operand.
Format: OR D, S
Action: [D] + [S] D
Destination Source Example
register register OR BX, CX
register MM OR DX, [BP + SI]
MM register OR BETA, CX
register immediate OR BX, 0015H
MM immediate OR byte ptr BETA, 12H
Pointers:
1. The OR instruction does not allow both source and destination operands to be memory
locations (no memory to memory OR). OR SET, FILE is therefore invalid.
2. Both source and destination operands should be of the same data size. The instruction OR AH,
BX is therefore invalid.
3. The destination operand cannot be immediate data. Thus, the instruction OR 1800H, CX is
invalid.
4. CP and OF are always 0 after execution while AF is undefined.
5. As with the MOV instruction, if the destination operand is a memory location and the source
operand is immediate data, the prefix byte ptr or word ptr should appear after the OR
instruction to denote the data size of the immediate operand.
6. The OR instruction can be used to set a certain bit to 1 in a byte or word. In order to do this,
simply logically OR a bit mask pattern and the byte or word concerned. A bit mask pattern
contains a pattern of 1’s and 0’s. A 1 in a bit position will cause that bit position to be set to 1,
while a 0 in a bit position will not change the value.
Example:
MOV CL, 05H
MOV DL, 80H
OR CL, DL
CL = 0 0 0 0 0 1 0 1
DL = 1 0 0 0 0 0 0 0 (mask)
CL = 1 0 0 0 0 1 0 1

bit 7 is set to 1, the rest of the bits remain the same.

 Flags:
CF, OF, PF, and ZF are all equal to 0.
SF = 1 while AF is undefined.
III. XOR Instruction – the Logical XOR instruction logically XORs the source and the destination operands
and stores the result in the destination operand.
Format: XOR D, S
Action: [D] A [S] D
Destination Source Example
register register XOR BX, CX
register MM XOR DX, [BP + SI]
MM register XOR BETA, CX
register immediate XOR BX, 0015H
MM immediate XOR byte ptr BETA, 12H
Pointers:
1. The XOR instruction does not allow both source and destination operands to be memory
locations (no memory to memory XOR). XOR SET, FILE is therefore invalid.
2. Both source and destination operands should be of the same data size. The instruction XOR
AH, BX is therefore invalid.
3. The destination operand cannot be immediate data. Thus, the instruction XOR 1800H, CX is
invalid.
4. CP and OF are always 0 after execution while AF is undefined.
5. As with the MOV instruction, if the destination operand is a memory location and the source
operand is immediate data, the prefix byte ptr or word ptr should appear after the XOR
instruction to denote the data size of the immediate operand.
6. It is faster for the 8086/8088 to initialize a register to zero using the XOR instruction rather
than the MOV instruction. Since any value XORed to itself to zero, XOR AL, AL is faster to
execute than MOV al, 00H.
Example:
MOV AL, 15H
MOV BL, ABH
XOR AL, BL
AL = 0 0 0 1 0 1 0 1
BL = 1 0 1 0 1 0 1 1 (mask)
AL = 1 0 1 1 1 1 1 0
Flags:
CF, OF, and ZF are all equal to 0.
PF, SF = 1 while AF is undefined.

IV. NOT Instruction – the Logical NOT instruction performs a 1’s complement on the operand.
Format: NOT D
Action: [D] D
Destination Example
register NOT AX
MM NOT byte ptr BETA
Pointers:
1. The destination operand cannot be immediate data. Thus, the instruction NOT 1800H is
invalid.
2. Flags are not affected.
 3. If the destination operand is a memory location, the prefix byte ptr or word ptr should appear
after the NOT instruction to denote the data size of the immediate operand.
Example:
Perform the following operations. Each instruction is dependent on one another. Assume all
flags are initially 0:
MOV BX, D32BH
MOV CX, 1056H
NOT BX
NOT CH
Answer:
MOV BX, D32BH
MOV CX, 1056H
BX = D32BH
CX = 1056H
NOT BX
[BX] = D32BH = 1101 0011 0010 1011
[BX]’ = 0010 1100 1101 0100
NOT CH
[CH] = 20H = 0001 0000
[CH]’ = 1110 1111
V. TEST Instruction – the TEST instruction logically ANDs the source and the destination operands. The result
is discarded but the values of the status flags are updated.
Format: TEST D, S
Action: [D] x [S]
Pointers:
1. The TEST instruction does not allow both source and destination operands to be memory
locations (no memory to memory AND). TEST SET, FILE is therefore invalid.
2. Both source and destination operands should be of the same data size. The instruction TEST
AH, BX is therefore invalid.
3. CP and OF are always 0 after execution while AF is undefined.
4. As with the MOV instruction, if the destination operand is a memory location and the source
operand is immediate data, the prefix byte ptr or word ptr should appear after the TEST
instruction to denote the data size of the immediate operand.
Example:
Perform the following operations. Each instruction is dependent on one another. Assume all flags
are initially 0:
MOV SI, 2376H
MOV DI, 1941H
TEST SI, DI
Answer:
MOV SI, 2376H
MOV DI, 1941H
SI = 2376H
DI = 1941H
TEST SI, DI
[SI] – 0010 0011 0111 0110
[DI] – 0001 1001 0100 0001
0000 0001 0100 0000
Flags:
CF, OF, PF, SF and ZF are all equal to 0, while AF is undefined.
Logic Instruction Program Tracing Example:
Trace the following program. Assume the following: all flags and registers (unless specified otherwise)
are initially zero, DS = 2000H, SS = 2001H, the label ALPHA = 001CH.
MOV BX, ALPHA
MOV SP, BX
NEG BX
AND BX, [AX]
OR BX, 0020H
CMP BX, SP
MOV CX, [SP]
TEST BX, CX
NOT AX
XOR AL, CL
Solution:
1. The instruction MOV BX, ALPHA simple loads the contents of the memory location whose
offset is ALPHA to BX.
Physical Address = DS * 10H + ALPHA
= 200000H + 001CH
= 2001CH
Since [2001CH] = 18H and [2001DH] = 00H, the contents of BX will be 0018H. The flags are
not affected (all flags are still zero).
2. The instruction MOV SP, BX copies the contents of BX to SP, SP will therefore be equal to
0018H. Flags are not affected.
3. The instruction NEG BX will simply perform 2’s complement on the contents of BX.
The content of BX is 0018H. The two’s complement of 0018H is FFE8H.
The new contents of BX will be FFE8H. The Flags will be:
SF= 1 ZF = 0 PF = 1 CF = 0 AF =0 OF = 0
4. The instruction AND BX, [AX] logically ANDS the contents of BX to the contents of the
memory location specified by AX and stores the results in BX.
Physical Address = DS * 10H + AX
= 20000H + 0000H
= 20000CH
Since [20000H] = AAH and [20001H] = 12H, the operation is as follows:
BX = FFE8H = 1111 1111 1110 1000
[AX] = 12AAH = 0001 0010 1010 1010
0001 0010 1010 1000
The new contents of BX will be 12A8H. The Flags will be:
SF= 0 ZF = 0 PF = 0 CF = 0 AF =X OF = 0
5. The instruction OR BX, 0020H will logically OR 0020H from the contents of register BX.
BX = 12A8H
- 0020H
1288H
The new contents of BX will be 1288H. The Flags will be:
SF= 0 ZF = 0 PF = 0 CF = 0 AF =X OF = 0
6. The instruction CMP BX, SP will merely subtract the contents of SP from the destination,
BX and discard the results and update the flags.
BX = 12A8H
- SP = 0018H
1290H
The new contents of BX will be 1290H. The Flags will be:
SF= 0 ZF = 0 PF = 1 CF = 0 AF =0 OF = 0
7. The instruction MOV CX, [SP] moves the contents of the memory location whose offset is
pointed to by BP to CX. Since SP is used, the SS register is addressed instead of DS.
 Top of the Stack = SS * 10H + SP
= 20010H + 0018H
= 20028H
Since [20028H] = 91H and [20029H] = 9FH, the new contents of CX will be 9F91H. The flags
are not affected and will remain as (from previous instruction).
SF= 0 ZF = 0 PF = 1 CF = 0 AF =0 OF = 0
8. The instruction TEST BX, CX will logically ANDs the contents of CX from BX and discard the
results and update the flags.
BX = 12A8H = 0001 0010 1010 1000
(mask) CX = 9F91H = 1001 1111 1001 0001
0001 0010 1000 0000
The new contents of AX will be 0C6AH. The Flags will be:
SF= 0 ZF = 0 PF = 0 CF = 0 AF =X OF = 0
9. The instruction NOT AX performs 1’s complement on operand and stores the results to
AX.
AX = E11FH = 1110 0001 0001 1111
AX’ = 0001 1110 1110 0000
= 1EE0H
The new contents of AX will be 1EE0H. The Flags will be:
SF= 1 ZF = 0 PF = 0 CF = 0 AF =1 OF = 0
10. The instruction XOR AL, CL will logically XORs the contents of AL to CL and stores the
results in AL.
AL = E0H = 1110 0000
+ CL = 91H = 1001 0001
71H = 0111 0001
The new contents of AL will be 71H. The Flags will be:
SF= 0 ZF = 0 PF = 1 CF = 0 AF =X OF = 0