TABLE OF CONTENTS

Contents Page no.

CHAPTER 1 INTRODUCTION 03

1.1 OVERVIEW 03

1.1.1 Router Design Principle 04

1.2 PROBLEM DEFINITION 06

CHAPTER 2 LITERATURE REVIEW 08

CHAPTER 3 METHODOLOGY 13

3.1 ROUTER PACKET 13

3.1.1 Input Protocol 14

3.1.2 Output Protocol

3.2 ROUTER TOP LEVEL BLOCK 16

3.3 FIFO 17

3.4 SYNCHRONIZER 18

FSM 20
3.5
REGISTER 22
3.6

1
CHAPTER 4 VERIFICATION ENVIRONMENT 24

CHAPTER 5 SIMULATION RESULTS 26

5.1 FIFO 26

5.2 SYNCRONIZER 28

5.3 CONTROLLER 30

5.4 REGISTER 32

5.5 ROUTER TOP MODULE 35

CHAPTER 6 FUTURE WORK AND TIMELINE 37

7.1 FUTURE WORK 37

7.2 TIMELINE 38

CHAPTER 7 REFERENCES 39

2
 CHAPTER :1

INTRODUCTION

1.1 OVERVIEW

• Why Would We Need a Router?

For most home users, they may want to set-up a LAN (local Area Network) or

WLAN (wireless LAN) and connect all computers to the Internet without having to pay

a full broadband subscription service to their ISP for each computer on the network. In

many instances, an ISP will allow you to use a router and connect multiple computers

to a single Internet connection and pay a nominal fee for each additional computer

sharing the connection. This is when home users will want to look at smaller routers,

often called broadband routers that enable two or more computers to share an Internet

connection. Within a business or organization, you may need to connect multiple

computers to the Internet, but also want to connect multiple private networks not all

routers are created equal since their job will differ slightly from network to network.

Additionally, you may look at a piece of hardware and not even realize it is a router.

What defines a router is not its shape, color, size or manufacturer, but its job

function of routing data packets between computers. A cable modem, which routes data

between your PC and your ISP can be considered as a router. In its most basic form, a

router could simply be one of two computers running the Windows 98 (or higher)

operating system connected together using ICS (Internet Connection Sharing). In this

scenario, the computer that is connected to the Internet is acting as the router for the

second computer to obtain its Internet connection. Going a step up from ICS, we have a

3
 category of hardware routers that are used to perform the same basic task as ICS, albeit

with more features and functions often called broadband or Internet connection sharing

routers, these routers allow you to share one Internet connection with multiple

computers. Broadband or ICS routers will look a bit different depending on the

manufacturer or brand, but wired routers are generally a small box-shaped hardware

device with ports on the front or back into which you will plug each computer along

with a port to plug in your broadband modem. These connection ports allow the router

to do its job of routing the data packets between each of the computers and the data

going to and from the Internet. Depending on the type of modem and Internet

connection you have, you could also choose a router with phone or fax machine ports.

A wired Ethernet broadband router will typically have a built-in Ethernet switch to

allow for expansion. These routers also support NAT (network address translation),

which allows all of your computers to share a single IP address on the Internet. Internet

connection sharing routers will also provide users with much needed features such as

an SPI firewall or serve as a DHCP Server.

1.1.1 Router Design Principles

Given the strict contest deadline and the short implementation window we

adopted a set of design principles to spend the available time as efficiently as possible.

This document provides specifications for the Router is a packet based protocol. Router

drives the incoming packet which comes from the input port to output ports based on

the address contained in the packet. The router is a” Network Router” has a one input

port from which the packet enters. It has output ports where the packet is driven out.

Packet contains 3 parts. They are Header, data and frame check sequence. Packet width

is 8 bits and the length of the packet can be between 1 byte to 63 bytes. Packet header
4
contains three fields DA and length. Destination address (DA) of the packet is of 8 bits.

The switch drives the packet to respective ports based on this destination address of the

packets. Each output port has 8- bit unique port address. If the destination address of

the packet matches the port address, then switch drives the packet to the output port,

Length of the data is of 8 bits and from 0 to 63. Length is measured in terms of bytes.

Data should be in terms of bytes and can take anything. Frame check sequence contains

the security check of the packet. It is calculated over the header and data. The

communication on network on chip is carried out by means of router, so for

implementing better NOC, the router should be efficiently design. This router supports

four parallel connections at the same time. It uses store and forward type of flow

control and FSM Controller deterministic routing which improves the performance of

router. The switching mechanism used here is packet switching which is generally used

on network on chip. In packet switching the data the data transfers in the form of

packets between co-operating routers and Independent routing decision is taken. The

store and forward flow mechanism is best because it does not reserve channels and thus

does not lead to idle physical channels. The arbiter is of rotating priority scheme so that

every channel once get chance to transfer its data. In this router both input and output

buffering is used so that congestion can be avoided at both sides.

• Features

• Full duplex synchronous serial data transfer

• Variable length of transfer word up to 64 bytes.

• HEADER is the first data transfer.

• Rx and Tx on both rising or falling

• edge of serial clock independently

• 4 receivers select lines

5
 • Fully static synchronous design with

• one clock domain

• Technology independent VERILOG

• Fully synthesizable.

ROUTER is a Synchronous protocol. The clock signal is provided by the master

to provide synchronization. The clock signal controls when data can change and when

it is valid for reading. Since ROUTER is synchronous, it has a clock pulse along with

the data. RS-232 and other asynchronous protocols do not use a clock pulse, but the

data must be timed very accurately. Since ROUTER has a clock signal, the clock can

vary without disrupting the data. The data rate will simply change along with the

changes in the clock rate. As compared with its counterpart I2C, ROUTER is more

suited for data stream applications. Communication between IP’s

1.2 PROBLEM DEFINITION

The Three Port Router Design is done by using of the three blocks. The blocks

are 8-Bit Register, Router Controller and output block. The router controller is design

by using FSM design and the output block consists of four FIFO’s combined together.

The FIFO’s store data packets and when you want to send data that time the data will

read from the FIFO’s. In this router design has four outputs i.e. 8-Bit size and one 8-bit

data port. It is used to drive the data into router. we are using the global clock, reset

signals, error signal and suspended data signals are the output’s of the router. The FSM

controller gives the error and SUSPENDED_DATA_IN signals. These functions are

discussed clearly in below FSM description. The ROUTER can operate with a single

master device and with one or more slave devices. If a single slave device is used, the

6
RE (read enable) pin may be fixed to logic low if the slave permits it. Some slaves

require the falling edge (HIGH→LOW transition) of the slave select to initiate an

action such as the mobile operators, which starts conversion on said transition. With

multiple slave devices, an independent RE signal is required from the master for each

slave device

Comparison between OSI reference model and TCP/IP reference model

To verify the functionality and performance compliance of the design with

respect to specifications and ensure that designs are correct. Functionality verification

is done by giving different test cases to the design through constrained random

verification. Coverage driven verification is also performed to know how much of the

design has been exercised.

7
 CHAPTER 2

LITERATURE REVIEW

Routing is the process of moving a packet of data from source to destination

and enables messages to pass from one computer to another and eventually reach the

target machine. A router is a networking device that forwards data packets between

computer networks. It is connected to two or more data lines from different networks

(as opposed to a network switch, which connects data lines from one single network).

This paper, mainly emphasizes upon the study of router device, it’s top level

architecture, and how various sub-modules of router i.e. Register, FIFO, FSM and

Synchronizer are synthesized, and simulated and finally connected to its top module.

A router is a networking device that forwards data packets between computer

networks. A router is connected to two or more data lines from different networks (as

opposed to a network switch, which connects data lines from one single network).

When a data packet comes in on one of the lines, the router reads the address

information in the packet to determine its ultimate destination. Then, using information

in its routing table or routing policy, it directs the packet to the next network on its

journey. This creates an overlay internetwork. Routers perform the "traffic directing"

functions on the Internet. A data packet is typically forwarded from one router to

another through the networks that constitute the internetwork until it reaches its

destination node.

8
 A router is a device that forwards data packets along networks. It is connected

to at least two networks, commonly two LANs or WANs or a LAN and its ISP's

network and is located at gateways, the places where two or more networks connect. It

is an OSI layer 3 routing device. It drives an incoming packet to an output channel

based on the address fields contained in the packet header. Routers use headers and

forwarding tables to determine the best path for forwarding the packets, and they use

protocols to communicate with each other and configure the best route between any

two hosts.

Figure below, shows top level architecture of router, which include components

like FIFO, Register, synchronizer, FSM and input and output signals between them.

9
 Architecture of Router

System on chip is a complex interconnection of various functional elements. It

creates communication bottleneck in the gigabit communication due to its bus based

architecture. Thus there was need of system that explicit modularity and parallelism,

network on chip possess many such attractive properties and solve the problem of

communication bottleneck. It basically works on the idea of interconnection of cores

using on chip network. The communication on network on chip is carried out by means

of router, so for implementing better NOC, the router should be efficiently design. This

router supports four parallel connections at the same time. It uses store and forward

type of flow control and Fsm Controller deterministic routing which improves the

performance of router. The switching mechanism used here is packet switching which

is generally used on network on chip. In packet switching the data the data transfers in

10
the form of packets between cooperating routers and independent routing decision is

taken. The store and forward flow mechanism is best because it does not reserve

channels and thus does not lead to idle physical channels. The arbiter is of rotating

priority scheme so that every channel once get chance to transfer its data. In this router

both input and output buffering is used so that congestion can be avoided at both sides.

A router is a device that forwards data packets across computer networks.

Routers perform the data "traffic direction" functions on the Internet. A router is a

microprocessor-controlled device that is connected to two or more data lines from

different networks. When a data packet comes in on one of the lines. The router reads

the address information in the packet to determine its ultimate destination. Then, using

information in its routing table, it directs the packet to the next network on its journey.

The router is a ” Five Port Network Router” has a one input port from which the packet

enters. It has seven output ports where the packet is driven out. Packet contains 3 parts.

They are Header, data and frame check sequence. Packet width is 8 bits and the length

of the packet can be between 1 bytes to 64 bytes. Packet header contains three fields

DA and length. Destination address(DA) of the packet is of 8 bits. The switch drives

the packet to respective ports based on this destination address of the packets. Each

output port has 8-bit unique port address. If the destination address of the packet

matches the port address, then switch drives the packet to the output port, Length of the

data is of 8 bits and from 0 to 63. Length is measured in terms of bytes. Data should be

in terms of bytes and can take anything. Frame check sequence contains the security

check of the packet. It is calculated over the header and data.

11
 Router is a packet based protocol. Router drives the incoming packet which

comes from the input port to output ports based on the address contained in the packet.

The router has a one input port from which the packet enters. It has three output ports

where the packet is driven out. The router has an active low synchronous input resetn

which resets the router. Data packet moves in to the input channel of one port of router

by which it is forwarded to the output channel of other port. Each input channel and

output channel has its own decoding logic which increases the performance of the

router. Buffers are present at all ports to store the data temporarily. The buffering

method used here is store and forward. Control logic is present to make arbitration

decisions. Thus communication is established between input and output ports.

According to the destination path of data packet, control bit lines of FSM are set. The

movement of data from source to destination is called switching mechanism The packet

switching mechanism is used here, in which the flit size is 8 bits .Thus the packet size

varies from 0 bits to 8 bits. A detailed explanation of Design is as bellow Fig.1.

Block Diagram of Router

12
 CHAPTER 3

METHODOLOGY

3.1 Router packet:

Packet format: the packet consists of 3 parts: Header, payload and parity each of 8 bit

width and the length of the payload can be extended between 1 byte to 63 byte.

Figure 4: Packet format of a Router

Header: Packet header contain two fields DA and length.

DA: Destination Address of the packet is of 2 bits. The router drives the packet to the

respective ports based on this destination address of the packets.

Each output port has 2-bit unique port address. If the destination address of the

packet matches the port address, then router drives the packet to the output port. The

address ‘3’ is invalid.

Length: length of the data is of 6-bits. It specifies the number of the number of the data

bytes. A packet can have a minimum data size of 1 byte and a maximum size of 63

bytes.

13
 If length =1, it means data length is 1 byte If length =2, it means data length is 2

bytes

If length =63, it means data length is 63 bytes

Payload: payload is the data information. Data should be in terms of the bytes.

Parity: This field contains the security check of the packet. It is calculated as bitwise

parity over the header and payload bytes of the packet as mentioned below.

3.1.1 Router Input Protocol:

Figure 5: Router Input protocol

The characteristics of the DUT input protocols are as follows:

Testbench Notes: All input signals are active high except low reset and are

synchronized to the falling edge of the clock. This is because the DUT router is

sensitive to the rising edge of the clock. Therefore, in the testbench, driving input

signals on the falling edge ensures setup and hold time. But in the system

Verilog/UVM based testbench, clocking block can be used to drive the signals on the

positive edge of the clock itself and thus avoids metastability.

The packet_valid signal is asserted on the same clock edge when the header

byte driven onto the input data bus. Since the header byte contains the address, this the
14
router to which output channel the packet should be routed to (data_out_0, data_out_1,

data_out_2).

Each subsequent byte of payload after header byte should be driven on the input data

bus for every new falling edge of the clock. After the last payload byte has been

driven, on the next falling edge of the clock, the packet_valid signal must be de-

asserted, and the packet parity should be driven. This signals packet completion. The

testbench shouldn`t drive any byte when busy signal is detected instead it should hold

the last driven values.

• The `busy` signal when asserted drops any incoming byte of the data.

• The “err” signal is asserted when a packet parity mismatch is detected.

3.1.2 Router Output Protocol

Figure 6: Router Output Protocol

The characteristics of the output protocol are as follows:

Test bench Note: All output signals are active high and are synchronized to the

rising edge of the clock. Each output port data_out_X (data_out_0, data_out_1,

data_out_2) is internally buffered by a FIFO of size 16X9. The router asserts the

15
vld_out_X (vld_out_0, vld_out_!, vld_out_2) signal when valid data appears on the

vld_out_X(data_out_0,data_out_1,data_out_2) output bus. This is a signal to the

receiver’s client which indicates the data is available on a particular output data bus.

The packet receiver will then wait until it has enough space to hold the bytes of

the packet and then respond with the assertion of the read_enb_X

(read_enb_0.read_enb_1,read_enb_2) signal.

The read_enb_X(read_enb_0,read_enb_`1 or read_enb_2) input signal can be

asserted on the falling clock edge in which data are read from the

data_out_X(data_out_0,data_out_1,data_out_2)bus.

The read_enb_X(read_enb_0,read_out_1 or read_out_2) must be asserted

within 30 clock cycles of the vld_out_X(vld_out_0,vld_out_1,vld_out_2) being

asserted else time-out occurs, which resets the FIFO.

The data_out_X (data_out_0,data_out_1 or data_out_2) bus will be tri-

stated(high Z) during a scenario when a packet’s header byte is lost due to time-out

condition .

3.2 Router- Top Level block

The top level architecture of router is shown in the figure. The router module

consists of FSM, REGISTER, SYNCHRONIZER, FIFO_0, FIFO_1, FIFO_2.

During the course of the designing and implementing the whole module, we

design each sub-module one by one individually using RTL coding in Verilog and then

from the top we will instantiate all sub-module using structural style of modeling and

using some constructs of advance Verilog also.

16
3.3 Router : FIFO

Figure 6: Router FIFO

Functionality

There are 3 FIFOs used in the router design. Each FIFO is of 9 bits wide and 16

bit bytes depth. The FIFO works on the system clock and is reset with a synchronizer

active low reset.The FIFO is also internally reset by an internal reset signal soft_reset.

Soft_reset is an active high signal which is generated by the SYNCHRONIZER block

during time out state of the ROUTER.

If resetn is low then full=0, empty=1 and data_out=0.

The FIFO m/m size is 16X9. The extra bit in the data width is appended in

order to detect the header byte. Lfd_state detects the header byte of a packet. The 9th

bit is 1 for header byte and 0 for the remaining bytes.

Write Operation:

Signal data_in is sampled at the rising edge of the edge of the clock when

write_enb is high. Write operation only takes place when FIFO is not full in order to

avoid over_run condition.

Read operation:

17
The data is read from data_out at rising edge of the clock, when read_enb is high. Read

operation only takes place when the FIFO is not empty in order to avoid under run

condition.

During the read operation when a header byte is read, an internal counter is

loaded with the payload length of the packet plus ‘1’ (parity byte) and starts

decrementing every clock till it reached 0. The counter holds 0 till it is reloaded

back with a new packet payload length.

During the time out condition, full=0, empty=1. data out is driven to HIGH

impedance state under 2 scenarios:

When the fifo m/m is read completely (header+payload+parity).

Under the time out condition of the Router.

Full- FIFO status which indicates that all the locations inside FIFO have been

written.

Empty- FIFO status which indicates that all the locations of the FIFO have been

read and made empty.

Read and write operation can be done simultaneously.

3.4 Router : SYNCHRONIZER

Figure 7: Router Synchronizer

18
Functionality:

This module provides synchronization between router FSM and router FIFO

modules. It provides faithful communication between the single input port and three

output ports.

detect_add and data_in signals are used to select a FIFO till a packet routing is

over for the selected FIFO.

Signal fifo_full signal is asserted based on full_status of fifo_0 or FIFO_1 or

FIFO_2.

If data_in =2’b00 then fifo_full=full_0

If data_in=2’b01 then fifo_full=full_1

If data_in=2’b10 then fifo_full=full_2 else fifo_full=0

The signal vld_out_x signal is generated based on empty status of the FIFO as

shown below :

vld_out_0=~empty_0

vld_out_1=~empty_1

vld_out_2=~empty_2

The write_enb_reg signal is used to generate write_enb signal for the write

operation of the selected FIFO.

There are 3 internal reset signals (soft_reset_0, soft_reset_1, soft_reset_2) for

each of the FIFO respectively. The respective internal reset signals goes high if

read_enb_X (read_enb_0,read_out_1,read_out_2) is not asserted within 30 clock cycles

of the vld_out_X(vld_out_0,vld_out_1 or vld_out_2) being asserted respectively.

19
3.5 Router : FSM

Figure 8: Router FSM

STATE-DECODE_ADDRESS

This is the initial reset state.

Signal detect_add is asserted in this state which is used to detect an incoming

packet. It is also used to latch the first byte as a header byte.

STATE-LOAD_FIRST_DATA

Signal lfd_state is asserted in this state which is used to load the first data byte

to the FIFO.

Signal busy is also asserted in this state so that header byte that is already

latched doesn’t update to a new value for the current packet.

This state is changed to LAOD_DATA state unconditionally in the next clock

cycle.

STATE-LOAD_DATA

In this state the signal ld_state is asserted which is used to load the payload data

to the FIFO.

20
 Signal busy is de asserted in this state, so that ROUTER can receive the new

data from input source every clock cycle,

Signal write_enb_reg is asserted in this state in order to write the Packet

information(Header+Payload+Parity) to the selected FIFO.

This state transits to LAOD_PARITY state when pkt_valid goes low and to

FIFO_FULL_STATE when FIFO is full.

STATE-LOAD_PARITY

In this state the last byte is latched which is the parity byte.

It goes unconditionally to the state CHECK_PARITY_ERROR.

Signal busy is asserted so that ROUTER doesn’t accepts any new data.

write_enb_reg is made high for latching the parity byte to FIFO.

STATE-FIFO_FULL_STATE

busy signal is made high and write_enb_reg signal is made low.

Signal full_state is asserted which detects the FIFO full state.

STATE-LOAD_AFTER_FULL

In this state laf_state signal is asserted which is used to latch the data after

FIFO_FULL_STATE.

Signal busy & write_enb_reg is asserted.

It checks for parity_done signal and if it is high, shows that LOAD_PARITY

state has been detected and it goes to the state DECODE_ADDRESS.

If low_packet_valid is high it goes to LOAD_PARITY state otherwise it goes

back to the LOAD_DATA state.

STATE-WAIT_TILL_EMPTY

21
 Busy signal is made high and write_enb_reg signal is made low.

STATE-CHECK_PARITY_ERROR

In this state rst_int_reg signal is generated, which is used to reset

low_packet_valid signal. This state changes to DECODE_ADDRESS when FIFO is

not full and to FIFO_FULL_STATE when FIFO is full. Busy is asserted in this state.

3.6 ROUTER: Register

Figure 9: Router : Register

Functionality:

This module implements 4 internal registers in order to hold a header byte,

FIFO full state byte, internal parity and packet parity byte. All the registers in this

module are latched on the rising edge of the clock.

If resetn is low then the signals (dout,err,parity_done and low_pkt_valid) are

low.

The signal parity_done is high under the following conditions:

When signal ld_state is high and signals (fifo_full and pkt_valid) are low.

22
 When signals laf_state and low_pkt_valid both are high and the previous value

of parity_done is low.

rst_int_reg signal is used to reset low_pkt_valid signal.

detect_add signal is used to reset parity_done signal.

Signal low_pkt_valid is high when ld_state is high and pkt_valid is low.

Low_packet_valid shows that pkt_valid for current state has been deasserted.

First data byte i.e., header is latched inside an internal register when

detect_add and pkt_valid signals are high. This data is latched to the output dout

when lfd_state goes high.

Then signal data_in i.e. Payload is latched to dout if ld_state signal is high and

fifo_full is low.

Signal data_in is latched to an internal register when ld_state and fifo_full are

high. This data is latched to output dout when laf_state goes high.

Full_state is used to calculate internal parity.

Another internal register is used to store internal parity for parity matching.

Internal parity is calculated using the bit-wise xor operation between header byte,

payload byte and previous parity values as shown below:

parity_reg=parity_reg_previous^header_byte t1 clock cycle

parity_reg=parity_reg_previous^header_byte t1 clock cycle

parity_reg=parity_reg_previous^header_byte t1 clock cycle

parity_reg=parity_reg_previous^header_byte t1 clock cycle

Last payload byte

The err is calculated only after packet parity is loaded and goes high if the

packet parity doesn’t match with the internal parity.

23
 CHAPTER 4:

VERIFICATION ENVIRONMENT

A test bench helps us to verify the functionality of the design through

simulations. DUT in this environment stands for design under test and is the hardware

design written in Verilog or VHDL. If the design contains hundreds of signals it would

be difficult to connect, maintain and reuse the signals. Instead we can place all the

input output signals into a container which becomes interface to the DUT. The design

can be then driven through the values in the interface. The driver is the verification

component which will drive the inputs to the DUT through the interface. When the

driver has to drive some values to the design it will call the task written on the

interface. The generator is the verification component which can create valid data

transaction and can send to the driver. The driver can simply send the data provided to

it by the generator through interface. The DUT picks the input then process output data

and it will send to output pins. The monitor picks up the processed data, converts it into

a data object and sends it to the scoreboard. The Scoreboard can have a reference

model that behaves the same way as the DUT. This model reflects the expected

behaviour of the DUT. Input sent to the DUT is also sent to this reference model. So if

the DUT has a functional problem, then the output from the DUT will not match the

output from our reference model. So comparison of outputs from the design and the

reference model will tell us if there is a functional defect in the design. This is usually

done in the scoreboard.

The design can also be verified by comparing write and read transactions in the

scoreboard. The test bench architecture is as shown in the figure below:

24
Fig. 4.1: SV Test bench architecture.

25
 CHAPTER 5

SIMULATION RESULT

5.1 FIFO
SCHEMATIC

26
SIMULATION

27
5.2 SYNCHRONIZER
SCHEMATIC

28
SIMULATION

29
5.3 CONTROLLER

RTL

30
SCHEMATIC

SIMULATION

31
5.4 REGISTER

32
RTL

SCHEMATIC

SIMULATION

33
34
5.5 ROUTER TOP MODULE

RTL

SCHEMATIC

SIMULATION
35
36
 CHAPTER 7

FUTURE WORK AND TIMELINE

7.1 FUTURE WORK

• Completion of the System Verilog test bench verification environment which

involves development of monitor and scoreboard.

• Also, to perform Coverage driven verification.

2. Different test cases to demonstrate what it is supposed to do.

3. Waveforms and Simulation results associated with test cases.

4. Development of UVM test bench architecture.

7.2 TIMELINE

Table 7.1: Project Time Line

Project Flow Time Period

Study of System Verilog 6 Weeks (Oct 2020)

Architecture and Specifications of Alarm clock 2 Weeks (NOV 2020)

Design of Router 6 Weeks (DEC 2020)

Development of SV Test Bench Architecture 8 Weeks (JAN 2019)

Writing test cases, Running test cases, Debug and 2 Weeks (FEB 2021)
Bug fixes

Coverage driven verification 2 Weeks (APRIL 2021)

37
Study of UVM 6 Weeks (MAY 2021)

Development of UVM Test Bench Architecture 6 Weeks (JUNE 2021)

PERL AND ITS IMPLEMENTATION 4 Weeks (JULY 2020)

VERIFICATION OF DESIGN 4 Weeks (AUGUST 2021

Project report 5 Weeks ( SEPT 2021)

38
 CHAPTER 8

REFERENCES

1. ARM, AMBA AXI Protocol Specification (Rev 2.0). [Online]. Available at

http://www.arm.com, March 2010.

2. Babu Rajesh, Gowtham Prasad, Siva Prasad Reddy,(2012), “A Synthesizable

Design of AMBA-AXI Protocol for SoC Integration” International Journal of
Engineering Inventions ISSN: 2278-7461, Volume 1, Issue 3, PP: 19-26

3. Harsha Garua. (2016) “Verification Of Amba Axi Bus Protocol Implementing Incr
And Wrap Burst Using System Verilog.” International Journal of Research in
Engineering and Technology, vol. 05, no. 03, pp. 201–206.

4. Kanaka Maha Lakshmi, Manasa Lakshmi,(2016), “AMBA-AXI Protocol

Verification by using System Verilog”, International Research Journal of
Engineering and Technology (IRJET) ,Volume: 03 Issue: 08

5. Nikhil Gaikwad, Vijay.N.Patil, (2018) ,“Verification of AMBA AXI on-chip

Communication Protocol”,Fourth International Conference on Computing
Communication Control and Automation (ICCUBEA)

6. Ramagundam, S.; Dept. of Computer Sci., Troy Univ., Montgomery, AL, USA ;
Das, S.R. ; Morton, S. ; Biswas, S.N. ,(2014) “Design and implementation of high-
performance master/slave memory controller with microcontroller bus
architecture”, Instrumentation and Measurement Technology Conference
(I2MTC) Proceedings, 2014 IEEE International.

7. Renduchinthala H. ,H. S. S. Prasad, and Ch Santhi Rani. (2016) “Development of

VIP for AMBA AXI-4.0 Protocol.” Indian Journal of Science and Technology, vol. 9,
no. 48.

8. Spear, Chris. Systemverilog for Verification: a Guide to Learning the Testbench

Language Features, Springer.

39