CHAPTER -1

INTRODUCTION TO
MICROPROCESSORS
 Dr Manoj V.N.V.
 TEXT BOOKS
 Gilmore C., “Microprocessor – Principles
and Applications”, 2nd Edition, Tata
McGraw-Hill, 1994
 Huang H., “PIC Microcontroller: An
Textbooks
Introduction to Software and Hardware
Interfacing”, Thomson Delmar Learning,
2005

 Causey D., Mazidi M.A. and McKinlay R.D.,

“PIC Microcontroller and Embedded
Systems: Using Assembly and C for PIC18”,
Pearson Education, 2008
 Clements A. , “Microprocessor System
Reference Design”, 3rd Edition, PWS Publishing
Books Company, 1997
 Tabak D. , “Advanced Microprocessors”, 2nd
Edition, McGraw-Hill, 1995
 Hayes J. , “Digital System Design and Slide

Microprocessors”, McGraw-Hill 2
International, 1984
Dr. Manoj V.N.V.
 MICROPROCESSOR
 In the year 1969 the microprocessor was called the “Micro computer
chip” and this was named by Busicom. The term microprocessor was
developed until 1972.
 Webster
 Integrated circuit that contains the entire central processing unit of a computer
on a single chip.
 Chambers
 Microprocessor is a device that integrates the functions of the CPU in a
computer onto the IC or semiconductor chip
 Oxford Dictionary
 An integrated circuit that contains all the functions of a central processing unit of
a computer
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 MICROPROCESSOR-BASED SYSTEMS
 Central Processing Unit (CPU)
 Memory

 Input/Output (I/O) circuitry

 Buses
 Address bus
 Data bus
 Control bus

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MPU

CLK CPU Reg

CPU
Arithmetic
Register
Logic
Arrays
Unit Microprocessor-based System

Control Unit
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MICROPROCESSOR-BASED SYSTEM WITH BUSES: ADDRESS, DATA,
AND CONTROL

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 MICROPROCESSOR-BASED SYSTEMS
MICROPROCESSOR
 the “brains” of the computer
 its job is to fetch instructions, decode them, and then execute them
 8/16/32/etc –bit
 contains: Arithmet
Register
ic Logic
Arrays
Unit

Control Unit

 ALU performs computing tasks – manipulates the data/ performs

numerical and logical computations
 Registers are used for temp. storage
 Control unit is used for timing and other controlling functions – contains
a program counter (next instruction’s address and status register) Slide
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HISTORY OF MICROPROCESSORS
 TRANSISTORS
 Vacuum Tubes: A devise to control, modify,
and amplify electric signals
 Then can transistors
 Designed by John Bardeen, William Shockley, and
Walter Brattain, scientists at the Bell Telephone
Laboratories in Murray Hill, New Jersey - 1947
 In 1960 Jack Kilby and Robert Noyce designed
the first integrated circuit (IC)
 Fairchild company manufactured logic gates

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 INTEGRATED CIRCUITS
 Advances in manufacturing
allowed packing more transistors
on a single chip
 Transistors and Integrated Circuits
from SSI (Small-Scale Integration)
to ULSI
 Birth of a microprocessor and its
revolutionary impact

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 MICROPROCESSORS
 Noyce and Gordon Moore started
Intel
 Intel designed he first calculator

 Intel designed the first programmable

calculator
 Intel designed the first microprocessor
in 1971
 Model 4004
 4-bit; 2300 transistors, 640 bytes of
memory, 108 KHz clock speed

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 FIRST PROCESSORS
 Intel released the 8086, a 16-bit microprocessor, in 1978
 Motorola followed with the MC68000 as their 16-bit processor
 The 16-bit processor works with 16 bit words, rather than 8 bit words
 Instructions are executed faster
 Provide single instructions for more complex instructions such as multiply and
divide
 16 bit processors evolved into 32 bit processors
 Intel released the 80386

 Motorola released the MC68020

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 GENERATIONS OF COMPUTER
 Vacuum tube - 1946-1957
 Transistor - 1958-1964

 Small scale integration - 1965 on

 Up to 100 devices on a chip
 Medium scale integration - to 1971
 100-3,000 devices on a chip
 Large scale integration - 1971-1977
 3,000 - 100,000 devices on a chip
 Very large scale integration - 1978 -1991
 100,000 - 100,000,000 devices on a chip
 Ultra large scale integration – 1991 -
 Over 100,000,000 devices on a chip Slide
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 MOORE’S LAW

 Increased density of components on chip

 Gordon Moore – co-founder of Intel
 Number of transistors on a chip will double
every year
 Since 1970’s development has slowed a little
 Number of transistors doubles every 18 months
 Higher packing density means shorter
electrical paths, giving higher performance
 Smaller size gives increased flexibility
 Reduced power and cooling requirements
 Fewer interconnections increases reliability
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 NEW APPROACH – MULTIPLE CORES
 Multiple processors on single chip
 Large shared cache
 Within a processor, increase in performance proportional to square root
of increase in complexity
 If software can use multiple processors, doubling number of processors
almost doubles performance
 So, use two simpler processors on the chip rather than one more
complex processor
 With two processors, larger caches are justified
 Power consumption of memory logic less than processing logic
 Example: IBM POWER4
 Two cores based on PowerPC Slide
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POWER4 CHIP ORGANIZATION

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 INTEL MICROPROCESSORS EVOLUTION
 1971 - 4004  8086
 First microprocessor  much more powerful
 All CPU components on a single chip  16 bit
 The 4-bit 4004 ran at 108 kHz and  instruction cache, prefetch few
contained 2300 transistors instructions
 Followed in 1972 by 8008  8088 (8 bit external bus) used in
 8 bit first IBM PC
 Both designed for specific applications  80286
 8080  16 Mbyte memory addressable
 first general purpose microprocessor  up from 1Mb
 8 bit data path
 80386
 Used in first personal computer – Altair
 32 bit
 Support for multitasking
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 INTEL MICROPROCESSORS EVOLUTION
 80486
 sophisticated powerful cache and instruction pipelining
 built in maths co-processor

 Pentium
 Superscalar
 Multiple instructions executed in parallel

 Pentium Pro
 Increased superscalar organization
 Aggressive register renaming
 branch prediction
 data flow analysis
 speculative execution Slide
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 INTEL MICROPROCESSORS EVOLUTION
 Pentium II
 MMX technology
 graphics, video & audio processing

 Pentium III
 Additional floating point instructions for 3D graphics
 Pentium 4
 Further floating point and multimedia enhancements
 Itanium
 64 bit
 Itanium 2
 Hardware enhancements to increase speed
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 INTEL MICROPROCESSORS EVOLUTION
 Core
 First x86 with dual core
 Core 2
 64 bit architecture
 Core 2 Quad – 3GHz – 820 million transistors
 Four processors on chip
 x86 architecture dominant outside embedded systems
 Organization and technology changed dramatically

 Instruction set architecture evolved with backwards compatibility

 ~1 instruction per month added
 500 instructions available

 See Intel web pages for detailed information on processors Slide

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INTEL 40XX PROCESSORS

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INTEL 8008

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INTEL 8080

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INTEL 8085

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INTEL 8086

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INTEL 8088

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INTEL 80186 AND 80188

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INTEL 80286

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INTEL 80386

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INTEL 80486

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INTEL PENTIUM

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INTEL PENTIUM PRO

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INTEL PENTIUM II

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INTEL PENTIUM II XEON

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INTEL PENTIUM III

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INTEL PENTIUM IV

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INTEL DUAL CORE

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INTEL CORE 2 DUO

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INTEL CORE I7
 In 2009 Lynnfield and
Clarksfield models
cames
 Prior to 2010 all
models were quad core
 In 2010 Arrandale
(dual core) models
comes
 In 2010 Gulftown
models (extreme)
comes which has six
hyperthreaded cores

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 CORE I7 PROCESSOR TECHNOLOGIES:
 Intel Turbo Boost technology
 maximizes speed for demanding applications, dynamically accelerating
performance to match your workload—more performance when you need it
the most.²
 Intel Smart Cache
 provides a higher-performance, more efficient cache subsystem. Optimized for
industry leading multi-threaded games.
 Intel QuickPath Interconnect
 designed for increased bandwidth and low latency. It can achieve data transfer
speeds as high as 25.6 GB/sec with the Extreme Edition processor.
 Intel HD Boost
 significantly improves a broad range of multimedia and compute-intensive
applications. The 128-bit SSE instructions are issued at a throughput rate of one
per clock cycle, allowing a new level of processing efficiency with SSE4
optimized applications.
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INTEL CORE I5

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INTEL CORE I3

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 FEATURES OF NETBURST ARCHITECTURE
 Hyperthreading
 single processor appears to be two logical processor
 Each logical processor has its own set of register, APIC( Advanced programmable
interrupt controller)
 Increases resource utilization and improve performance.

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CORE I7 PROCESSORS

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LATEST CORE I7 PROCESSORS

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NEHALEM ARCHITECTURE

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 POWERPC
 1975, 801 minicomputer project (IBM) RISC
 Berkeley RISC I processor
 1986, IBM commercial RISC workstation product, RT PC.
 Not commercial success
 Many rivals with comparable or better performance
 1990, IBM RISC System/6000
 RISC-like superscalar machine
 POWER architecture
 IBM alliance with Motorola (68000 microprocessors), and Apple, (used 68000
in Macintosh)
 Result is PowerPC architecture
 Derived from the POWER architecture
 Superscalar RISC
 Apple Macintosh
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 POWERPC FAMILY
 601:
 Quickly to market. 32-bit machine
 603:
 Low-end desktop and portable
 32-bit
 Comparable performance with 601
 Lower cost and more efficient implementation
 604:
 Desktop and low-end servers
 32-bit machine
 Much more advanced superscalar design
 Greater performance
 620:
 High-end servers
 64-bit architecture
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 POWERPC FAMILY
 740/750:
 Also known as G3
 Two levels of cache on chip

 G4:
 Increases parallelism and internal speed
 G5:
 Improvements in parallelism and internal speed
 64-bit organization

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 INSTRUCTION EXECUTION RATE
 Millions of instructions per second (MIPS)
 Millions of floating point instructions per second (MFLOPS)

 Heavily dependent on instruction set, compiler design, processor

implementation, cache & memory hierarchy

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INSIDE THE CPU (MICROPROCESSOR)

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HOW THE CPU WORKS

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INTEL 8086 (X86) ARCHITECTURE AND
INSTRUCTION SET
 Advanced Microprocessors
 INTEL 8086 MICROPROCESSOR
 Key Features:
 Released by Intel in 1978
 Produced from 1978 to 1990s
 A 16-bit microprocessor chip.
 Max. CPU clock rate :
 5 MHz to 12 MHz
 Instruction set: x86-16
 Package: 40 pin DIP
 The 8086 gave rise to
 the x86 architecture of Intel's future processors.
 Common manufacturer(s): Intel, AMD, NEC, Fujitsu, Harris (Intersil), OKI,
Siemens AG, Texas Instruments, Mitsubishi.
 The Intel 8088, released in 1979, was a slightly modified chip with an
external 8-bit data bus and is notable as the processor used in the original IBM
PC. Slide
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 8086 CPU CHIP
 8086 CPU Chip in DIP Package Internal View

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A SAMPLE 8086 KIT

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INTEL 8086 DIP PIN LAYOUT

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8086 INTERNAL ARCHITECTURE

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REGISTERS OF THE 8086/80286

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GENERAL PURPOSE REGISTERS

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POINTER AND INDEX REGISTERS

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FETCH AND EXECUTION CYCLE

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ORIGIN AND DEFINITION OF A SEGMENT

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 MEMORY SEGMENTATION
 Example

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 LOGICAL AND PHYSICAL ADDRESS

CS 3 4 8 A 0 DS 1 2 3 4 0
IP + 4 2 1 4 DI + 0 0 2 2
Instruction address 3 8 A B 4 Data address 1 2 3 6 2

SS 5 0 0 0 0
SP + F F E 0
Stack address 5 F F E 0
Physical Address is some times referred as Effective Address
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SEGMENT REGISTER ASSIGNMENTS

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…FLAG(STATUS) REGISTER

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32-BIT PROGRAMMING MODEL OF X86 FAMILY

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EFLAGS

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 ADDRESSING MODES OF 8086
 Thus the addressing modes describe the types of operands and the way
they are accessed for executing an instruction.
 Immediate Addressing Mode
 Direct Addressing Mode
 Register Addressing Mode
 Register Indirect Addressing Mode
 Indexed Addressing Mode
 Register Relative
 Based Indexed
 Relative Based Indexed

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DIFFERENT WAYS OF ADDRESSING MEMORY

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CLASSIFICATION OF INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
 General-Purpose Byte or Word Transfer Instructions:
MOV Copy byte or word from specified source to specified destination.
PUSH Copy specified word to top of stack.
POP Copy word from top of stack to specified location.
XCHG Exchange bytes or exchange words.
XLAT Translate a byte in AL using a table in memory.
 Simple Input Output Port Transfer Instructions:
IN Copy a byte or word from specified port to accumulator.
OUT Copy a byte or word from accumulator to specified port.
 Special Address Transfer Instructions:
LEA Load effective address of operand into specified register.
LDS Load DS register and other specified register from memory.
LES Load ES register and other specified register from me
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 CLASSIFICATION OF INSTRUCTIONS
… DATA TRANSFER INSTRUCTIONS

 Flag Transfer Instructions:

LAHF Load (copy to) AH with the low byte of the flag register.
SAHF Store (copy) AH register to low byte of flag register.
PUSHF Copy flag register to top of stack.
POPF Copy word at top of stack to flag register.

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CLASSIFICATION OF INSTRUCTIONS
ARITHMETIC INSTRUCTIONS
 Addition Instructions:
ADD Add specified byte-to-byte or specified word to word.
ADC Add byte + byte + carry flag or word + word + carry flag.
INC Increment specified byte or specified word by 1.
AAA ASCII adjust after addition.
DAA Decimal (BCD) adjust after addition.
 Subtraction Instructions:
SUB Subtract byte from byte or word from word.
SBB Subtract byte and carry flag from byte or word and carry flag from word.
DEC Decrement specified byte or specified word by 1.
NEG Negate-Invert each bit of a specified byte or word and add 1
(form 2's complement).
CMP Compare two specified bytes or two specified words.
AAS ASCII adjust after subtraction.
DAS Decimal (BCD) adjust after subtraction.
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CLASSIFICATION OF INSTRUCTIONS
ARITHMETIC INSTRUCTIONS
 Multiplication Instructions:

MUL Multiply unsigned byte-by-byte or unsigned word by word.

IMUL Multiply signed byte by byte or signed word by word.
AAM ASCII adjust after multiplication.

 Division Instructions:
DIV Divide unsigned word by byte or unsigned double word by word.
IDIV Divide signed word by byte or signed double word by word.
AAD ASCII adjust before division.
CBW Fill upper byte of word with copies of sign bit of lower byte.
CWD Fill upper word of double word with sign bit of lower word.
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 CLASSIFICATION OF INSTRUCTIONS
BIT MANIPULATION INSTRUCTIONS
 Logical Instructions:

NOT Invert each bit of a byte or word.

AND AND each bit in a byte or word with the corresponding bit in another byte or word.
OR OR each bit in a byte or word with the corresponding bit in another byte or word.
XOR Exclusive OR each bit in a byte or word with the corresponding bit in another byte or word.
TEST AND operands to update flags, but don't change operands.

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 CLASSIFICATION OF INSTRUCTIONS
…BIT MANIPULATION INSTRUCTIONS

 Shift Instructions:
SHL/SAL Shift bits of word or byte left, put zero(s) in LSB(s).
SHR Shift bits of word or byte right, put zero(s) in MSB(s).
SAR Shift bits of word or byte right, copy old MSB into new MSB
 Rotate Instructions:
ROL Rotate bits of byte or word left, MSB to LSB and to CF.
ROR Rotate bits of byte or word right, LSB to MSB and to CF.
RCL Rotate bits of byte or word left, MSB to CF and CF to LSB.
RCR Rotate bits of byte or word right, LSB to CF and CF to MSB.

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 CLASSIFICATION OF INSTRUCTIONS
STRING INSTRUCTIONS
REP An instruction prefix. Repeat the following instruction until CX = 0.
REPE/REPZ An instruction prefix. Repeat instruction until CX = 0 or zero flag ZF ≠ 1.
REPNE/REPNZ An instruction prefix. Repeat until CX = 0 or ZF = 1.
MOVS/MOVSB/MOVSW Move byte or word from one string to another.

COMPS/COMPSB/COMPSW Compare two string bytes or two string words.

SCAS/SCASB/SCASW Scan a string. Compare a string byte with a byte
in AL or a string word with a word in AX.
LODS/LODSB/LODSW Load string byte into AL or string word into AX.
STOS/STOSB/STOSW Store byte from AL or word from AX into string.

Note: A ‘B’ in a mnemonic is used to specifically indicate that a string of bytes is to be acted upon. A ‘W’ in
Slide
the mnemonic is used to indicate that a string of words is to be acted upon.
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 CLASSIFICATION OF INSTRUCTIONS
PROGRAM EXECUTION TRANSFER INSTRUCTIONS

 Unconditional Transfer Instructions:

CALL Call a procedure (subprogram), save return address on stack.

RET Return from procedure to calling program.
JMP Go to specified address to get next instruction.

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CLASSIFICATION OF INSTRUCTIONS
…PROGRAM EXECUTION TRANSFER INSTRUCTIONS
 Conditional Transfer Instructions:
JA/JNBE Jump if above/jump if not below or equal.
JAE/JNB Jump if above or equal/jump if not below.
JB/JNAE Jump if below/jump if not above or equal.
JBE/JNA Jump if below or equal/jump if not above.
JC Jump if carry flag CF = 1.
JE/JZ Jump if equal/jump if zero flag ZF = 1.
JG/JNLE Jump if greater/jump if not less than or equal.
JGE/JNL Jump if greater than or equal/ Jump if not less than.
JL/JNGE Jump if less than/jump if not greater than or-equal.
JLE/JNG Jump if less than or equal/jump if not greater than.
JNC Jump if no carry (CF = 0).
JNE/JNZ Jump if not equal/jump if not zero (ZF = 0).
JNO Jump if no overflow (overflow flag OF = 0).
JNP/JPO Jump if not parity/jump if parity odd (PF = 0).
JNS Jump if not sign (sign flag SF= 0).
JO Jump if overflow flag OF = 1.
JP/JPE Jump if parity/jump if parity even (PF = 1). Slide

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 CLASSIFICATION OF INSTRUCTIONS
…PROGRAM EXECUTION TRANSFER INSTRUCTIONS

 Iteration Control Instructions:

LOOP Loop through a sequence of instructions until CX = 0.
LOOPE/LOOPZ Loop through a sequence of instructions while ZF =1 and CX ≠ 0.
LOOPNE/LOOPNZ Loop through a sequence of instructions while ZF = 0 and CX ≠ 0.
JCXZ Jump to specified address if CX = 0.

 Interrupt Instructions:

INT Interrupt program execution, call service procedure (ISR-Interrupt Service Routine).
INTO Interrupt program execution if OF = 1.
IRET Return from interrupt service procedure to main program.

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CLASSIFICATION OF INSTRUCTIONS
PROCESSOR CONTROL INSTRUCTIONS:
 Flag Set/clear Instructions:

STC Set carry flag CF to 1.

CLC Clear carry flag CF to 0.
CMC Complement the state of the carry flag CF.
STD Set direction flag DF to 1 (decrement string pointers).
CLD Clear direction flag DF to 0.
STI Set interrupt enable flag to 1 (enable INTR input).
CLI Clear interrupt enable flag to 0 (disable INTR input).

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CLASSIFICATION OF INSTRUCTIONS
…PROCESSOR CONTROL INSTRUCTIONS:
 External Hardware Synchronization Instructions:

HLT Halt (do nothing) until interrupt or reset.

WAIT Wait (do nothing) until signal on the TEST pin is low.
ESC Escape to external coprocessor such as 8087 or 8089
LOCK An instruction prefix. Prevents another processor from taking the bus
(in MAX mode)
 No Operation Instruction:

NOP No action except fetch and decode.

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 DETAILED DISCUSSION ON INSTRUCTIONS
(For Extensive Understanding of the Instructions)
Please note that the instruction study has to be done by the
students themselves as the time allocated is very short for the
lecture. Use the subsequent slides as a guide.
 MOV - COPY A WORD OR BYTE
MOV DESTINATION, SOURCE
MOV CX, 037AH Put the immediate number 037AH in CX
MOV BL, [437AH] Copy byte in DS at offset 437AH to BL
MOV AX, BX Copy contents of register BX to AX
MOV DL, [BX] Copy byte from memory at [BX] to DL.
MOV DS, BX Copy word from BX to DS register
MOV RESULTS[BP],AX Copy AX to two memory locations-AL to the first location, AH
to the second
EA of the first memory location is the sum of the displacement represented by RESULTS and
contents of BP. Physical address = EA + SS.
MOV CS:RESULTS[BP],AX Same as the above instruction, but physical address = EA + CS because
of the segment override prefix CS.

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 PUSH
PUSH SOURCE
PUSH BX Decrement SP by 2, copy BX to stack
PUSH DS Decrement SP by 2, copy DS to stack
PUSH AL Illegal, must push a word

PUSH TABLE [BX]

Decrement SP by 2, copy word from memory in DS at EA = TABLE + [BX] to stack

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 POP
POP DESTINATION
POP DX Copy a word from top of stack to DX Increment SP by 2
POP DS Copy a word from top of stack to DS Increment SP by 2
POP TABLE [BX] Copy a word from top of stack to memory in DS with EA = TABLE +[BX]
POP CS is illegal

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 XCHG
XCHG DESTINATION, SOURCE

EXAMPLES:

XCHG AX,DX Exchange word in AX with word in DX

XCHG BL,CH Exchange byte in BL with byte in CH
XCHG AL,PRICES [BX] Exchange byte in AL with byte in memory at
EA = PRICES [BX] in DS

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 XLAT/XLATB-TRANSLATE A BYTE IN AL
 Used to translate a byte from one code to another code. The instruction replaces a byte
in the AL register with a byte pointed to by BX in a lookup table in memory.
 Before the XLATB instruction can be executed, the lookup table containing the values for the
new code must be put in memory, and the offset of the starting address of the lookup table
must be loaded in BX.
 The code byte to be translated is put in AL. To point to the desired byte in the lookup table,
the XLATB instruction adds the byte in AL to the offset of the start of the table in BX. It then
copies the byte from the address pointed to by (BX + AL) back into AL.
 XLATB changes no flags.
 EXAMPLE:
8086 routine to convert ASCII code byte to EBCDIC equivalent.
ASCII code byte is in AL at start. EBCDIC code in AL at end.
MOV BX,OFFSET EBCDIC_TABLE
Point BX at start of EBCDIC table in DS
XLATB Replace ASCII in AL with EBCDIC from table

The XLATB instruction can be used to convert any code of 8 bits or less to any other code of 8
bits or less.
Slide
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 IN-COPY DATA FROM A PORT
IN ACCUMULATOR AL OR AX, PORT
IN AL, 0C8H Input a byte from port 0C8H to AL
IN AX,34H Input a word from port 34H to AX
A_TO_D EQU 4AH
IN AX,A_TO_D Input a word from port 4AH to AX

For the variable-port-type IN instruction, the port address is loaded into the DX
register before the IN instruction. Since DX is a 16-bit register, the port address can
be any number between 0000H and FFFFH. Therefore, up to 65,536 ports are
addressable in this mode.

MOV DX, 0FF78H Initialize DX to point to port

IN AL, DX Input a byte from 8-bit port 0FF78H to AL Slide

IN AX, DX Input a word from 16-bit port 0FF78H to AX 90

Dr. Manoj V.N.V.

 OUT-OUTPUT A BYTE OR WORD TO A PORT
OUT PORT, ACCUMULATOR AL OR AX
OUT 3BH,AL Copy the contents of AL to port 3BH
OUT 2CH,AX Copy the contents of AX to port 2CH
 For the variable-port form of the OUT instruction, the contents of AL or AX will
be copied to the port at an address contained in DX
 Therefore, the DX register must always be loaded with the desired port address
before this form of the OUT instruction is used
 The advantage of the variable-port form of addressing is described in the
discussion of the IN instruction
 The OUT instruction does not affect any flags.

MOV DX, 0FFF8H Load desired port address in DX

OUT DX, AL Copy contents of AL to port FFF8H
OUT DX, AX Copy contents of AX to port FFF8H
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 LEA-LOAD EFFECTIVE ADDRESS
LEA REGISTER, SOURCE

LEA BX, PRICES Load BX with offset of PRICES in DS

LEA BP, SS: STACK_TOP Load BP with offset of STACK_TOP in SS
LEA CX, [BX][DI] Load CX with EA = (BX) + (DI)

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 LDS-LOAD REGISTER AND DS WITH WORDS FROM MEMORY
LDS REGISTER, MEMORY ADDRESS OF FIRST WORD
 This instruction copies a word from two memory locations into the register
specified in the instruction.
 It then copies a word from the next two memory locations into the DS register.
 LDS is useful for pointing SI and DS at the start of a string before using one of
the string instructions, LDS affects no flags.

LDS BX, [4326] Copy contents of memory at displacement 4326H in DS to BL,

contents of 4327H to BH. Copy contents at displacement of 4328H
and 4329H in DS to DS register.
LDS SI, STRING_POINTER
Copy contents of memory at displacements STRING_POINTER and
STRING_POINTER+1 in DS to SI register. Copy contents of memory at
displacements STRING_POINTER+2 and STRING POINTER+3 In DS to Slide

DS register. DS:SI now points at start of desired string. 93

Dr. Manoj V.N.V.

 LES-LOAD REGISTER AND ES WITH WORDS FROM MEMORY
LES REGISTER, MEMORY ADDRESS OF FIRST WORD
 This instruction loads new values into the specified register and into the
ES register from four successive memory locations.
 The word from the first two memory locations is copied into the
specified register, and the word from the next two memory locations is
copied into the ES register.
 LES can be used to point DI and ES at the start of a string before a string
instruction is executed. LES affects no flags.
LES BX, [789AH] Contents of memory at displacements 789AH and
789BH In DS copied to BX
Contents of memory at displacements 789CH and 789DH in DS copied to ES
register. LES DI, [BX]
Copy contents of memory at offset [BX] and offset [BX+1] in DS to DI register
Copy contents of memory at offsets [BX + 2] and [BX + 3] to ES register.
Slide
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 LAHF-COPY LOW BYTE OF FLAG REGISTER TO AH
 The lower byte of the 8086 flag register is the same as the flag byte for
the 8085.
 LAHF copies these 8085 equivalent flags to the AH register. They can
then be pushed onto the stack along with AL by a PUSH AX instruction.
 An LAHF instruction followed by a PUSH AX instruction has the same
effect as the 8085 PUSH PSW instruction.
 The LAHF instruction was included in the 8086 instruction set so that the
8085 PUSH PSW instruction could easily be simulated on an 8086.
 LAHF changes no flags.

Slide
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 SAHF-COPY AH REGISTER TO LOW BYTE OF FLAG
REGISTER
 The lower byte of the 8086 flag register corresponds exactly to the
8085 flag byte.
 SAHF replaces this 8085 equivalent flag byte with a byte from the AH
register.
 SAHF is used with the POP AX instruction to simulate the 8085 POP
PSW instruction.
 As described under the heading LAHF, an 8085 PUSH PSW instruction
will be translated to an LAHF--PUSH AX sequence to run on an 8086.
 An 8085 POP PSW instruction will be translated to a POP AX--SAHF
sequence to run on an 8086.
 SAHF changes the flags in the lower byte of the flag register.

Slide
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 PUSHF AND POPF

 PUSHF-Push Flag Register on the Stack

 This instruction decrements the stack pointer by 2 and copies the word In the
flag register to the memory locations pointed to by the stack pointer.
 The stack segment register is not affected. No flags are changed.

 POPF-Pop Word from Top of Stack to Flag Register

 This instruction copies a word from the two memory locations at the top of the
stack to the flag register and increments the stack pointer by 2.
 The stack segment register and the word on the stack are not affected. AU flags
are affected.

Slide
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 ADC-ADD WITH CARRY- ADC DESTINATION, SOURCE
ADD- ADD DESTINATION, SOURCE
ADD AL, 74H Add immediate number 74H to contents of AL. Result In AL
ADC CL, BL Add contents of BL plus carry status to contents of CL.
ADD DX, BX Add contents of BX to contents of DX
ADD DX,[SI] Add word from memory at offset [SI]in DS to contents of DX
ADC AL, PRICES [BX] Add byte from effective address PRICES [BX] plus carry status to
contents of AL
ADD PRICES [BX], AL Add contents of AL to contents of memory location at effective
address PRICES[BX]

Slide
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 INC-INCREMENT-
INC DESTINATION
 INC BL Add 1 to contents of BL register
 INC CX Add1to contents of CX register
 INC BYTE PTR [ BX]
 Increment byte in data segment at offset contained in BX. The BYTE PTR directive is necessary to tell the
assembler to put in the right code to indicate that a byte in memory, rather than a word, is to be
incremented. The instruction essentially says, "Increment the byte pointed to by the contents of BX."
 INC WORD PTR [BX]
 Increment the word at offset of [BX] and [BX + 1] in the data segment. In other words, increment the
word in memory pointed to by BX.
 INC MAX_TEMPERATURE
 Increment byte or word named MAX-TEMPERATURE in data segment. Increment byte if
MAX_TEMPERATURE declared with DB. Increment word if MAX-TEMPERATURE declared with DW.
 INC PRICES [BX]
 Increment element pointed to by [BX] in array PRICES. Increment a word if PRICES was defined as an
array of words with a DW directive. Increment a byte if PRICES was defined as an array of bytes with a
DB directive.
 NOTE: The PTR operator is not needed in the last two examples because the assembler
knows the type of the operand from the DB or DW used to declare the named data initially.
Slide
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 AAA-ASCII ADJUST FOR ADDITION
 Numerical data coming into a computer from a terminal is usually in ASCII
code.
 The 8086 allows us to add the ASCII codes for two decimal digits without
masking off the "3" in the upper nibble of each.
 After the addition, the AAA Instruction is used to make sure the result is the
correct unpacked BCD; A simple numerical example will show how this works.
EXAMPLE:
Assume AL = 0 0 1 1 0 1 0 1, ASCII 5
BL = 0 0 1 1 1 0 0 1, ASCII 9
ADD AL,BL Result: AL= 0 1 1 0 1 1 1 0 = 6EH,which is incorrect BCD
AAA Now AL = 00000100, unpacked BCD 4.
CF = 1 indicates answer is 14 decimal
The AAA instruction works only on the AL register. The AAA instruction updates
AF and CF, but OF, PF, SF, and ZF are left undefined. Slide
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 DAA-DECIMAL ADJUST AL AFTER BCD ADDITION
 This instruction is used to make sure the result of adding two packed BCD
numbers is adjusted to be a legal BCD number.

AL = 0101 1001 = 59 BCD

BL = 0011 0101 = 35 BCD
ADD AL, BL AL = 1000 1110 = 8EH
DAA Add 01 10 because 1110 > 9 AL = 1001 0100 = 94 BCD
AL = 1000 1000 = 88 BCD
BL = 0100 1001 = 49 BCD
ADD AL, BL AL = 1101 0001, AF=1
DAA Add 0110 because AF =1, AL = 11101 0111 = D7H
1101 > 9 so add 0110 0000
AL = 0011 0111= 37 BCD, CF =1
Slide
101
The DAA instruction updates AF, CF, PF, and ZF. OF is undefined after a DAA instruction.
Dr. Manoj V.N.V.
 SBB-SUBTRACT WITH BORROW SBB DESTINATION, SOURCE
SUB-SUBTRACT SUB DESTINATION, SOURCE
SUB CX, BX CX - BX. Result in CX
SBB CH, AL Subtract contents of AL and contents of CF from
contents of CH. Result In CH
SUB AX,3427H Subtract immediate number 3427H from AX
SBB BX,[3427H] Subtract word at displacement 3427H in DS and
contents of CF from BX
SUB PRICES[BX], 04H Subtract 04 from byte at effective address PRICES [BX] if
PRICES declared with DB. Subtract 04 from word at
effective address PRICES [BX] if PRICES declared with DW.
SBB CX, TABLE[BX] Subtract word from effective address TABLE [BX]
and status of CF from CX.
SBB TABLE[BX], CX Subtract CX and status of CF from word in Slide

 memory at effective address TABLE[BX]. 102

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 DEC-DECREMENT DESTINATION REGISTER OR MEMORY-
DEC DESTINATION
 This Instruction subtracts 1 from the destination word or byte

DEC CL Subtract 1 from contents of CL register

DEC BP Subtract 1 from contents of BP register
DEC BYTE PTR [BX] Subtract 1 from byte at offset [BX]in DS.
DEC WORD PTR [BP] Subtract 1 from a word at offset [BP] in SS.
DEC TOMATO_CAN_COUNT Subtract 1 from byte or word named
TOMATO_CAN_COUNT in DS
If TOMATO_CAN_COUNT was declared with a DB, then the assembler
will code this instruction to decrement a byte. If TOMATO-CAN-COUNT
was declared with a DW, then the assembler will code this instruction to
decrement a word. Slide
103

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 NEG-FORM 2'S COMPLEMENT
NEG DESTINATION
 This Instruction replaces the number in a destination with the 2's
complement of that number.

NEG AL Replace number in AL with its 2's complement

NEG BX
NEG BYTE PTR [BX]
NEG WORD PTR [BP]
Replace word in BX with its 2's complement
Replace byte at offset [BX] in DS with its 2's
complement
Replace word at offset [BP] in SS with its 2's
complement

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 CMP-COMPARE BYTE OR WORD
CMP DESTINATION, SOURCE
 This instruction compares a byte from the specified source with a byte
from the specified destination, or a word from the specified source with
a word from the specified destination.
 The comparison is actually done by subtracting the source byte or word
from the destination byte or word.
 The source and the destination are not changed, but the flags are set to
indicate the results of the comparison.
AF, OF, SF, ZF, PF, and CF are updated by the CMP instruction.
CMP CX, BX CF, ZF, and SF will be left as follows:
CF ZF SF
CX = BX 0 1 0 Result of subtraction is 0
CX > BX 0 0 0 No borrow required, so CF = 0
CX < BX 1 0 1 Subtraction required borrow, so CF = 1 Slide
105

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 … CMP DESTINATION, SOURCE
CMP AL, 01H Compare immediate number01H with byte In AL
CMP BH, CL Compare byte in CL with byte in BH
CMP CX, TEMP_MIN
Compare word in DS at displacement TEMP_MIN with word in CX
CMP TEMP-MAX, CX
Compare CX with word in DS at displacement TEMP-MAX
CMP PRICES [BX], 49H
Compare immediate 49H with byte at offset [BX] in array PRICES

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 AAS--ASCII ADJUST FOR SUBTRACTION
 The 8086 allows us to subtract the ASCII codes for two decimal digits without masking
the "3" in the upper nibble of each.
 The AAS instruction is then used to make sure the result is the correct unpacked BCD.
ASCII 9-ASCII 5 (9-5)
AL = 00111001 = 39H = ASCII 9
BL = 001 10101 = 35H = ASCII 5
SUB AL, BL Result: AL = 00000100 = BCD 04 and CF = 0
AAS Result: AL = 00000100 = BCD 04 and CF = 0
no borrow required
ASCII 5-ASCII 9 (5-9)
Assume AL = 00110101 = 35H ASCII 5
and BL = 0011 1001 = 39H = ASCII 9
SUB AL, BL Result: AL = 11111100 = - 4 in 2s complement and CF =1
AAS Result: AL = 00000100 = BCD 04 and CF = 1, borrow needed
 The AAS instruction leaves the correct unpacked BCD result in the low nibble of AL and
resets the upper nibble of AL to all 0's. If we want to send the result back to a CRT Slide

terminal, we can OR AL with 30H to produce the correct ASCII code for the result. 107

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 DAS-DECIMAL ADJUST AFTER BCD SUBTRACTION
 This instruction is used after subtracting two packed BCD numbers to make sure the
result is correct packed BCD.
 The result of the subtraction must be in AL for DAS to work correctly. If the lower
nibble in AL after a subtraction is greater than 9 or the AF was set by the subtraction,
then the DAS instruction will subtract 6 from the lower nibble of AL
 If the result in the upper nibble is now greater than 9 or if the carry flag was set, the
DAS instruction will subtract 60 from AL.
AL 1000 0110 86 BCD
BH 0101 0111 57 BCD
SUB AL,BH AL 0010 1111 2FH, CF = 0
DAS Lower nibble of result is 1111, so DAS automatically
subtracts 0000 0110 to give AL = 00101001 29 BCD
AL 0100 1001 49 BCD
BH 0111 0010 72 BCD
SUB AL,BH AL 1101 0111 D7H, CF = 1
DAS Subtracts 0110 0000 (- 60H)
because 1101 in upper nibble > 9
AL = 01110111= 77 BCD, CF=1 CF=1 means borrow was needed
Slide
The DAS instruction updates AF, CF, SF, PF, and ZF, but OF is undefined. 108

Dr. Manoj V.N.V.

 MUL---MULTIPLY UNSIGNED BYTES OR WORDS
MUL SOURCE
MUL BH AL times BH, result in AX
MUL CX AX times CX, result high word in DX, low word in
AX
MUL BYTE PTR [BX] AL times byte in DS pointed to by [BX]
MUL CONVERSION_FACTOIR[BX]
Multiply AL times byte at effective address
CONVERSION-FACTOR[BX] if it was declared as type byte with DB.
Multiply AX times word at effective address
CONVERSION_FACTOR [BX] if it was declared as type word
with DW.
; Example showing a byte multiplied by a word
MOV AX, MULTIPLICAND_16 Load 16-bit multiplicand into AX
MOV CL, MULTIPLIER_8 Load 8-bit multiplier into CL
MOV CH, 00H Set upper byte of CX to all 0's Slide
109
MUL CX AX times CX, 32-bit result in DX and AX
Dr. Manoj V.N.V.
 IMUL-MULTIPLY SIGNED NUMBERS
IMUL SOURCE
 This instruction multiplies a signed byte from some source times a signed byte in
AL or a signed word from some source times a signed word in AX.
IMUL BH Signed byte in AL times signed byte in BH, result in AX
IMUL AX AX times AX, result in DX and AX
Multiplying a signed byte by a signed word
MOV CX, MULTIPLIER Load signed word in CX
MOV AL, MULTIPLICAND Load signed byte in AL
CBW Extend sign of AL into AH
IMUL CX Result in DX and AX
69 x 14
AL = 01000101 = 69 decimal, BL = 00001110 = 14 decimal
IMUL BL AX = 03C6H = + 966 decimal
MSB = 0, positive result magnitude in true form.
SF = 0, CF,OF = 1
-28 x 59 AL = 11100100 = - 28 decimal
BL = 00111011 = + 59 decimal
IMUL BL AX = F98CH = - 1652 decimal MSB = 1, negative result magnitude in 2's Slide

complement. SF, CF, OF = 1 110

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 AAM-BCD ADJUST AFTER MULTIPLY
 Before we can multiply two ASCII digits, we must first mask the upper 4 bits of each.
 This leaves unpacked BCD (one BCD digit per byte) in each byte.
 After the two unpacked BCD digits are multiplied, the AAM instruction is used to adjust
the product to two unpacked BCD digits In AX.
 AAM works only after the multiplication of two un- packed BCD bytes, and it works
only on an operand in AL. AAM updates PF, SF, and ZF, but AF, CF, and OF are left
undefined.
 EXAMPLE:
AL 00000101 unpacked BCD 5
BH 00001001 unpacked BCD 9
MUL BH AL x BH; result in AX
AX = 00000000 00101101 = 002DH
AAM AX = 00000100 00000101 = 0405H,
which is unpacked BCD for 45.
If ASCII codes for the result are desired, use next instruction
OR AX, 3030H Put 3 in upper nibble of each byte. Slide
111
AX = 0011 0100 0011 0101 = 3435H, which is ASCII code for 45
Dr. Manoj V.N.V.
 DIV-UNSIGNED DIVIDE-
DIV SOURCE
 This instruction is used to divide an unsigned word by a byte or to divide an
unsigned doubleword (32 bits) by a word.
 When a word is divided by a byte, the word must be in the AX register.
 The divisor can be in a register or a memory location.
 After the division, AL will contain an 8-bit result (quotient), and AH will contain an 8-bit
remainder.
 If an attempt is made to divide by 0 or if the quotient is too large to fit in AL (greater
than FFH), the 8086 will automatically do a type 0 interrupt.
 When a doubleword is divided by a word, the most significant word of the
doubleword must be in DX, and the least significant word of the doubleword
must be in AX.
 After the division, AX will contain the 16-bit result (quotient), and DX will contain a 16-
bit remainder. Again, if an attempt is made to divide by 0 or if the quotient Is too large
to fit in AX (greater than FFFFH), the 8086 will do a type 0 interrupt.
 For a DIV, the dividend (numerator) must always be in AX or DX and AX, but
the source of the divisor (denominator) can be a register or a memory location
specified by any one of the 24 addressing modes. Slide
 All flags are undefined after a DIV instruction. 112

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DIV BL Divide word in AX by byte in BL. Quotient in AL, remainder in
AH
DIV CX Divide doubleword in DX and AX by word in CX.
Quotient in AX, remainder in DX.
DIV SCALE [BX] AX/(byte at effective address SCALE[BX]), if SCALE[BX] is of
type byte or (DX and AX)/(word at effective address SCALE
[BX]) if SCALE[BX] is of type word
DIV BH AX = 37D7H = 14,295 decimal BH = 97H = 151 decimal
AX/BH, AL = quotient = 5EH = 94 decimal
AH = remainder = 65H = 101 decimal

 Since the remainder is greater than half of the divisor, the actual quotient is
closer to 5FH than to the 5EH produced. However, as indicated before, the
quotient is always truncated to the next lower integer rather than rounded to
the closest integer. Slide
113

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 IDIV-DIVIDE BY SIGNED BYTE OR WORD-IDIV SOURCE
 This instruction is used to divide a signed word by a signed byte, or to
divide a signed doubleword (32 bits) by a signed word.
IDIV BL Signed word in AX/signed byte in BL
IDIV BP Signed doubleword in. DX and AX/signed word in BP
IDIV BYTE PTR [BX] AX/byte at offset [BX] in DS
MOV AL, DIVIDEND Position byte dividend
CBW Extend sign of AL into AH
IDIV DMSOR Divide by byte divisor

Slide
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 AAD -BCD-TO-BINARY CONVERT BEFORE DIVISION
 AAD converts two unpacked BCD digits in AH and AL to the equivalent binary
number in AL.
 This adjustment must be made before dividing the two unpacked BCD digits in
AX by an unpacked BCD byte.
 After the division, AL will contain the unpacked BCD quotient and AH will
contain the unpacked BCD remainder.
 PF, SF, and ZF are updated. AF, CF, and OF are undefined after AAD.
EXAMPLE:
AX = 0607H unpacked BCD for 67 decimal
CH = 09H, now adjust to binary
AAD Result: AX = 0043 = 43H = 67 decimal
DIV CH Divide AX by unpacked BCD in CH
Quotient: AL = 07 unpacked BCD Remainder:
AH = 04 unpacked BCD
Flags undefined after DIV Slide

NOTE: If an attempt is made to divide by 0, the 8086 will do a type 0 interrupt. 115

Dr. Manoj V.N.V.

 CBW-CONVERT SIGNED BYTE TO SIGNED WORD
 This instruction copies the sign of a byte in AL to all the bits in AH. AH is
then said to be the sign extension of AL.
 The CBW operation must be done before a signed byte in AL can be
divided by another signed byte with the IDIV instruction.
 CBW affects no flags.

 EXAMPLE:
AX = 00000000 10011011 155 decimal
CBW Convert signed byte in AL to signed word in AX
Result: AX = 11111111 10011011 155 decimal

Slide
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 CWD-CONVERT SIGNED WORD TO SIGNED DOUBLE
WORD
 CWD copies the sign bit of a word in AX to all the bits of the DX register.
 In other words it extends the sign of AX into all of DX.

 The CWD operation must be done before a signed word in AX can be

divided by another signed word with the IDIV instruction.
CWD affects no flags.
EXAMPLE:
DX = 00000000 00000000
AX = 11110000 11000111 3897 decimal
CWD Convert signed word in AX to signed doubleword in
DX:AX
Result DX = 11111111 11111111
AX = 11110000 11000111 3897 decimal Slide
117

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 NOT-INVERT EACH BIT OF OPERAND-NOT DESTINATION
 The NOT instruction inverts each bit (forms the 1's complement) of the
byte or word at the specified destination.
 The destination can be a register or a memory location specified by any
one of the 24 addressing modes.
 No flags are affected by the NOT Instruction.

EXAMPLES:
NOT BX Complement contents of BX register
NOT BYTE PTR [BX] Complement memory byte at offset IBXI in data
segment

Slide
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 AND-AND CORRESPONDING BITS OF TWO OPERANDS--
AND DESTINATION, SOURCE
AND CX, [SI] AND word in DS at offset [SI] with word in CX register
Result in CX register
AND BH, CL AND byte in CL with byte in BH Result in BH
AND BX, 00FFH AND word in BX with immediate 00FFH.
Masks upper byte, leaves lower byte unchanged

BX = 10110011 01011110
AND BX, 00FFH Mask out upper 8 bits of BX
Result: BX = 00000000 01011110
CF, OF, PF, SF, ZF = 0
CF and OF are both 0 after AND. PF, SF, and ZF are updated by AND. AF Slide

is undefined. 119

Dr. Manoj V.N.V.

 OR-LOGICALLY OR CORRESPONDING BITS OF TWO
OPERANDS-OR DESTINATION, SOURCE
OR AH, CL CL ORed with AH, result in AH. CL not changed
OR BP, SI SI ORed with BP, result in BP. SI not changed
OR SI, BP BP ORed with SI, result in SI. BP not changed
OR BL, 80H BL ORed with immediate 80H. Set MSB of BL to a 1
OR CX, TABLE [BX][SI] CX ORed with word from effective address
TABLE[BX][SI] in data segment.
OR CX, 0FF00H CX = 00111101 10100101 ,OR CX with immediate
FF00H, Result in CX = 11111111 10100101
CF=0,OF=0,PF= 1,SF= 1,ZF=0.
 CF and OF are both 0 after OR. PF, SF, and ZF are updated by the OR
instruction. AF is undefined after OR. Note that PF has meaning only for the
lower 8 bits of a result. Slide
120

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 XOR-EXCLUSIVE OR CORRESPONDING BITS OF TWO
OPERANDS -- XOR DESTINATION, SOURCE
XOR CL,BH Byte in BH Exclusive-ORed with byte in CL. Result in CL.
BH not chanced
XOR BP,DL Word in DI Exclusive-ORed with word in BP. Result in BP. DI not
changed
XOR WORD PTR [BX], 00FFH
Exclusive-OR immediate number OOFFH with word at offset [BXI in
data segment. Result in memory location [BX]
BX = 0011110 01101001 , CX = 00000000 11111111
XOR BX,CX Result: BX = 0011110110010110 Note bits in lower byte are
inverted CF,OF,SF,ZF = 0, PF = 1, AF is undefined.
CF and OF are both 0 after XOR. PF, SF, and ZF are updated.
AF is undefined after XOR.

Slide
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 TEST-AND OPERANDS TO UPDATE FLAGS-
TEST DESTINATION, SOURCE
 This instruction ANDs the contents of a source byte or word with the contents of the specified
destination word.
 Flags are updated, but neither operand is changed.

TEST AL, BH AND BH with AL, no result stored. Update PF, SF, ZF
TEST CX, 0001 H AND CX with immediate number 0001H, no result stored.
Update PF, SF, ZF
TEST BP, [BX][DI] AND word at offset [BX][DI] in DS with word in BP. no result
stored. Update PF, SF, and ZF
Example of a polling sequence using TEST
AGAIN: IN AL, 2AH Read port with strobe connected to LSB
TEST AL, 01H AND immediate 01 H with AL to test if LSB of
AL is 1 or 0 ZF = 1 if LSB of result is 0 No result stored
JZ AGAIN Read port again if LSB = 0

AL = 01010001
TEST AL, 80H AND immediate 80H with AL to test if MSB of AL is 1 or 0
ZF = 1if MSB of AL = 0. AL = 01010001 (unchanged) Slide

PF = 0, SF = 0, ZF = 1, because ANDing produced 00. 122

Dr. Manoj V.N.V.

 SAL/SHL-SHIFT OPERAND BITS LEFT, PUT ZERO IN LSB(S)-
SAL/SHL DESTINATION, COUNT
 CF MSB LSB 0
 The destination operand can be a byte or a word that can be in a register or in
a memory location specified by any one of the 24 addressing modes.
 If the desired number of shifts is one, this can be specified by putting a 1 in the
count position of the instruction.
 For shifts of more than 1 bit position, the desired number of shifts is loaded into
the CL register, and CL is put in the count position of the instruction.
 The advantage of using the CL register is that the number of shifts can be
dynamically calculated as the program executes.
 CF contains the bit most recently shifted in from MSB.
 For a single shift, OF will be 1 if CF and the current MSB are not the same.
 For multiple-bit shifts, OF is undefined. SF and ZF will be updated to reflect the
condition of the destination. PF will have meaning only for an operand in AL. Slide
123
AF is undefined.
Dr. Manoj V.N.V.
 SAL USAGE
SAL BX, 1 Shift word in BX1bit position left, 0 in LSB
MOV CL, 02H Load desired number of shifts in CL
SAL BP, CL Shift word in BP left (CL) bit positions, 0's in 2 LSBs

SAL BYRE PTR [BX], 1 Shift byte In DS at offset [BX], 1 bit position left, 0 in LSB
IN AL, COUNTER_DIGIT
MOV CL, 04H Set count for 4 bit positions
SAL AL, CL Shift BCD to upper nibble, 0's in lower nibble.

Slide
124

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 SHR-SHIFT OPERAND BITS RIGHT, PUT ZERO IN MSB(S)
SHR DESTINATION, COUNT
0 MSB LSB CF
The flags are affected by SHR as follows: CF contains the bit most recently shifted in from
the LSB.
For a 'count of one, OF will be a 1 if the two MSBs are not both O's.
For multiple-bit shifts, OF is meaningless. SF and ZF will be updated to show the condition
of the destination. PF will have meaning only for the lower 8 bits of the destination. AF is
undefined.
SHR BP, 1 Shift word in BP one bit position right, 0 in MSB
MOV CL,03H Load desired number of shifts into CL
SHR BYTE PM [BX] Shift byte in DS at offset [BX] 3 bits right. 0's in 3 MSBs

Example of SHR used to help unpack two BCD digits in AL to BH and BL

MOV BL,AL Copy packed BCD to BL
AND BL,0FH Mask out upper nibble. Low BCD digit now in BL
MOV CL,04H Load count for shift in CL
SHR AL,CL Shift AL four bit positions right and put 0's in upper 4 bits Slide

MOV BH.AL Copy upper BCD nibble to BH 125

Dr. Manoj V.N.V.

 SAR-SHIFT OPERAND BITS RIGHT, NEW MSB OLD MSB
SAR DESTINATION, COUNT
MSB MSB LSB CF
CF contains the bit most recently shifted in from the LSB.
For a count of one, OF will be a 1 if the two MSBs are not the same.
After a multibit SAR, OF will be 0. SF and ZF will be updated to show the
condition of the destination. PF will have meaning only for an 8-bit
destination. AF will be undefined after SAR.
SAR DI, 1 Shift word in DI one bit position right, new MSB = old MSB
MOV CL, 02H Load desired number of shifts in CL
SAR WORD PTR [BP], CL Shift word at offset [BP] in stack segment
right two bit positions. Two MSBs are now copies of original MSB

Slide
126

Dr. Manoj V.N.V.

 ROL-ROTATE ALL BITS OF OPERAND LEFT, MSB TO LSB-
ROL DESTINATION, COUNT

ROL affects only CF and OF. After ROL, CF will contain the bit most recently rotated out of the MSB. OF
will be a1 after a single bit ROL if the MSB was changed by the rotate.
ROL AX, 1 Word in AX1bit position left, MSB to LSB and CF
MOV CL, 04H Load number of bits to rotate in CL
ROL BL, CL Rotate BL 4 bit positions (swap nibbles)
ROL FACTOMBXI, 1 MSB of word or byte in DS at EA = FACTOR[BXI]
1 bit position left into CF
JC ERROR Jump if CF =1to en-or routine

ROL BH, 1 CF = 0, BH = 10101110 , Result: CF,OF = 1,

BH = 0101 1101
ROL BX,CL BX = 0101110011010011, CL = 8, set for 8-bit rotate
Rotate BX 8 times left (swap bytes)
Slide
CF = 0, BX = 1101001101011100, OF undefined 127

Dr. Manoj V.N.V.

 ROR-ROTATE ALL BITS OF OPERAND RIGHT, LSB TO MSB
ROR DESTINATION, COUNT

 ROR affects only CF and OF.

 After ROR, CF will contain the bit most recently rotated out of the LSB.
For a single- bit rotate, OF will be 1 after ROR if the MSB is changed by
the rotate.

Slide
128

Dr. Manoj V.N.V.

 RCL-ROTATE OPERAND AROUND TO THE LEFT THROUGH CF
RCL DESTINATION, COUNT
RCL affects only CF and OF. After RCL, CF will contain the bit most recently rotated out
of the MSB.
OF will be a 1 after a single-bit RCL if the MSB was changed by the rotate.
OF is undefined after a multi-bit rotate.
RCL DX, 1 Word in DX 1 bit left, MSB to CF, CF to LSB
MOV CL,4 Load number of bit positions to rotate into CL
RCL SUM [BX], CL Rotate byte or word at effective address SUM[BX], 4
bits left Original bit 4 now in CF, original CF now in bit 3
RCL BH, 1 CF = 0, BH = 1011 0011 ,Result: BH= 0110 0110
CF = 1, OF =1 because MSB changed CF = 1,
AX= 0001 1111 1010 1001
MOV CL, 2 Load CL for rotating 2 bit positions
RCL AX, CL Result: CF = 0, OF undefined Slide
129
AX = 0111 1110 1010 0110
Dr. Manoj V.N.V.
 RCR-ROTATE OPERAND AROUND TO THE RIGHT THROUGH CF
RCR DESTINATION, COUNT

RCR affects only CF and OF. After RCR, CF will contain the bit most recently rotated out of the MSB.
OF will be a 1 after a single-bit RCR if the MSB was changed by the rotate.
OF will be undefined after multibit rotates.
RCR BX, 1 Word in BX right 1 bit CF to MSB, LSB to CF
MOV CL, 04H Load CL for rotating 4 bit positions
RCR BYTE PTR [BX] Rotate byte at offset [BX] in DS 4 bit positions right
CF = original bit 3. Bit 4 original CF
RCR BL, 1 CF = 1, BL = 001 1 1000
Result: BL = 10011100, CF = 0 OF = 1 because MSB changed to 1
CF = 0, WORD PTR [BX]= 0101111000001111
MOV CL, 02H Load CL for rotate 2 bit positions
RCR WORD PTR [BX], CL Rotate word in DS at offset [BX], 2 bits right
CF = original bit 1. Slide
130
Bit 14 = original CF,WORD PTR [BX] = 10010111 10000011
Dr. Manoj V.N.V.
 MOVS/MOVSB/MOVSW -MOVE STRING BYTE OR STRING WORD
MOVS DESTINATION STRING-NAME, SOURCE STRING-NAME
 This instruction copies a byte or a word from a location in the data segment to
a location in the extra segment.
 The offset of the source byte or word in the data segment must be in the SI
register.
 The offset of the destination in the extra segment must be contained in the DI
register.
 For multiple-byte or multiple-word moves, the number of elements to be
moved is put in the CX register so that it can function as a counter.
 After the byte or word is moved, SI and DI are automatically adjusted to point
to the next source and the next destination.
 If the direction flag is 0, then SI and DI will be incremented by 1 after a byte
move and incremented by 2 after a word move.
 If the DF is a 1, then SI and DI will be decremented by 1 after a byte move and
decremented by 2 after a word move.
Slide
 MOVS affects no flags. 131

Dr. Manoj V.N.V.

 MOVSB EXAMPLE
MOV SI, OFFSET SOURCE_STRING Load offset of start of source string in DS into SI
MOV DI, OFFSET DESTINATION-STRING Load offset of start of destination string in ES into DI
CLD Clear direction flag to auto increment SI & DI after move
MOV CX, 04H Load length of string into CX as counter
REP MOVSB Decrement CX and copy string bytes until CX = 0

After the move, SI will be 1 greater than the offset of the last byte in the source string.
DI will be 1 greater than the offset of the last byte in the destination string.
CX will be 0.

Slide
132

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 LODS/LODSB/LODSW
LOAD STRING BYTE INTO AL OR LOAD STRING WORD INTO AX
This instruction copies a byte from a string location pointed to by SI to AL, or a word from a string location
pointed to by SI to AX.
If the direction flag is cleared (0), SI will automatically be incremented to point to the next element of the string.
For a string of bytes, SI will be incremented by 1. For a string of words, SI will be incremented by 2 if the
direction flag (DF) is set (1), SI will be automatically decremented to point to the next string element.
For a byte string, SI will be decremented by 1, and for a word string, SI will be decremented by 2. LODS affects
no flags.
EXAMPLE:
CLD Clear direction flag so SI is auto incremented.
MOV SI, OFFSET SOURCE-STRING Point SI at start of string
LODS SOURCE-STRING Copy byte or word from string to AL or AX

Slide
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 STOS/STOSB/STOSW
STORE BYTE OR WORD IN STRING
The STOS instruction copies a byte from AL or a word from AX to a memory location in the extra segment
pointed to by DI. In effect, it replaces a string element with a byte from AL or a word from AX.
After the copy, DI is automatically incremented or decremented to point to the next string element in memory.
If the direction flag (DF) is cleared, then DI will automatically be incremented by 1 for a byte string or
incremented by 2 for a word string.
If the direction flag is set, DI will be automatically decremented by 1 for a byte string or decremented by 2 for a
word string. STOS does not affect any flags.
EXAMPLES:
Point DI at start of destination string
MOV DI, OFFGET TARGET_STRING
STOS TARGET_STRING Assembler uses string name to determine whether string is of type
byte or type word. If byte string, then string byte replaced with contents of AL
If word string, then string word replaced with contents of AX Point DI at start of destination string.
MOV DI,OFFSET TARGET_STRING
STOSB "B" added to STOS mnemonic directly tells assembler to replace byte in string with
byte from AL
Slide
STOSW would tell assembler directly to replace a word in the string with a word from AX. 134

Dr. Manoj V.N.V.

 SCAS/SCASB/SCASW
SCAN A STRING BYTE OR A STRING WORD
 SCAS compares a byte in AL or a word in AX with a byte or word pointed to by DI in ES.
 Therefore, the string to be scanned must be in the extra segment, and DI must contain the offset of the
byte or the word to be compared.
 If the direction flag is cleared (0), then DI will be incremented after SCAS. If the direction flag is set (1),
then DI will be decremented after SCAS. For byte strings, DI will be incremented or decremented by 1,
and for word strings, DI will be incremented or decremented by 2.
 SCAS affects AF, CF, OF, PF, SF, and ZF, but it does not change either the operand in AL (AX) or the
operand in the string.
 This instruction is often used with a repeat prefix to find the first occurrence of a specified byte or
word In a string.
 EXAMPLE:
 Scan a text string of 80 characters for a carriage return, ODH. Put offset of string into DI.
 MOV DI,OFFSET TEXT_STRING
 MOV AL,ODH Byte to be scanned for into AL
 MOV CX,80 CX used as element counter
 CLD Clear DF so DI autoincrements
 REPNE SCAS TEXT_STRING Compare byte in string with byte in AL
 Scanning is repeated as long as the bytes are not equal and the end of the string has not been reached.
If a carriage return ODH is found, ZF = 1, and DI will point at the next byte after the carriage return in
the string. If a carriage return is not found, then CX = 0 and ZF = 0. Slide
135

Dr. Manoj V.N.V.

 CMPS/CMPSB/CMPSW-COMPARE STRING BYTES OR
STRING WORDS
 A string is a series of the same type of data items in sequential memory locations.
 The CMPS instruction can be used to compare a byte in one string with a byte in another string
or to compare a word in one string with a word in another string.
 SI is used to hold the offset of a byte or word in the source string, and DI is used to hold the
offset of a byte or a word in the other string.
 The comparison is done by subtracting the byte or word pointed to by DI from the byte or word
pointed to by SI.
 The AF, CF, OF, PF, SF, and ZF flags are affected by the comparison, but neither operand is
affected.
 After the comparison, SI and DI will automatically be incremented or decremented to point to
the next elements in the two strings.
 If the direction flag has previously been set to a 1 with an STD instruction, then SI and DI will
automatically be decremented by 1 for a byte string or by 2 for a word string. If the direction flag
has previously been reset to a 0 with a CLD instruction, then SI and DI will automatically be
incremented after the compare. They will be incremented by 1 for byte strings and by 2 for word
strings.
 The string pointed to by DI must be in the extra segment. The string pointed to by SI must be in
the data segment.
 The CMPS instruction can be used with a REPE or REPNE prefix to compare all the elements of a Slide
string. 136

Dr. Manoj V.N.V.

 REPE CMPSB USAGE
MOV SI, OFFSET FIRST-STRING Point SI at source string
MOV DI, OFFSET SECOND-STRING Point DI at destination string CLD DF cleared, so SI and DI will auto
increment after compare
MOV CX,100 Put number of string elements in CX
REPE CMPSB Repeat the comparison of string bytes until end of string or until
compared bytes are not equal
CX functions as a counter, which, the REPE prefix will cause to be decremented after each compare.
The B attached to CMPS tells the assembler that the strings are of type byte.
If we want to tell the assembler that the strings are of type word, write the instruction as CMPSW.
The REPE CMPSW instruction will cause the pointers in SI and DI to be incremented by 2 after each compare if
the direction flag is cleared or decremented by 2 if the direction flag is set.

Slide
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 REP/REPE/REPZ/REPNE/REPNZ- (PREFIX)
REPEAT STRING INSTRUCTION UNTIL SPECIFIED CONDITIONS EXIST
 REP is a prefix, which is written before one of the string instructions. It will
cause the CX register to be decremented and the string instruction to be
repeated until CX = 0.
 The instruction REP MOVSB, for example, will continue to copy string bytes
until the number of bytes loaded into CX has been copied.
 REPE and REPZ are two mnemonics for the same prefix.
 They stand for Repeat if Equal and Repeat if Zero, respectively.
 We can use whichever prefix makes the operation clearer to we in a given
program.
 REPE or REPZ is often used with the Compare String instruction or with the
Scan String instruction.
 REPE or REPZ will cause the string instruction to be repeated as long as the
compared bytes or words are equal (ZF = 1) and CX is not yet counted down
to zero.
 In other words, there are two conditions that will stop the repetition: CX = 0
or string bytes or words not equal. Slide
138

Dr. Manoj V.N.V.

 REPE, REPNE AND REPNZ USAGE
 REPE CMPSB Compare string bytes until end of string or until string bytes not equal.
 REPNE and REPNZ They stand for Repeat if Not Equal and Repeat if Not Zero, respectively.
REPNE or REPNZ is often used with the Scan String instruction. RFPNE or REPNZ will cause the string instruction
to be repeated until the compared bytes or words are equal (ZF = 1) or until CX = 0 (end of string).
 REPNE SCASW Scan a string of words until a word in the string matches the word in AX or until all of the
string has been scanned. See the discussion of SCAS for a more detailed example of the use of this prefix
 The string instruction used with the prefix determines which flags are affected. See the individual instructions
for this information.
 Interrupts should be disabled when multiple prefixes are used, such as LOCK, segment override, and REP with
string instructions on the 8086/8088. This is because, during an interrupt response, the 8086 can remember
only the prefix just before the string instruction.

Slide
139

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EXAMPLES
TO COPY A STRING FROM ONE SET OF LOCATIONS TO ANOTHER
data segment
testmsg db ‘Defence Engineering College'
len dw 30
data ends
dst segment
dest db 30 dup(0)
dst ends
code segment
assume cs:code,ds:data,es:dst
start: mov ax,data
mov ds,ax
mov ax,dst
mov es,ax
lea si,testmsg
lea di,dest
mov cx,len
cld
rep movsb
mov ah,4ch
int 21h
Slide
code ends
140
end start

Dr. Manoj V.N.V.

PROGRAM TO FIND THE LARGEST OF 5 BYTES
data segment
arr db 09,02,99,02,05
count dw 05h
lar db ?
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov si,offset[arr]
mov cx,count
dec cx
mov al,[si]
up: inc si
cmp al,[si]
jnc down1
mov al,[si]
down1: loop up
mov lar,al
int 3
Slide
code ends
end start
141

Dr. Manoj V.N.V.

TO SORT AN ARRAY IN ASCENDING ORDER (USING
BUBBLE SORTING METHOD)
data segment
arr db 5, 4, 3, 1, 2
count dw 05
data ends
code segment
assume cs:code, ds:data
start:mov ax,data
mov ds,ax
mov cx,count
dec cx
up2: mov dx,cx
mov bx,0000h
up1: mov al,arr[bx]
cmp al,arr[bx+1]
jbe down
xchg al,arr[bx+1]
mov arr[bx],al
down: inc bx
loop up1
mov cx,dx
loop up2
int 3h
code ends Slide
end start 142

Dr. Manoj V.N.V.

END OF SECTION Slide
143

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