7/15/2021 Synchronous Counter

Instructions

4-Bit Synchronous Parallel Counter using J-K Flip-Flop

Q1

Q0

Q2 Q3

IC 7476 IC 7476 Q3 Q2 Q1

Switch

16

Negatively Triggered Clock

      TRUTH TABLE                   TIMING DIAGRAM                             Generate Wave

Serial No. Clock Q3 Q2 Q1 Q0

1 1 0 0 0 0
2 2 0 0 0 1
3 3 0 0 1 0
4 4 0 0 1 1
5 5 0 1 0 0
6 6 0 1 0 1
7 7 0 1 1 0
8 8 0 1 1 1
9 9 1 0 0 0
10 10 1 0 0 1
11 11 1 0 1 0
12 12 1 0 1 1
13 13 1 1 0 0
14 14 1 1 0 1
15 15 1 1 1 0
16 16 1 1 1 1

vlabs.iitb.ac.in/vlabs-dev/labs/digital-electronics/experiments/verify-four-bit-synchronous-asynchronous-counter-iitr/round-template/experiment/si… 1/2
7/15/2021 Synchronous Counter

vlabs.iitb.ac.in/vlabs-dev/labs/digital-electronics/experiments/verify-four-bit-synchronous-asynchronous-counter-iitr/round-template/experiment/si… 2/2