Name : Mendoza, Aldrin Daniel G.

Course & Section : BET-CpET-2C-STEM

Date : January 18, 2023
Teacher : Ms. Mary Jane Concepcion

SYCHRONOUS COUNTER

I. Introductory Information

For high – speed counting, synchronous counters are preferred for reasons explained earlier. This
experiment focuses on a common synchronous IC counter the 74LS160. The IC is a decade counter.
This means that it counts from zero to nine (0000 to 1001) for a total of ten.

Synchronous counting is achieved by having the clocks of the flip – flops internally clock simultaneously.
The outputs change at the same time when instructed by the count – enable inputs and internal gating.
The clock input triggers the flip – flops on the rising edge of the input clock.

The IC’s pin configuration is shown below. The IC is in a 16 – pin package and equipped with many input
pins to control the counting. The IC’s clear function is, however, asynchronous. This allows the flip – flop
outputs to be reset regardless of the levels of the clock, load and enable inputs.

The IC is also programmable. This means that the output maybe preset to either high or low level and
can be made to start count at a specific value. This is done by activating the parallel input pin and loading
the required data on the parallel port. The count then starts at that point.

Without additional gating, the IC provides cascading for n-bit synchronous counting through the carry look
– ahead circuitry. To allow counting, both count – enable inputs (CET and CEP) should be high.
Modifying the control inputs are not reflected in the output until the next clock pulse.

II. Materials : 5 volts DC Power Supply, 74LS160. Any Software simulator.

Interconnect the circuit shown. Initially, turn off the power to the trainer and double check your work to
ensure that everything is in order before proceeding with the experiment.
III. Procedure

Switch the clock frequency range to low position and adjust the clock frequency to minimum position (full
counterclockwise). Switch D3 to logic high position. Switch both D1 and D2 to logic low or off position.

1. Switch on the power supply.

2. Switch on both D1 and D2.
3. Observe the light pattern displayed by IN1, IN2, IN3 and IN4.
4. Identify the LED patterns displayed by these LEDs.

CLK Count IN1 IN2 IN3 IN4 TC

0 0
1 0
2 0
3 0
4 0
5 1
6 0
7 0
8 1
9 1
0 0
0 0
0 1
0 1
1 0
0 1
1 1
1 1
0 0
0 0
0 0
1 0
0 0
1 0
0 0
0 0
0 0
1 0
0 0
1 1

5. When does the output IN5 (pin 15) go high? When it reaches the 10th cycle of the cycle. Therefore,
once the IN5 lit, the input will get toggled and returns 0 state in all outputs.

6. Disconnect the jumper from the clock pulse generator to the clock input. What happens to the
counting? Output attains zero state. No count is being generated and no pattern is being
displayed.
 7. Switch D3 to logic low position. What happens to the circuit? The clock count stops and only stays
at its current output state.

8. What should be the condition of control pins R (pin 1), PE (pin 9), CET (pin 10) and CEP (pin 7) to
allow the IC to count continuously? All switches must be ON or at HIGH state in order for the
count flows simultaneously.

9. Describe operation of this IC counter.

- The Synchronous Counter implies on terms of sharing the same clock input in all flip-flops and
simultaneously generates the same clock signal. It defines as a decade counter where the count
starts from zero to nine. The clock count resets once it reaches its 10th count(1 0 0 1) and it will
return to the first count (0 0 0 0) vice versa.

IV. Conclusion

Results have shown that the Synchronous Counter happens when there’s an occurrence of the
clock input. As for the observation, it has been shown that when all switches are at HIGH state, the
clock counts simultaneously. However, once the interconnected ENP and ENT in D3 is OFF , the
clock count stops that makes the output stays in regards what was presently attained. In other
cases, no outputs will be given when there’s no clock input connected.