1.

When we move from lower technology to higher technology, say from 65nm to 180nm,
does the operating voltage increase or decrease(generally)?
2. If a circuit is designed at 250nm technology, can we simulate the circuit at 180nm
technology using the same software and obtain similar results just by adjusting the
length ? explain your answer.
3. Explain Dual Damascene process and pitch off briefly?
4.

5. What is Dishing? Why do one encounter problem like dishing? What is the solution to it?
6.

7. What are the steps involved in Library Design Flow.

8. If we are using 193nm light and working at 65nm or lower technology the wavelength of
light is comparable to the object size so in that case diffraction will occur but we still use
it. How this diffraction problem is solved? The light used is not even laser we use lenses
to converge our light why? (It could have made our life's easier why an extra setup?)
(Short answer)

9. What is the significance of full custom design or what is the significance of asymmetric
sizing? (Long answer)
10. List any two process for Si manufacturing
11

12 explain photolithography with neat diagram

13.What is a clean room?

14)

15) Explain photolithography along with a neat diagram ?

16)

17)
18)
(i) What is the wavelength of light used for masking at 28nm technology node? (1 Marks)
(ii) What Latch up? How to avoid it while making a layout?

19)

20)

21)

22)
What are the issues we face while using copper wire in fabrication process and how to
overcome those issues. [2 Marks]
23)

24)
25)

26)

27)
28) Compare the two technology scaling methods,full scaling and the constant voltage
scaling .Mention two differences.Also ,what would happen if the design rule changes from 1
micrometre to 1/S micrometre(S>1)?

29.

30.

32.

33.
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35

36.

37

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37.

38.

39.
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41. Short Answer Type

Q. Why do we use tungsten to make contacts instead of Copper?
Ans. Tungsten is used because copper creates intermediate energy levels between band gap of
silicon. Energy barrier reduces and the semiconducting property fades.
42. Answer the following questions.[5 Marks][Each question carry 1
Mark].
a.Why does delay decreases when there is a increase in Vdd?
b.Draw the C-V plot of NMOS and if we implant positive charges in Silicon
oxide then to which side the graph will shift?
c.For interconnects consider two wires,if voltage in both wires are switching in
opposite manner, then what will be the value of MCF?
d. Why Tungsten is used for making contacts and why copper is not used for
contacts?
e.Between Intrametal and Intermetal capacitance which one has larger
contibution in advance technologies and WHY?
43.

a)Explain Dual damascene process.

b) Explain copper dishing. How to remove dishing?

Ans a) In a dual-damascene (DD) structure, only a single metal

deposition step is used to simultaneously form the main metal
lines and the metal in the vias. That is, both trenches and vias
are formed in a single dielectric layer. The vias and trenches
are defined by using two lithography steps
 b) Copper dishing is defined as the difference between the
lowest and the highest point of copper, that is the difference
between the highest level go SiO2 and the lowest point of
copper

To remove this we do slotting by making pillars of SiO2 in the copper.

44.

45.
What is Dishing? How to prevent dishing?
Copper is a ductile metal which is surrounded by barrier like Titanium Nitride. After chemical
mechanical planarization, there may be some metal particle remain on the surface of dielectric
even after removing the extra metal layer. Hence, we do extra polishing that leads erosion of
copper in case of thick wires. This is called dishing. This increases the resistance of the wire.
In order to avoid dishing, slots are made in the wires of certain spacing. Slots are filled with
SiO2, which now acts as a barrier for the wires during dishing.
46.

47.
48.
49. Explain any two precautions taken in fabrication facilities to ensure high yield. [2] A) (Any 2 out of
5)
1. Compulsory use of PPE while entering the facility
2. Separate front end and back end facilities. Backend handles copper deposition. There is at least
100m distance between FE and BE to prevent copper vapours from reaching FE. If copper diffuses
into silicon, then it’s semiconductor properties may change causing the dies to fail.
3. We use yellow shifted light sources to prevent unwanted exposure of UV on the dies. 4. Air
curtains are used to isolate the clean room from the external environment. 5. The floor is porus and
airflow is from roof to floor to catch airborne particles.
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53

54 List down any 3 possible ways to optimize the layout design.

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