REGISTERS &

ADDRESSING MODES
Outline

• CPU Registers Types

• ARM Cortex-M3/4 Registers
• Memory Addressing Modes
• ARM Cortex-M3/4 Memory Access Instructions
Why Registers

• Registers the most important resource in the CPU

• It makes up what is known as the programmer’s model
• CPU contains a set of registers used in your program
• Registers may have different sizes – depend on CPU
Architecture
– 8b, 16b, 32b, 64b, etc.
• Registers holds operands used in CPU calculations and
store intermediate results
Types of Registers

• Accumulators: used to accumulate answers. Can serve

as source for one operand and destination of an ALU
operation
• Condition Code Registers: also know as Flags or
Status Register. Holds condition code bits generated by
the processor as a result of an operation, e.g.
– Z: Zero bit is set when the result is zero
– V: overflow bit is set when the result does not fit in
the register, i.e. he register content is faulty
– N: Negative (Sign) bit is set if the answer is negative
– C: Carry (Borrow) bit is used to indicate the
operation has a carry
Types of Registers

• Doubled Registers: used in smaller CPU to hold bigger

size data, e.g. 2x16b registers AL, AH can represent a
32b value A
• General Purpose Registers: Hold date. Serve as
source/destination of data transfer operations and
source of operands in ALU operations.
• Index Registers: used to calculate the effective
address of a memory access operation.
– Effective Address = Index + offset
– Usually support increment/decrement operations
• Pointer Registers: Holds the address of a memory
access operation, support ++/-- operations
Types of Registers

• Segment Registers: used in some CPUs. The physical

address consists of two parts:
– Segment part: define a region, e.g. page to access
– Offset part: define location inside the above region
• Stack Pointer: used to access variables in the stack,
which is typically used to hold function arguments and
return values
ARM Processor Programmers’ Model

• Privilege Modes:
1. Privileged mode: can access all resources
2. Unprivileged (user) mode: prohibited from
accessing certain memory regions and from
executing some operations
• Operation States:
1. Debug State: when the processor is halted by a
breakpoint
2. Thumb State: Normal operation (Thumb refers to
the name of the instruction set – ARM Cortex
specific)
ARM Processor Programmers’ Model

• Operation Modes:
1. Handler Mode: when executing an exception
handler, e.g. Interrupt Service Routine (ISR)
2. Thread Mode: when executing normal application
code
ARM Cortex–M3 / Cortex-M4 Registers
ARM Cortex–M3 / Cortex-M4 Registers

• R0-R12: general purpose registers.

– 16bit instructions can only access R0-R7
– 32bit instructions can access R0-R12
• R13, Stack Pointer (SP)
– R13 is the stack pointer
– Used to access the stack via PUSH/POP operations
• R14, Link Register (LR)
– Used to hold the return address when calling a
function or a subroutine
• R15, Program Counter (PC)
– Holds the address of the next instruction to execute
ARM Cortex Special Registers

• Three Program status registers (PSR)

– Application PSR (APSR)
– Execution PSR (EPSR)
– Interrupt PSR (IPSR)
• Can be accessed into one register called xPSR
– Since not all bits are used, all fields of the 3 PSR can
be consolidated in one register called xPSR
ARM Cortex Special Registers
ARM Cortex Special Registers
Condition Code Registers (Flags)
Condition Code Registers (Flags)

• Overflow: means the result of addition or subtraction

is too large to be represented by number of bits
available.
• Carry bit set when overflow occurs during
addition/subtraction of unsigned numbers
– Sometimes referred to as the carry/borrow bit
– Set to 1 when an overflow occurs: an addition
produces a carry or a subtraction requires a borrow
– Can be used for multiple-byte addition or subtraction
Condition Code Registers (Flags)
Condition Code Registers (Flags)
MEMORY ADDRESSING
MODES
Terminology

• Effective Address: the result of address calculation of

multiple addressing variables. May be physical or logical
address
• Expanded or Extended Addressing: allows for
addressing a memory size bigger than the addressable
memory space by the processor, i.e. 2Addr_Width. Done by
making some regions use the same physical address
• Logical Address: part of the address required for
programming purposes, e.g. index, offset. Used to
calculate the physical address
• Memory Map: shows the address ranges (region) used
for different purposes. May show memory type, e.g.
RAM/ROM
Terminology

• Physical Address: the actual address that must be

supplied to the memory hardware on the address bus.
• RAM: Random access memory, can be read/written
• ROM: Read only memory
• Relative Address: calculated by adding an offset to
program counter register
• Segment Address: the starting address of a segmen,
i.e. a region in memory, smaller than the full memory
size
• Stack: an area of RAM reserved for temporary data
storage by a program
Addressing Modes

• Linear Addressing: Instruction specifies full physical

Address
• Segmented Addressing: used in Intel 80xxx
microprocessors
– Example:

0x10000 0x1000 Segment Register

64B Segment
0x1000_ Segment shifter left 4b
0x1FFFF
0x200 Offset address

0x10200 Physical Address

Addressing Modes

• Expansion Memory: some processors allow the

processor to address physical addresses outside the
range addressable by the the address bus
– For example Motorola Freescale processor has a
certain paging window which can be used to access
pages overlaid on the same physical address
Addressing Modes – Paging window
16b address range

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17
Addressing Modes

• Register Addressing: instructions such as mov can use

register names for source/destination
– Registers are addressed by their names, e.g. R1
• Immediate Addressing: used for constant values, e.g.
literal values used in the program R0 = R1 + 3
– The literal value ‘3’ can be used immediately by
placing it as part of the instruction, instead of soring
the value in memory and loading it from memory at
execution time
– Can be used for simple data structure/types, e.g. int
Addressing Modes

• Direct Addressing: the memory address of the variable

to use by the instruction is stored as part of the
instruction. During the execution the value is loaded
from memory to one of the GP registers
– Normally used to access variables
– May be used to access constants of a complex data
types like the string “hellow world!” in printf
(“hellow world!”);
 In this case the literal value can be placed after
the instruction codes or at a fixed location in
memory, which the compiler can detect and use
 Addressing Modes

• Indirect Addressing: is very similar to direct addressing

except that the address used as part of the instruction
is the address of a pointer (i.e. address)
– That means indirect addressing requires 2 memory
loads
1. Load the pointer
2. Load the value pointed to by the pointer

The address contains the address of the data in memory indirect addressing
Addressing Modes

• Indexed and Based Addressing: when the effective

address is the sum of a constant value and a register,
the mode is indexed or based addressing
– Used to address an array, e.g. Data[i]
 The base address of Data, i.e. Data[0] is a
constant
 The index I is stored in a register and is
incremented each time a new access is made
Addressing Modes

• Relative Addressing: used to skip few instructions is

program branching or looping
– e.g. skip next instruction if zero-flag is set
– In the general case the relative address is a signed
integer that is added to the program counter (PC) to
jump to a different instruction in memory
Stack Addressing

• The stack is an area of RAM that is reserved for

temporary data storage
• Stack operates on a last-in-first-out (LIFO) basis
• Stack Pointer (SP) is a special register, which is used to
store/retrieve data to/from the stack
– In some implementations SP points to the next
available location to store data to stack
– In other implementations SP points to the memory
location pointing to the last stored value
• Stack supports 2 operations Push and Pop
 Stack Addressing

sp sp
sp sp
Data2 Data2 Data3
sp
Data1 Data1 Data1 Data1
Data Data Data Data Data
Data Data Data Data Data
Data Data Data Data Data

Initial state Push Data1 Push Data2 Pop Data2 Push Data3
MEMORY ACCESS
INSTRUCTIONS IN ARM

Addressing Modes
ARM Cortex-M3, Cortex-M4
Moving Data within ARM Processor

Immediate Addressing
Memory Access Instructions - ARM

Signed load instructions automatically perform sign expansion from smaller size
e.g. ldrsb 0x85 will write 0xffffff85 in the destination register
Memory Access Instructions - ARM

• Immediate Offset (pre-index): the effective address of

the memory transfer is the sum of the a register value
and an immediate constant value (offset)
– LDRB R0, [R1, #0x3];
– Read a byte from address R1+0x3, and store the
read data in R0
– The offset value can be either positive or negative
– Note: the square brackets means an effective
address calculation is required
Immediate Offset
Immediate Offset with Write Back

• Immediate Offset with write back: is exactly the same

as immediate offset, i.e. the effective address of the
memory transfer is the sum of the a register value and
an immediate constant value (offset)
– It also updates the address register with the
effective address used in the operation
– LDRB R0, [R1, #0x3]!;
– Read a byte from address R1+0x3, and store the
read data in R0
– Update R1 = R1 + 0x3
– The ‘!’ at the end of the instruction indicate write
back feature
Immediate Offset with Write Back
Literal Pool Access

• Literal Pool Access means the effective address involves

the Program Counter (PC) and an immediate offset
Register Offset (pre-index)

• Use in the processing of data arrays where the effective

address is a combination of a base address and an
offset that is calculated from an index
• To make the operation even more efficient the index
value can be shifted by up to 3 bits before adding it to
the base register
– LDR R3, [R0, R2, LSL #2];
– Read memory[R0+(R2 << 2)] into R3
– The shift is optional
– STR R5, [R0, R7];
– Write R5 into memory[R0+R7]
Register Offset (pre-index)

Note: {..} means optional

Register Offset (post-index)

• Memory access instructions with post-offset is very

similar to the memory access instructions with pre-
offset, except that the effective address calculation is
not used in the load/store operation, but is used to
update the offset register for the next operation
– LDR R0, [R1], #offset;
– Read memory[R1] into R0, then update
R1=R1+offset
– Note the [..] indicate that the effective address used
is R1, the offset is then used to update R1 after the
data transfer
Register Offset (post-index)
Multiple Load/Store

• One of the key advantages of the ARM architecture is

that is allows for multiple data read/write
– LDM (Load Multiple Registers)
– STM (Store Multiple Registers)
– Support on 32b data
– Used with the following postfixes:
 IA: Increment address After each read/write
 DB: Decrement address Before each read/write
– Registers are defined as a list, for example
 {R1-R5}: LDM R0, {R1-R5}; Read 5 words and
 {R1,R2,R3, R6} STM R4, {R1,R2,R3, R6}; write 4 words
 {R2, R4-R6}
Multiple Load/Store
Multiple Load/Store
Stack Push and Pop

• Stack push/pop are another form of multiple register

read/write
• They use the stack pointer (SP) for address generation
• The register list has the same syntax as LDM & STM
– PUSH {R0, R4-R7, R9};
– Push the register list into stack
– POP {R2, R3};
– Pop R2 and R3 from stack
• Usually Push instructions will have a corresponding pop
instruction of the same list to keep the stack in a same
state
Stack Push and Pop
References

• Microcontrollers and Microprocessors, chapter 4:

Introduction to CPU Registers
• Microcontrollers and Microprocessors, chapter 5:
Memory Addressing Modes
• The definitive Guide to ARM Cortex-M3 & Cortex-M4,
chapter 5: Instruction Set