19BEI0046 YANSHU

ADC LAB EXPERIMENT : 9&10

SUDHAKAR .N. SLOT:L33+L34
YANSHU YADA 19BEI004
V

6

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Experiment :09
AIM: TO DESIGN 2-BIT MAGNITUDE COMPRATOR USING BASIC LOGIC
GATES APPARATUS REQ:

P SPICE capture CISlite,digCLC(source),(7408/7400),(7486/7400),(7432/7400)

(7404,7400),(7411/7400).

CIRCUIT DIAGRAMS:

2 BIT MAGNITUDE COMPRATOR :

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PROCEDURE:

1.CREATE A NEW BLANK PROJECT.

2.ADD THE ELEMENTS FROM THE LIBRARY TO SCHEAMATIC AS PER

THE CIRCUIT DIAGRAM.CLICK ON P SPICE AND SELECT NEW
SIMUKATION PROFILE AND CREATE IT.

3. FOR HALF ADDER SET THE SIMULATION ANALYSIS TYPE AS “TIME

DOMAIN” (TRANSIENT ),RUN TO TIME :16ms .CLICK OK.

4.NOW PLACE THE VOLTAGE PROBES AT INPUT AND OUTPUT ENDS

OF THE REQUIRED PLACE.

5.CLICK RUN BUTTON AND GET THE REQUIRED OUTPUT FOR

DIFFERENT PULSES.

RESULT:

THE CIRCUIT AND OUTPUT WERE NOTE D AND VERIFIED .OUPUT

MATCHES WITH TABLE.
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EXPERIMENT:10
INVERTING AND NON-INVERTING COMPARATOR
BINARY-GRAY & GRAY-BINARY

AIM:

TO design inv and non-inv comprators using op-amps with AC input with positive
voltage and zero crossing detector.

APPARATUS REQUIRED:
P spice ,digiclock(source),-3,2XOR gates (7486/7400).

CIRCUIT DIAGRAM:

INVERTING COMPRATOR WITH AC I/P WITH POSITIVE VOLTAGE:





S

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INVERTING COMPRATOR WITH ZERO CROSSING DETECTOR:

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NON-INVERTING COMPRATOR WITH AC I/P WITH POSITIVE VOLTAGE:

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NON-INVERTING COMPRATOR WITH ZERO CROSSING DETECTOR:

PROCEDURE:

1.CREATE A NEW BLANK PROJECT.

2.ADD THE ELEMENTS FROM THE LIBRARY TO SCHEAMATIC AS PER

THE CIRCUIT DIAGRAM.CLICK ON P SPICE AND SELECT NEW
SIMUKATION PROFILE AND CREATE IT.

3. FOR BOTH CONVERSIONS SET THE SIMULATION ANALYSIS TYPE

AS “TIME DOMAIN” (TRANSIENT ),RTT 100ms. MAX STEP SIZE:100ms
CLICK OK.
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4.NOW PLACE THE VOLTAGE PROBES AT INPUT AND OUTPUT ENDS

OF THE REQUIRED PLACE.

5.CLICK RUN BUTTON AND GET THE REQUIRED OUTPUT FOR

DIFFERENT PULSES.