This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2868281, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
A New High Step-Up Multi-Input Multi-
Output DC-DC Converter
Parham Mohseni, Seyed Hossein Hosseini, Member, IEEE, Mehran Sabahi, Tohid
Jalilzadeh, and Mohammad Maalandish
Abstract—In this paper, a new multi-input-multi-output
(MIMO) dc-dc converter with high step-up capability is
proposed for wide power ranges. Also, in order to increase
each output voltage, diode-capacitor (D-C) voltage
multiplier (VM) stages are utilized in the proposed
converter. The number of input stages, output stages, and
VM stages are arbitrary and dependent to design
conditions. At first, the general structure of proposed MIMO
converter is presented. Then, in order to explain the
converter operation, we walk through the design of a 1 kW
four-input-two-output example, including loss and
efficiency calculations. We validate the design with a
prototype that matches efficiency calculations.
Index Terms—high power converter, low voltage stress,
multi-input-multi-output (MIMO) converter, non-isolated
high step-up dc-dc converter.
I. INTRODUCTION
A T the present time, due to the limitations of fossil fuels and
growing demand for electrical energy along with
environmental pollution concerns, renewable energy sources
have attracted investigators attention [1, 2]. Due to the low
generated voltage of the Photovoltaic (PV) panels, high step-up
DC-DC converters are required to increase the output voltage
of PV panels for grid-connected power systems [3]. In the
traditional method, PV modules are connected series and
parallel in order to provide the required output voltage and
power level, respectively. Therefore, maximum power point
tracking (MPPT) is not available for each PV module and the
reliability of the system is reduced. For these applications,
multi-input DC-DC converters (MICs) are the suitable solution
for simultaneous use of input sources and performing MPPT for
each PV module independently [4].
In [5-8], some isolated MICs are presented to perform
simultaneous power management of different PV panels, wind
turbine generators (WTGs), and hybrid generation applications.
In these kinds of converters, high-frequency transformers are
used for galvanic isolation which increases the volume and cost
of the converters and also the design of a transformer is
complicated. In [9-11] three new structures of non-isolated
MICs with a bidirectional and some unidirectional ports are
presented for grid-connected hybrid PV/FC/Battery
Manuscript received January 23, 2018; revised April 15, 2018, June
18, 2018 and August 11, 2018; accepted August14, 2018.
Parham Mohseni, Mehran Sabahi, Tohid Jalilzadeh and
Mohammad Maalandish are with the Faculty of Electrical and Computer
Engineering, University of Tabriz, Tabriz, 51666, Iran.
(E-mail: parham.mohseni.71@gmail.com;sabahi@tabrizu.ac.ir;
jalilzadeht1@yahoo.com and m.maalandish.ps@gmail.com).
Seyed Hossein Hosseini is with the Faculty of Electrical and
Computer Engineering, University of Tabriz, Tabriz, 51666, Iran, and
the Engineering Faculty, Near East University, 99138 Nicosia, North
Cyprus, Mersin 10, Turkey (e-mail: hosseini116j@yahoo.com).
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applications. Three new structures of two input high step-up
DC-DC converters based on Cockcroft-Walton (CW) [12] and
Modified Dickson Charge Pump [13, 14] voltage multiplier
(VM) cells are presented so that their output voltage level and
semiconductors voltage stress are dependent to the number of
VM cells. Some new non-isolated high step-up MICs are
presented in [4, 15-18]. The converter presented in [4] is based
on buck-boost and boost converters. The power flow of each
input sources can be controlled by the duty cycle of each input
stage power switch, and there is no limit for the duty cycle of
power switches and number of input stages. However, the
voltage stress of the last stage power switch and output diode is
higher than the output voltage. The voltage gain of the
converters in [15-17] is high and the voltage stress of
semiconductors is reduced by increasing the number of input
stages. In these converters, for N numbers of input stages, the
duty cycles of power switches should be more than (1-1/N) and
interleaved with 360/N.
Recently, multi-input-multi-output (MIMO) converters are
utilized to generate output voltages with various levels by
combining the different input sources with various voltage-
current characteristics in a single-stage. Some MIMO
converters are presented for DC distribution of future energy
efficient homes [19] and low power applications such as
wireless sensor networks [20-22]. In [23] a new structure of
MIMO converter based on buck-boost converter is presented
for micro-grid applications. In this converter, the number of
power switches and diodes is high that results in high power
losses, cost, and complicated structure. Two structures of
MIMO DC-DC converters which are suitable for connecting to
multi-level inverters for electric vehicle (EV) applications [24]
and high voltage level applications [25] are presented. The
converter in [24] utilizes one bidirectional input port for
charging and discharging the battery via other alternative input
sources. The converter in [25] benefits from switched-capacitor
(SC) converter to generate different output voltage levels.
In this paper, a new MIMO DC-DC converter with high
output voltage levels is proposed which the number of inputs
and outputs are independent of each other. In the proposed
converter, diode-capacitor (D-C) VM stages can be utilized for
each output port in order to increase the voltage levels of the
outputs. The number of diodes and capacitors depends on the
number of input and output ports, the output voltage levels, and
the design conditions. The converter can simultaneously use the
input sources with different voltage and power ranges for
feeding their corresponding output loads.
The proposed converter can continue its operation when one
or some number of input sources have a fault or they are not
able to provide the power of their corresponding output loads.
In this case, the other input sources can provide the power of
their corresponding load. Also, the input faults or disabilities
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2868281, IEEE
Transactions on Industrial Electronics
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will not affect the irrelevant outputs. It can be mentioned, the

converter can continue its operation in the event of failure one
or more capacitors of each output and provide the
corresponding output power. And the failure of capacitors will
not have any effect on unrelated outputs. Since there is no
restriction to increase the number of input sources and VM
stages, there is no need for series or parallel connection of the
PV modules in order to provide the required output voltage and
power level, respectively. Therefore, the proposed converter
can be a good candidate to utilize in micro-grid applications at
low/high ranges of power with high efficiency. The multi-input-
single-output (MISO) structure of the proposed converter, its
operation modes, and components design are explained in [26].

II. PROPOSED CONVERTER STRUCTURE AND

OPERATIONAL PRINCIPLES Fig. 1. The structure of the proposed MIMO converter
The structure of the proposed MIMO converter is shown in
Fig. 1. In the proposed structure, for N input voltage sources, N
inductors and N power switches are used. Hence, the number of
used power switches is minimum. As shown in Fig. 1, all the
input cells are based on the conventional boost converter. The
presented structure is composed of a number of D-C VM stages.
These stages are alternately charged via their input cell which
causes their corresponding output voltage to be increased. Each
of the VM stages is composed of one capacitor and one diode
in which the capacitors and diodes are denoted Ci,j,k and Di,j,k,
respectively. i, j, and k are the number of VM stage, the
capacitor charger input number, and the corresponding output
number of the VM, respectively. Each of the input cells is Fig. 2. Four-input-two-output sample of proposed converter
composed of one voltage source, one inductor, and one power
switch in which Vin-i, Li, and Si are the input voltage, inductor,
and the power switch of the ith cell. Also, RLi and Vout-i are the
ith equivalent output resistance and the output voltage,
respectively.
In order to simplify understanding of the converter
performance, a four-input-two-output sample of the proposed Fig. 3. Switching signals of proposed four-input-two-output converter
converter which is shown in Fig. 2 is chosen. For first output,
four stages of D-C VM (two stages for first input, one stage for B. Operation Modes
second input and one stage for fourth input) are used. Also, In this study, the operating of proposed converter is analyzed
three stages of D-C VM (one stage for second input, one stage in CCM. By supposing the same duty cycles for entire switches,
for third input and one stage for fourth input) are used for the proposed four-input-two-output converter has three
second output. operation modes which are shown in Fig. 4.
First operation mode: As shown in Fig. 4(a), in this mode,
A. Switching Method of the Proposed MIMO Converter
all the four power switches are in ON state and all the inductors
In the proposed converter, charging cells of odd stages are magnetized via its input voltage sources and their current
capacitor of VM for one output are categorized into one group are increased linearly. All the diodes are reverse biased and VM
and charging cells of even stages capacitor of VM for the same capacitors except for capacitor of the last multipliers stage of
output are categorized in another group. For normal operation each output, do not charge or discharge and have constant
of the above-mentioned converter, during turn-on, there should voltage. Moreover, first and second output voltages are
be an overlapping time between corresponding switches of supplied through its last VM stage capacitor C4.4,1 (Cout1) and
charging cells of VM even stages and VM odd stages for each C3,4,2 (Cout2 ), respectively. In this mode, the following equation
output. Also, during a period of switching, at least one of the can be written
group corresponding power switches of each output must be VL -ON  Vin , i  {1, 2, 3, 4} (1)
i i
turned off. Therefore, for each output, there is a 180 degrees
phase shift between the corresponding switches of charging In (1), the index ON represents the parameter value during turn-
cells of VM even stages and VM odd stages. Moreover, the duty on of its corresponding switch.
cycle of entire power switches must be higher than 50%. The Second operation mode: According to Fig. 4(b), in this
switching method of the proposed four-input-two-output is mode, the switches S1 and S3 are in ON state and the switches
demonstrated in Fig. 3. S2 and S4 are in OFF state. The current of inductors L1 and L3 is
increased linearly. Entire diodes of first output with the odd

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2868281, IEEE
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(a) (b) (c)

Fig. 4. The operation modes of the proposed four-input-two-output converter in CCM, (a) First mode, (b) Second mode, (c) Third mode

number (D1,1,1, D3,1,1, …) and the diodes of second output with inductors. Using this law and equations (1)-(7), the capacitors
the even number (D2,3,2 ,…) are reverse biased. Moreover, the voltage of VM stages and the voltage of first and second outputs
diodes of first output with the even number (D2,2,1 , D4,4,1 ,…) and are obtained as follows
of second output with the odd number (D1,2,2, D3,4,2 ,…) are VC 
1
Vin1 ; VC 
1
Vin1 
1
Vin 2 ; VC 
2
Vin1 
1
Vin 2 (8)
directly biased and conduct. The current of inductors L2 and L4 1,1,1 1- D1 2,2,1 1- D1 1- D2 3,1,1 1- D1 1- D2
charges the capacitors of first output with the even number 2 1 1
Vout1  VC  Vin1  Vin 2  Vin 4 (9)
(C2,2,1, C4,4,1 ,…) and second output with the odd number (C1,2,2 , 4,4,1 1- D1 1- D2 1- D4
C3,4,2,…) and discharges the capacitors of first output with the 1 1 1
odd number (C1,1,1, C3,1,1, …) and second output with the even VC  Vin 2 ; VC  Vin 2  Vin3 (10)
1,2,2 1- D2 2,3,2 1- D2 1- D3
number (C2,3,2 ,…). Since the number of multiplier stages is even
for first output and is odd for second output, the load for two 1 1 1
Vout 2  VC  Vin 2  Vin 3  Vin 4 (11)
outputs is supplied via the stored current in the inductor of last 3,4,2 1- D2 1- D3 1- D4
input cell for each of the stages (L4 ). The following equations In (8)-(11), D1 , D2, D3 , and D4 are the duty cycles of switches
are obtained for this operation mode S1 , S2 , S3, and S4, respectively. The above-mentioned
VL -ON  Vin , i  {1, 3}
i i
(2) calculations can be extended for the proposed MIMO converter
VL 2-OFF  Vin2  VC1,1,1  VC2,2,1  Vin2  VC1,2,2 (3) (which is presented in Fig. 1) as following
 For first output: α1 stages of VM for first input cell, α2
VL 4-OFF  Vin  VC  VC  Vin  VC  Vout1  stages of VM for second input cell, αa stages of VM for ath
4 3,1,1 4,4,1 4 3,1,1
(4)
Vin  VC  VC  Vin  VC  Vout 2 input cell, αb stages of VM for bth input cell, …
4 2,3,2 3,4,2 4 2,3,2
 For second output: β2 stages of VM for second input cell,
In (3) and (4), the index OFF represents the parameter value
β3 stages of VM for third input cell, βb stages of VM for bth
during turn-off of its corresponding switch.
Third operation mode: In this mode, as shown in Fig. 4(c), input cell, βc stages of VM for cth input cell, …
the switches S1 and S3 are in OFF state and the switches S2 and  …
S4 are in ON state and conduct. The current of inductors L2 and Therefore, the output voltages are determined as follows
L4 is increased linearly. Entire diodes of first output with the  1 2 a b
Vout1  1- D Vin1  1- D Vin 2  1- D Vina  1- D Vinb  ...
even number (D2,2,1, D4,4,1, …) and of second output with the  1 2 a b
 (12)
odd number (D1,2,2 , D3,4,2 …) are reverse biased. Moreover, the V   2  3 b c
V  V  V  V  ...
diodes of first output with the odd number (D1,1,1, D3,1,1,…) and  out 2 1- D2 in 2 1- D3 in 3 1- Db inb 1- Dc inc
of second output with the even number (D2,3,2,…) are directly Da , Db , and Dc are the duty cycles of switches Sa, Sb, and Sc,
biased and conduct. The stored current of inductors L1 and L3 respectively.
charges the capacitors of first output with the odd number
(C1,1,1, C3,1,1,…) and of second output with the even number III. DESIGN OF COMPONENTS
(C2,3,2,…) and discharges the capacitors of first output with the
even number (C2,2,1 , C4,4,1 , …) and of second output with the A. Inductors Design
odd number (C1,2,2, C3,4,2 …). Since the number of multiplier The value of inductors is designed so that the converter
stages is even for first output and is odd for second output, the operates in CCM. Therefore, the average current of each of the
loads for two outputs is supplied via the capacitor of its last VM inductors must be greater than their half current ripple. For
stage C4.4,1 (Cout1 ) and C3.4,2 (Cout2). The following equations are choosing the size of inductors, their average current and current
obtained for this operation mode ripple must be calculated. The average current of inductors L1 ,
VL1-OFF  Vin1  VC1,1,1  Vin1  VC2,2,1  VC3,1,1 (5) L2 , L3, …, La , Lb , Lc, …, in the proposed converter is as follows
1  I  2 I out 2  I  ...
VL - ON  Vin , i  {2, 4} (6) I L1,avg  I out 1; I L 2,avg  2 out 1 ; I L 3,avg  3 out 2 ;...
i i 1- D1 1- D2 1- D3
(7) (13)
VL 3-OFF  Vin3  VC1,2,2  VC2,3,2   I  b I out 2  I  ...
I La ,avg  a Iout1; I Lb ,avg  b out1 ; I Lc ,avg  c out 2 ;...
In order to calculate the output voltages and the voltage of 1- Da 1- Db 1- Dc
capacitors, the volt-second balance law is used for entire input

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2868281, IEEE
Transactions on Industrial Electronics
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Also, the current ripple of each of the inductors is determined As a result, the voltage stress across the diodes is always lower
as follows than the output voltage so that as the number of VM stages
DV
i in
increases, the normalized diodes voltage stress is decreased.
i
I Li  , i  {1, 2, 3, ..., a, b, c, ...} (14) Also, the voltage stress across the output diode is, for each
Li f s
output, lower than the other diodes voltage stress which is
In (14), ∆ILi and fs are the inductor Li current ripple and expressed as follows
switching frequency, respectively. Using (13) and (14), the 1
minimum value of inductors L1, L2 , L3 , …, La, Lb, Lc, … is VD -Stress = V in (20)
i,j,k 1-D j j
calculated as follows
D1 1- D1  Vin1 D2  1- D2  Vin 2 D3  1- D3  Vin3
According to the operation modes, the average current of entire
L1  ; L2  ; L3  ;... diodes during one switching period is equal to
2 f s1I out1 2 f s   2 I out1   2 I out 2  2 f s  3 I out 2  ...
(15) I D , avg  I out , i, j, k  {1, 2, 3, ...} (21)
Da  1- Da  Vin1 Db  1 - Db  Vin 2 Dc  1- Dc  Vin3 i , j ,k k
La  ; Lb  ; Lc  ;...
2 f s a I out1 2 f s   b I out1   b I out 2  2 f s   c I out 2  ... D. Capacitors Design
Using (13) and (14), the maximum current value of the The capacitor value of last VM stage (output capacitor) for
inductors can be written as follows each of the outputs is chosen based on the transferred charge to
DV
i in the outputs in order to provide the desired voltage ripple of the
i
I Li,max  I Li, avg  , i  {1, 2, 3, ..., a, b, c, ...} (16)
2Li f s each of the outputs. The capacitance of the output capacitor for
kth output is equal to
B. Power Switches Design I out
k
It is important to mention that the semiconductors are Cout  Ci , j , k 
k
D j , i, j, k  {1, 2, 3, ...} (22)
f s Vout
designed in such a way that they can withstand the voltage k

stress across them. In the proposed converter, the power Also, the value of the other capacitors of the VM stages for kth
switches voltage stress is minimum and similar to the output is equal to
conventional boost converter. The general equation for the Iout
k
voltage stress of the power switch in the MIMO converter is as Ci, j,k  , i, j, k  {1, 2, 3, ...} (23)
f sVC
follows
1 E. Number of D-C VM and input stages design
VS - Stress  Vin , i  {1, 2, 3, ..., a, b, c, ...} (17)
i 1- Di i According to the mathematical analysis performed in a
Therefore, the voltage stress of the power switch is minimum steady state, each output voltage level increases by increasing
and it is possible to use the switches with low nominal voltage its number of D-C VM stages. Also, the voltage stress across
and RDS-on which increases the converter efficiency. Also, with the power switches of each output decreases by increasing the
increasing the number of VM stages for each output, the power stages. Therefore, the number of voltage multiplier stages for
switches voltage stress is reduced. The used semiconductors each output can be designed based on the peak inverse voltage
must withstand the conduction current. A general equation can of the available power switches VDS-max. The number of D-C
be written for the average current of switches S1, S2, S3, …,Sa , VM stages for the kth output can be obtained as follows:
Sb , Sc as follows V
1Iout1  I  I  I  ... nk  kout-k (24)
I S1,avg  - Iout1; IS 2,avg  2 out1 2 out 2 - Iout 2 ; IS 3,avg  3 out 2 - ... ;... VDS-max
1- D1 1- D2 1- D3
(18) Also, the number of D-C VM stages for each input can be
I  I  I  I  ...
I Sa,avg  a out1 ; ISb,avg  b out1 b out 2 ; ISc,avg  c out 2 ;... calculated based on the continuous Drain current IDS of the
1- Da 1- Db 1- Dc
corresponding power switches. Therefore, based on (18) the
Therefore, the current stress flowing the power switches number of VM stages for each input can be obtained as follows:
depends on the number of VM stages which is charging through (1- D1 )( I DS1  I out1 ) (1- Da ) I DSa
 
that input cell. Also, according to (13) and (18), the average  1  I out 1  a  I out1
current of switches S1 , S2, S3, … is smaller than the average  
 
 2 I out1   2 I out 2  (1- D2 )( I DS 2  I out 2 ) ,  b I out1   b I out 2  (1- Db ) I DSb (25)
current of corresponding inductors of its input cells.  I  I
 ...  (1- D3 )( I DS 3  I out 3 )  ...  (1- Dc ) I DSc
Furthermore, the average current of switches Sa, Sb, Sc, … is  3 out 2  c out 2
equal to the average current of corresponding inductors of its  
input cell. By considering (24) and (25) it can be written:
1   2   a  b  ...  n1; 2  3  b  c  ...  n2 ; ... (26)
C. Diodes Design
Therefore, by using the equations (24)-(26) the number of D-C
According to the operation modes, the voltage stress across VM and input stages for each output can be obtained.
the diodes of the VM stages depends on the voltage of two
capacitors which the diode is connected between them. If Di,j,k
IV. CONVERTER PERFORMANCE IN CASE OF ELEMENT
and D(i+1),m,k are two consecutive diodes of kth output for i, j, k,
FAILURE
m={1, 2, 3, …}, the general equation of the voltage stress
across the diodes of the VM stages is determined as follows In the proposed converter, if one or more input sources are
1 1 encountered failure or are not able to provide their related
VD - Stress  Vin  Vin (19) outputs power, the other input sources can provide their related
i, j,k 1- D j j 1 - Dm m
output power and the inability of the input sources will not have

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2868281, IEEE
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any effect on unrelated outputs. For example, in the presented output variables, state variables and control signals,
converter in Fig. 2, when the third input voltage source Vin3 respectively.
cannot generate any power, the second and fourth input voltage The proposed MIMO converter has to be controlled by
sources (Vin2 and Vin4 , respectively) can provide the power of multi-variable control method, for example, decoupling method
second output power (Pout2 ), and the inability of the third input is applied in Refs [4 and 9], and pole-placement method (via
source has no effect on first output voltage level (Vout1 ). These integral state feedback) is applied in [30]. Decoupling method
conditions occur when PV inputs are fully shadowed or in the becomes more complex when the system order goes more than
hybrid systems, one or more inputs are not capable of three. Therefore, it should be used the pole placement method
generating power. In the event of failure or open circuit of the via integral state feedback to reach a suitable control method
one input sources, the parallel diode of the corresponding power for the proposed expandable system. This control method is
switch of the input cell, will forward biased when the power shown in Fig. 5. In this method, if the MIMO control system is
switch turned-off and it will be caused to continue the operation complete states controllable, it can be located the closed-loop
of the converter. Therefore, this structure is suitable for use in poles of the system to any suitable location with proper design
renewable energies due to their production capacity is of the state feedback gain matrix. According to Fig. 5 it can be
dependent on environmental conditions. It can be also written with equation (27):
mentioned, in the event of failure (open circuit) one or more u  - K x x - K q q (29)
capacitors corresponding to each output, the converter can q  r - y  r - C ' x (30)
continue its operation and provide the corresponding output
power. Also, the failure (open circuit) of the capacitor or Where q is the integrator output and r is the reference signals
capacitors will not have any effect on unrelated outputs. For vector for the output variables of the converter. By considering
example, in the presented converter in Fig. 2, if the capacitor (27), the controllability matrix of this system is defined as
C1,1,1 opens, at the first operation mode, the converter can act as follows
its normal operation. In the second operation mode, the diodes Φc   B ' A ' B ' A '2 B ' ... A 'n -1 B ' (31)
D1,1,1 , D2,2,1 and D3,1,1 are forward biased and the diode D4,4,1 is For this system, if the rank of the controllability matrix Øc is
reverse biased. The stored current of inductor L1 causes charge complete rank(Øc)=n, then the system is complete state
the capacitor C3,1,1. Capacitor C2,2,1 does not charge or discharge controllable.
at this condition. In the third operation mode, the diodes D1,1,1 , By combining (27) and (30), the new state space model for
D2,2,1 and D3,1,1 will be reverse biased and the diode D4,4,1 will be the converter is obtained as follows:
forward biased. The stored current in the inductor L2 will charge ˆ
 A
'  Bˆ '
just the capacitor C1,2,2 and the stored current in the inductor L4
 x (t ) 
 A ' 0   x (t )   B '  0   x (t ) 
will transfer to the output. Also, there is no change in the     -C ' 0   q (t )    0  u (t )   I  r (t ) ; y (t )   C ' 0  q (t )  (32)
operation of the converter for the second output at the three  q (t )          
operation modes. The obtained system should be complete state controllable. If
the following matrix rank is n+m, the defined system is
V. CONTROL S YSTEM FOR THE PROPOSED CONVERTER complete state controllable:
In the proposed MIMO converter, all the inputs are fed by  B ' A' 
M   ; rank ( M )  n  m (33)
renewable energy sources that the generating power depends on  0 -C '
their environmental conditions. Therefore, a proper control Equation (33) guarantees that there is a feedback matrix K=[Kx
method is required to set suitable duty cycle for each of the Kq], which places closed-loop poles in arbitrary places. This
power switches to draw maximum power from the input state feedback can be entered into the control system as follows:
sources. A small signal modeling is necessary to design of the  x (t )   x (t ) 
closed-loop control system. The state space averaged model is u (t )  - K    -  K x K q    (34)
 q (t )   q (t ) 
used to reach the small signal model of the proposed MIMO
By importing (34) in (32), the state equations of the control
converter which is explained in Refs [4, 9 and 30]. In this
system are written as follows
converter, the current of all inductors and the voltage of
capacitors are chosen as the state variables, and the duty cycles  x (t )   A '- B ' K x - B ' K q   x (t )   0
   r (t ) (35)
are the control inputs. Therefore, the small signal model of the  q (t )   -C ' 0   q(t )   I 
proposed converter in Fig. 2 as follows: By specifying the desired eigenvalues of A'-B'K ˆ ˆ (The desired
 x  A ' x  B ' u closed-loop poles) as µ1, µ2 , … and µ(n+m), The state-feedback
 (27)
 y  C ' x gain matrix Kx and integral gain constant Kq can be determined
In (24), x , u and y are the state variables vector, control by the control system toolbox of the MATLAB software. Since
the designed control system has an integrator, it tracks the input
signals, and output signals, respectively.
references IL1,ref, IL2,ref , IL3,ref and IL4,ref without steady-state
 i L 2 i L 3 i L 4 v C1,1,1 v C1,2,2 v C2,3,2 v Cout 2 
 x  i L1
T
error. The bode-plots of the four-input-two-output converter
 (28)
u T  [ d1 d2 d3 d4 ] & y T  [i L1 i L 2 i L 3 i L 4 ] system after controllers are illustrated in Fig. 6. The desired
closed-loop poles should be determined to reach the gain
Where A ' (n×n fixed matrix), B' (n×r fixed matrix) and C' margin of GM≥10 and phase margin of 60º≤PM≤80º for each
(m×n fixed matrix) that they can be obtained from the explained closed-loop control path. As it can be seen, the phase margins
method in Refs [4, 9 and 30], and m, n and r are the numbers of of the closed-loop control paths iL1 , iL2, iL3 and iL4 are 78.6º,

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75.3º, 61.9º and 79.9º, respectively. Therefore, the phase and In (29), IDi,j,k and ID(i+1),m,k are the current of two consecutive
gain margins are in their optimum areas. diodes, ICi,j,k is the current of VM capacitors except for the last
VM stage of each output, Dj and Dm are the duty-cycles of the
switches Sj and Sm, respectively. So according to the operation
modes, RMS currents of the VM capacitors are obtained as
follows:
Fig. 5. Closed-loop system control schematic of the sample four-input- 2 - D j - Dm
IC  Iout , i, j, m  {1, 2, 3, 4} , k  {1, 2} (43)
i , j , k - RMS
two-output of the proposed converter 1- D  1- D 
j m
k

D4
ICout  Iout , k  {1, 2} (44)
k RMS 1- D4 k
Therefore, the conduction losses of capacitors are equal to:
2- D - D  P k j m out
Pr  rCi , j ,k , i, j, m  {1, 2, 3, 4}, k  {1, 2} (45)
C -i , j , k
1- D  1- D  R
j m Load
k
Fig. 6. Bode plots for the transfer functions of the inductor currents D4 Pout
k
Pr  rCoutk , k  {1, 2} (46)
VI. EFFICIENCY ANALYSIS
C -outk
1- D4  RLoadk
In this part, the efficiency of the proposed converter is Also, according to the operating modes of the converter, RMS
presented with the parasitic values of the components such as currents of the power switches S1, S2, S3 and S4 are obtained as
ESR (equivalent series resistance) of the inductors (rL) and follows:
2 2 2 2
capacitors (rC ), ON-state resistance of MOSFET switches (rDS ), 4I out 1 I out 1 I out 2 I out 2
I S1 - RMS   ;I  
forward resistance of diodes (rD ) and forward voltage of diodes 1- D1 
2
1- D2  S3 - RMS 1- D3 
2
1- D2 
(VF). Also, the converter switching losses due to the major role
in the converter efficiency are presented. For efficiency analysis DI 2
  2 - D2  I 2
 2I out 1I out 2 2
I out
IS  2 out 2 out 1
 1 (47)
2 - RMS
of the converter, the current ripple of the inductors is neglected. 1- D2  2
1- D1 
Therefore, the RMS values of inductor currents are equal to 2
average values. So we have: IS 
 2 - D4  Iout1  Iout 2  
I out1  I out 2  Iout 1  I2
 out 2
4 - RMS
I Lj - RMS  I Lj , avg , j  {1, 2, 3, 4} (36) 1- D4 2 1- D1  1- D3 
So, by replacing (13) into (24), the conduction losses of the So the conduction losses of the power switch S1, S2 , S3andS4 can
inductors L1 , L2, L3 andL4 can be calculated as follows: be calculated as follows
4 Pout1 rL2  Pout1 P 2Vout1Vout 2  4 1 Pout1 Pout2 1 1
Pr L1  rL1 ; Pr L2   out 2  Pr =rDS1 ( + ) ,P =r ( + )
1- D1 
2
RLoad1 1- D2 
2 
R
 Load1 RLoad 2 R

Load1RLoad 2 
DS1
 1-D1 
2
 1-D2  RLoad1 rDS3 DS3 RLoad2  1-D3  2  1-D2 
(37) D2 Pout2  2-D2  Pout1 2Vout1Vout2
Pout 2 rL 4  Pout1 P 2Vout1Vout 2  + +
Pr L3  rL3 2
; Pr L4  2   out 2   RLoad2 RLoad1 RLoad1RLoad2 Pout1
1- D3  RLoad 2 1- D4  R
 Load1 RLoad 2 R Load1RLoad 2  Pr =rDS2 ( 2 
 1-D1  RLoad1
)
DS2
 1-D2  (48)
For RMS currents of the diodes can be written as follows:
P P 2V V P V V
I out  2-D4  ( out1  out2  out1 out2 ) ( out1  out1 out2 )
k RLoad1 RLoad2 RLoad1 RLoad2 RLoad1 RLoad1RLoad2
ID
i , j , k  RMS
 , i, j  {1, 2, 3, 4} , k  {1, 2} (38) Pr =rDS4 ( 2 
1- D j DS4
 1-D4   1-D1 
Therefore, the conduction losses of the diodes can be calculated Pout2
+ )
as follows:  1-D3  RLoad2
rD
i , j ,k
Pout
k
The switching losses of the proposed converter for the switches
Pr  , i, j  {1, 2, 3, 4} , k  {1, 2} (39) S1 , S2, S3 and S4 , can be calculated as follows:
Di , j , k
1- D  R j Load
k 1 1
The average current of diodes is essential for forwarding PSj -Switching  I LjVSj  tON  tOFF   f S COSS VSj2 , j  { 1, 2 , 3, 4 } (49)
2  j j  2 j
voltage losses of the diode. Therefore, by using (21), the In above equation, COSSj is the capacitor of each power switch
forward voltage losses of diodes can be calculated as follows: or MOSFET. fs, VSj and ILj are the switching frequency, voltage
VF Pout across the power switch Sj and the average current of inductor
i , j ,k k
PV  , i, j  {1, 2, 3, 4} , k  {1, 2} (40)
F -i , j , k Vout Lj, respectively. tONj and tOFFj are the turn-on delay time and
k
turn-off delay time of the power switch or MOSFET Sj.
The current of each VM capacitors during a period of time can The efficiency of the four-input-two-output sample of the
be expressed as follows: proposed converter can be calculated as follows: [see (50)]
 I Di , j ,k (1- D j )Ts Where PrL, PrDS , PrD, PVF, PrC , and PS-Switching are conduction
IC  , i, j, m  {1, 2, 3, 4} , k  {1, 2} (41)
losses of inductors, conduction losses of power switches,
 I D( i1),m,k (1- Dm )Ts
i , j ,k

conduction losses of diodes, forward voltage losses of diodes,

 I Doutk - I outk (1- D4 )Ts and switching losses of power switches.
I Cout   , k  {1, 2} (42)
- I outk D4Ts
k

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Pout -Total Pout1  Pout 2

   100% , PLoss-Total  Pr L  Pr  PrD  PV  Pr  PS - Switching
Pin-Total Pout1  Pout 2  PLoss -Total DS F C

4 A1 A2  r rL 4 
2  1
Pr L  rL1 2
 rL 3 2
 L2
2
  A  A2  2 B1 B2 
1 - D1  1 - D3   1 - D2  1 - D4  
 4A A1   A A2   D A   2 - D2  A1  2 B1 B2 A1   2 - D4  A1  A2  2 B1 B2   2 - D2  A1  B1 B2 A2  (50)
Pr  rDS 1  1
 r  2
 r  2 2  r    
DS  1 - D1 
2
1 - D2   DS 3  1 - D3  2  1 - D2   DS 2   1 - D2 
2
1 - D1   DS 4   1 - D4 
2
 1 - D1   1 - D3  
 2 A1 A1 A1   A2 A2 A2  4
1   1 2
Pr  rD1      rD 2     & PS - Switching   I LjVSj  tON  tOFF   f S COSS VSj & PV  4VF1 B1  3VF 2 B2
 1 - D1  1 - D2  1 - D4    1 - D2  1 - D3   1 - D4   j 1 2  j j 2 j
D F

 2  2 - D1 - D2  A1  2 - D1 - D4  A1 D4 A1    2 - D2 - D3  A2  2 - D3 - D4  A2 D4 A2  Pout 1 Pout 2 V V
Pr  rC 1    r     & A1  , A2  , B1  out 1 , B2  out 2
C
 1 - D1 1 - D2  1 - D1 1 - D4  1 - D4   C 2  1 - D2  1 - D3  1 - D3  1 - D4   1 - D4   RL1 RL 2 RL1 RL 2

TABLE I
COMPARISON BETW EEN THE PROPOSED CONVERTER AND OTHER CONVERTERS
Max. voltage Max. voltage Freq. Eff. Pout Number of
Converter Output voltage levels Input Current
across switches across diodes [kHz] [%] [W] Input Output Inductor Switch Diode Capacitor
[19] High High - Discontinuous - - - N M N+1 N+M N+M N+M
[20] Low High - Discontinuous 9 - 200 N M 1 N+M N+M M+2
MIMO

[21,22] Low High - Discontinuous - 86 200 N M 1 N+M N+M M

[23] Low High - Discontinuous 10 - 100 N M M N×M M(N+1) M
[24] Low High - Discontinuous 10 80 230 N M 1 N+M N+M M
[25] High Low - Discontinuous 10 - 60 N M 1 N+1 N+2M 2M-1
[5] n (1- D ) Vo n Vo Continuous 63 94 300 2 1 3 2 4 3
[8] 2nD Vo 2nD (1- D ) Vo 2(1- D ) Continuous 60 90.2 100 N 1 N+2 N N+4 2
MIMO

[18] N (1- D) Vo N Vo N Continuous 15 91.2 300 N 1 N N 2N-1 2N

[17]  N (1- D)  D  (1- D )2 DVo N (1- D )  D Vo  N (1- D)  D  Continuous 30 - 81 N 1 N+1 N+1 N+1 N+1
[15] N (1- D) Vo N 2Vo N Continuous 100 - 96 N 1 N N N N
[27] (1  3D ) (1- D ) Vo (1  3D ) 2Vo (1  3 D ) Continuous 50 96.5 200 1 1 3 2 2 3
 D(n -1)  n  2 1- D Vo ( n  1)Vo 2
SISO

[28] Continuous 50 95 1000 1 1 (3-winding 2 6 5

n1  n2  n D ( n -1)  n  2 D ( n -1)  n  2 coupled )

[29] (3  D) (1- D ) V o (3  D ) 2Vo (3  D ) Continuous 25 96.2 1000 1 1 6 6 14 8

Proposed m (1- D ) Vo m 2Vo m Continuous 40 96.8 1000 N M N N Depends on design
m,N and M are the numbers of diode-capacitor voltage multiplier stages, input stages and output ports of the proposed converter, respectively (where m≥N), D is
the equal duty cycles (D1= D2= D3= D4= …= D) of the converters, n is the turns ratio of the transformer (n=Ns/Np) in the converters presented in [5, 8] ,and n1
and n2 are the turns ratios of three-winding coupled inductors n1=(N2/N1) and (n2=(N3/N1) of the converter in [28].

(a) (b) (c)

Fig. 7. Comparison of the proposed converter, other MISO converters with three inputs (N=3) for (Vin1=Vin2=Vin3=Vin) and (D1=D2=D3=D 4=D) and
SISO converters, (a) Voltage gain comparison, (b) Normalized power switch voltage stress comparison, (c) Normalized power diodes voltage stress
comparison

VII. COMPARISON STUDY proposed converter is low, hence size of the converter is
In this section, in order to evaluate the advantages of the decreased (by using low input filter). In the converters of [20-
proposed converter, a comparison is performed between the 22], [24], and [25], using just one inductor for any numbers of
proposed converter and some MIMO and MISO converters in inputs and outputs, the complexity, size, and weight of the
the literature. The results of the comparison are tabulated in converters is decreased. However, at any moment, just one of
Table I. According to Table I, the converters presented in [20- the input sources delivers its power to the circuit and it causes
24], due to their low outputs voltage levels are not suitable for the problem of time distribution between the inputs, limitation
connecting the renewable power sources to the power grid. in transferring input powers, limitation to getting maximum
Moreover, the proposed converter is a current fed converter and power from the inputs, and wide ripple on input currents. Also,
its input currents are continues, and the converters in [19-25] the converters in [19-22], and [24], at any moment just one of
are voltage fed converters and their input currents are the output ports get power from the circuit and the limitation of
discontinues. Therefore, the input currents ripple of the

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time distribution is intensified by increasing the number of
outputs.
The comparison of the voltage gain and the normalized
voltage stress across the semiconductors between the proposed
converter, other MISO converters with three input sources and
Single-input-single-output (SISO) interleaved converters are
shown in Fig. 7. According to Fig. 7(a), it can be said that for
D<0.75, the voltage gain of the proposed converter with m=6
is higher than other topologies. For D>0.75, the converter in
[17] has the highest voltage gain. Nevertheless, it is noticeable
that operating at extreme values of duty cycle complicates the
converter control and reduce its stability. From Fig. 7(b) and
(c),it is transparent that the normalized voltage stress across the
semiconductors is lower than other converters, significantly.
Also, the outputs voltage levels and semiconductors voltage
stress are dependent to the number of D-C VM stages and with
increasing the number of VM stages, the outputs voltage levels
of the proposed converter increases and the normalized voltage
stress across the semiconductors decreases. One of the main
advantages of the proposed converter compared to the other
MIMO/SO and SISO converters are the ability of the proposed
converter to operate at high/low power applications with high
efficiency. Moreover, by increasing the number of input cells,
the ability of the converter to operate in high power levels
increases. These features provide more flexibility for a designer
to select the right numbers of D-C VM stages and input cells
based on efficiency, cost, output voltage levels, semiconductors
stress, and power required.
TABLE II
COMPONENTS CHARACTERISTICS
Values
Components
Experimental Efficiency calculations
Output Powers Pout1=520 W, Pout2=480 W 10 W-5 kW
Vin1=52 V, Vin2=40 V,
Input Voltages Vin=50 V
Vin3=50 V, Vin4=42 V
Switching Frequency 40 kHz 40 kHz
Output Voltages Vout1=453 V,Vout2=322 V Vout1=400 V,Vout2=300V
Duty Cycles 0.6 0.5
Inductors L1= L2= L3= L4=400 µH rL=80 mΩ
Power Switches IRFP260 rDS=40 mΩ
Power Diodes STRP860DF rD=50 mΩ, VFD=0.7 V
Capacitors 44 µF, 450 V rC=20 mΩ
VIII. EXPERIMENTAL RESULTS
In order to validate the operation and theoretical analysis of
the proposed converter, a prototype of the converter in Fig. 2,
is constructed and tested in the laboratory. The components
characteristics that are used to construct the prototype of the
converter and to calculate the efficiency of the proposed
converter are listed in Table II.
The experimental waveforms of the inductors current iL1 and
iL2 are shown in Figs. 8(a) and 8(b), respectively. The measured
average current of inductors L1 and L2 is 5.82 A and 6.67 A,
respectively. According to (13), the calculated average current
of inductors L1 and L2 is 5.59 A and 6.43 A, respectively. The
measured current ripple of the inductors L1 and L2 are 2 A and
1.6 A, respectively which can be obtained from (14). Figs. 8(c)
and 8(d) illustrates the experimental waveforms of the voltage
stress across power switches (S1 and S2) and the output voltages
(Vout1 and Vout2 ), respectively. The measured voltage stress
across power switches S1 and S2 is 128.5 V and 98 V,
respectively which is shown in Figs. 8(c) and they confirm (17).
The calculated voltages of first and second output are 465 V and
330 V from (9) and (11), respectively. The output voltages Vout1
and Vout2 are obtained 451.5 V and 320 V from experimental
results which are shown in Fig. 8(d). The maximum voltage
stress across the power diodes are shown in Fig. 9. The voltage
stress across the first VM diode of the first output D1,1,1 and the
first output diode Dout1 are obtained 225 V and 100 V from
experimental results. Also, based on experimental results, the
voltage stress across VM diodes of the second output D1,2,2 and
D2,3,2 are 218.7 V and 224 V, respectively, and they are
approximately equal. Therefore, the experimental results of
voltage stress across the power diodes confirm (19) and (20).
(a) (b)
(c) (d)
Fig. 8. Experimental waveforms of the proposed four-input-two-output
converter, (a) Inductor L1 current (iL1), (b) Inductor L2 current (iL2), (c)
Voltages of the switches S1 and S2, (d) Output voltages (Vout1 and Vout2)
(a) (b)
(c) (d)
Fig 9. Experimental waveforms of voltages across the VM diodes, (a)
Diode D1,1,1 voltage, (b) The first output diode Dout1 voltage, (c) Diode
D1,2,2 Voltage, (d) Diode D2,3,2 voltage
Figs. 10 (a) and 10(b) illustrate the transient response of the
proposed converter under 50% step-change (from 520W to
260W) of the first output load. Based on Fig. 10(a), the first
output voltage (Vout1) arrivesin steady state after 37.5ms (the
voltage variation is 1% about). Fig. 10(b) illustrates the voltage
variation of the second output voltage Vout2 (it is about 0.3%).
Therefore, it can be concluded that the outputs voltages of the
proposed converter have not significantly changed with load
variations, and also the first and second outputs voltages are
independent of each other. Fig. 10(c) illustrates output voltages
when one of the input sources (Vin3 ) is corrupted. It is clear that
the voltage Vout1 have not significantly changed and after 50ms
is fixed. By observing this figure, the second output voltage
(Vout2 ) is dropped from 320 V to 197 V about after 50ms after
the failure of the input source Vin3 . Based on equations (9) and
(11), it can be said that the first output voltage Vout1 is
independent of Vin3 and the second output voltage Vout2 depends

0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2868281, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
on Vin3 . Therefore, equations (9) and (11) confirm the converter
experimental results of the outputs voltages (Vout1 and Vout2 )
which is shown in Fig. 10(c).
(a) (b)
(c)
Fig. 10. Transient response, (a) of the first output for 100% and 50%
variation load of first output, (b) of the second output for 100% and 50%
variation load of first output, (c) for before and after the corruption of the
third input source (Vin3)
(a) (b)
(c)
Fig. 11. Theoretical and Experimental efficiency results of the four-input-
two-output proposed converter, (a) Theoretical efficiency of the
converter at various total outputs powers, (b) Theoretical efficiency of
the converter for various equal duty-cycles (D1=D2=D3=D4=D) (c)
Experimental efficiency of the converter at various total output powers
The results of the theoretical and experimental efficiency of
the four-input-two-output proposed converter are shown in Fig.
9. Fig. 9(a) illustrates the theoretical efficiency of the converter
at various total output powers. By considering Fig. 9(a), it can
be concluded that the efficiency of the converter is high at high
powers and the converter has the ability to operate at high
power applications. Also, the converter can operate at power
levels higher than 5 kW by increasing the number of input cells.
Fig. 9(b) illustrates the efficiency of the converter for various
equal duty-cycles. According to this figure, it can be concluded
that the efficiency of the converter is decreased by increasing
the duty-cycles and this reduction at high powers is noticeable.
Fig. 11(c) illustrates the experimental CCM operation
efficiency of the proposed converter at various total output
powers. According to this figure, it can be said that the
efficiency of the converter decreases by increasing the total
outputs power with a slight slope at power levels higher than
650 W. The maximum efficiency of the converter is 97.51% at
652 W total outputs power and the experimental efficiency of
the converter at 1000 W total outputs power is obtained
96.82%. Therefore, the figure confirms that the converter has
high efficiency (more than 96.5%) even the total output power
is more than 1 kW and the converter can work in low/high
powers with high efficiency.
0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
IX. CONCLUSION
In this paper, a new MIMO high step-up DC-DC converter is
proposed. The typical four-input-two-output of the converter is
presented to describe its operation. In the proposed converter,
the D-C VM stages can be utilized for each output port to
increase the output voltage levels and to decrease the
normalized voltage stress across the semiconductors. The
proposed converter benefits from the advantages of ability to
use different input power sources with various power and
voltage levels, the ability to operate in low/high power ranges,
the continuous current of the input sources, the various and high
output voltage levels and low voltage stress across the power
switches and diodes. In the proposed converter, if one or some
number of input sources are encountered failure, the other
inputs can provide their corresponding output loads and the
converter can continue its operation. To validate the proposed
converter operation, a 1kW four-input-two-output laboratory
prototype is built that its efficiency is approximately 95.96%.
Finally, the experimental results verified the converter
operation and theoretical calculations.
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[16] K. Varesi, S. H. Hosseini, M. Sabahi, and E. Babaei, "A high‐voltage In 1982, he joined the University of Tabriz as an
gain nonisolated noncoupled inductor based multi‐input DC‐DC Assistant Professor in the Department of Electrical Engineering. From
topology with reduced number of components for renewable energy September 1990 to September 1991, he was a Visiting Professor with
systems," Int. J. Circuit Theory and Appl., 2017. the University of Queensland, Brisbane, Australia. From 1990 to 1995,
[17] K. Varesi, A. A. Ghandomi, S. Hosseini, M. Sabahi, and E. Babaei, "An he was an Associate Professor at the University of Tabriz.
improved structure for Multi-Input high step-up DC-DC converters," in Since 1995, he has been a full Professor at the Department of Electrical
Power Electronics, Drive Systems & Technologies Conference Engineering, University of Tabriz. From September 1996 to September
(PEDSTC), 2017 8th, 2017, pp. 241-246: IEEE. 1997, he was a Visiting Professor with the University of Western Ontario,
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step-up DC–DC converter for hybrid energy systems," Electric Power East University of North Cyprus, Turkey. He is the author of more than
Syst. Research, vol. 149, pp. 111-124, 2017. 700 Journal and Conference papers. Being announced by the Thomson
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multiple-input multiple-output dc-dc converter for dc distribution of Influential Scientific Minds – 1% Top Scientist of the World. His research
future energy efficient homes," in Ind. Electron. Society, IECON 2014- interests include power electronics, application of power electronics in
40th Annual Conference of the IEEE, 2014, pp. 4126-4132: IEEE. renewable energy sources, power quality issues, harmonics and VAR
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multi-output DC-DC converter with the step up/down capability," in
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2013, pp. 5546-5552: IEEE. 1968. He received the B.Sc. degree in electronic
[21] H. Behjati and A. Davoudi, "Single-stage multi-port DC–DC converter engineering from the University of Tabriz, the
topology," IET Power Electron., vol. 6, no. 2, pp. 392-403, 2013. M.Sc. degree in electrical engineering from
[22] H. Behjati and A. Davoudi, "A multiple-input multiple-output DC–DC Tehran University, Tehran, Iran, and the Ph.D.
converter," IEEE Trans. Ind. Appl., vol. 49, no. 3, pp. 1464-1479, 2013. degree in electrical engineering from the
[23] M. Jafari, G. Hunter, and J. G. Zhu, "A new topology of multi-input University of Tabriz, in 1991, 1994, and 2009,
multi-output Buck-Boost DC-DC Converter for microgrid applications," respectively. In 2009, he joined the Faculty of
in Power and Energy (PECon), 2012 IEEE Int. Conf., 2012, pp. 286- electrical and computer engineering, University
291: IEEE. of Tabriz, where he has been an associate
[24] A. Nahavandi, M. T. Hagh, M. B. B. Sharifian, and S. Danyali, "A professor since 2015. His current research interests include power
nonisolated multiinput multioutput DC–DC boost converter for electric electronic converters and renewable energy systems.
vehicle applications," IEEE Trans. Power Electron., vol. 30, no. 4, pp.
1818-1835, 2015. Tohid Jalilzadeh was born in June 1992 in
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boost converter," IET Power Electron., vol. 9, no. 1, pp. 9-19, 2016. electrical engineering from Urmia University,
[26] S. H. Hosseini, P. Mohseni, and M. Sabahi, "An Extended High Step-Up Urmia, Iran, in 2014. He also received his M.Sc
Multi-Input DC-DC Converter", in Electrical and Electronics at power electronics from University of Tabriz,
Engineering (ELECO), 2017 10th Int. Conf., 2017 IEEE, pp. 285-289: Department of Electrical and Computer
IEEE. Engineering in 2016. He is currently Ph.D.
[27] M. A. Salvador, T. B. Lazzarin, and R. F. Coelho, "High Step-Up DC– degree at the Department of Electrical and
DC Converter With Active Switched-Inductor and Passive Switched- Computer Engineering, University of Tabriz
Capacitor Networks," IEEE Transactions on Industrial Electronics, vol. since 2017 Her research interests include Power
65, no. 7, pp. 5644-5654, 2018. Conversion (DC-DC & DC-AC), designing and controlling of power
[28] K.-C. Tseng, J.-Z. Chen, J.-T. Lin, C.-C. Huang, and T.-H. Yen, "High electronic converters, Hybrid Vehicles, Leakage Current Elimination,
step-up interleaved forward-flyback boost converter with three-winding Renewable applications.
coupled inductors," IEEE Transactions on Power Electronics, vol. 30,
no. 9, pp. 4696-4703, 2015. Mohammad Maalandish was born in September
[29] M. Maalandish, S. H. Hosseini, S. Ghasemzadeh, E. Babaei, R. S. 1990 in Marand (Yamchi), Iran. He received his
Alishah, and T. Jalilzadeh, "Six-phase interleaved boost dc/dc converter B.Sc. degree in electrical engineering from
with high-voltage gain and reduced voltage stress," IET Power Azarbaijan Shahid Madani University, Tabriz,
Electronics, vol. 10, no. 14, pp. 1904-1914, 2017. Iran, in 2013. He also received his M.Sc at power
[30] S. Danyali, S. H. Hosseini, and G. B. Gharehpetian, "New extendable electronics from University of Tabriz, Faculty of
single-stage multi-input DC–DC/AC boost converter," IEEE Electrical and Computer Engineering, Power
Transactions on power electronics, vol. 29, no. 2, pp. 775-788, 2014. Engineering Department, in 2016. Her research
interests include Power Conversion (DC-DC &
Parham Mohseni was born in March 1993 in DC-AC), designing and controlling of power
Urmia, Iran. He received his B.Sc. degree in electronic converters, MPC Method, Leakage Current Elimination,
power electrical engineering from Urmia Renewable Energies.
University, Urmia, Iran, in 2015. He also
received his M.Sc in power electronics from
University of Tabriz, Faculty of Electrical and
Computer Engineering in 2016. His research
interests include High Step-Up Power Electronic
Converters, Multi-Input-Multi-Output/Single-
Output Converters, Soft Switching, designing
and controlling of power electronic converters.

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