IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 25, NO.
4, OCTOBER 2010
Dynamic Performance of a Modular Multilevel
Back-to-Back HVDC System
Maryam Saeedifard, Member, IEEE, and Reza Iravani, Fellow, IEEE
Abstract—The modular multilevel converter (MMC) is a newly
introduced switch-mode converter topology with the potential
for high-voltage direct current (HVDC) transmission applica-
tions. This paper focuses on the dynamic performance of an
MMC-based, back-to-back HVDC system. A phase-disposition
(PD) sinusoidal pulsewidth modulation (SPWM) strategy, in-
cluding a voltage balancing method, for the operation of an MMC
is presented in this paper. Based on the proposed PD-SPWM
switching strategy, a mathematical model for the MMC-HVDC
system, under both balanced and unbalanced grid operation
modes, is developed. Dynamic performance of the MMC-based
back-to-back HVDC converter system, based on time-domain
simulation studies in the PSCAD/EMTDC environment, is then
evaluated. The reported time-domain simulation results show
that based on the adopted PD-SPWM switching strategy, the
MMC-HVDC station can respond satisfactorily to the system
dynamics and control commands under balanced and unbalanced
conditions while maintaining voltage balance of the dc capacitors.
Index Terms—Capacitor voltage balancing, HVDC transmis-
sion, modular multilevel converter, sinusoidal PWM.
I. INTRODUCTION
T HE SWITCH-MODE voltage-sourced converter (VSC) is
the building block for a specific class of HVDC converters
[1]–[5]. However, the requirement to meet high voltage levels,
both at ac and dc sides of a VSC-based HVDC converter sta-
tion, is best accommodated by the multilevel voltage synthesis
strategy (i.e., multi-module [6]–[8] and multilevel [2], [9], [10]
converters).
The multilevel VSC-based HVDC converters that have
been proposed and/or implemented, are mainly based on the
three-level diode-clamped converter (DCC) technology [2], [8],
[10]. Although technical merits of the n-level DCC for
HVDC applications are well understood [9], its applications,
due to the complexity in counteracting the dc-capacitor voltage
drift phenomenon, have been limited [11]. This is also the case
for multilevel flying-capacitor converter (FCC) topology [8].
Furthermore, DCC and FCC configurations do not fully satisfy
scalability, structural modularity, and fault tolerance for HVDC
Manuscript received September 04, 2009; revised January 28, 2010. Date of
publication September 07, 2010; date of current version September 22, 2010.
Paper no. TPWRD-00668-2009.
M. Saeedifard is with the School of Electrical and Computer Engineering,
Power and Energy Devices and Systems Group, Purdue University, West
Lafayette, IN 47907-2035 USA (e-mail: maryam@purdue.edu).
R. Iravani is with the Department of Electrical and Computer Engineering,
University of Toronto, Toronto, ON M5S 3G4, Canada (e-mail: iravani@ecf.
utoronto.ca).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPWRD.2010.2050787
0885-8977/$26.00 © 2010 IEEE
2903
applications. Although the multi-module VSC-based HVDC
converter provides modularity [6]–[8], it requires multiple
bulky transformers.
The modular multilevel converter (MMC) is a new and a
potential candidate for HVDC applications [12]–[16]. Concep-
tually, the MMC does not have the drawbacks of the multi-
level and multi-module converters. However, the MMC-HVDC
system has neither been comprehensively analyzed nor its con-
trol strategies and operational characteristics been adequately
investigated [12]–[15]. The main objective of this paper is to
investigate and evaluate dynamic behavior of the MMC in a
back-to-back connected HVDC system.
This paper presents: 1) a phase disposition (PD) sinusoidal
pulsewidth modulation (SPWM) strategy in conjunction with a
voltage balancing strategy for an MMC-based HVDC system
and 2) develops a comprehensive mathematical model to design
controllers of the overall MMC-based HVDC system. The de-
veloped model is based on the negative and positive sequence
decomposition technique [17] to study and control the MMC-
HVDC system under both balanced and unbalanced grid oper-
ating conditions. The performance of the MMC-based back-to-
back HVDC converter system, in terms of capacitor voltages
balancing and dynamic behavior, is also carried out based on
time domain simulations in the PSCAD/EMTDC environment.
The rest of this paper is organized as follows. Section II
introduces the HVDC study system. Section III introduces
the principles of operation of the MMC, the SPWM-based
switching strategy, and the dc-capacitor voltage balancing
method. Section IV present the HVDC converter station model
and the designed controllers. Section V reports the study re-
sults. Section VI provides further discussion on the subject, and
Section VII concludes this paper.
II. MMC-BASED HVDC SYSTEM STRUCTURE
Fig. 1(a) shows a single-line diagram of the study system
and Fig. 1(b) depicts a schematic representation of the
MMC-based HVDC system. The converter system comprises
two back-to-back connected MMCs which are hereinafter
referred to as MMC-1 and MMC-2. Each MMC consists of
six arms where each arm includes series-connected, nomi-
nally identical, half-bridge submodules (SMs). Without loss of
generality, in this paper, we assume . Reactors are to
provide current control within the phase arms and limit fault
currents. An estimate of the total switching loss of the converter
system is modelled by resistor that is connected in parallel
with the dc-bus, Fig. 1(b).
The ac terminal of each MMC is connected to a utility grid
through a series connected filter, a three-phase transformer. Two
2904 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 25, NO. 4, OCTOBER 2010

Fig. 1. Schematic representation of the MMC-HVDC system: (a) single-line diagram and (b) circuit diagram of the MMC-HVDC converter stations.

three-phase shunt filters installed at the low-voltage side of the TABLE I

transformer [Fig. 1(a)]. The shunt filters are either to trap dom- SWITCHING STATES OF A SUBMODULE OF FIG. 1
inant switching harmonics, or low-order harmonics. The syn-
chronization signal of the control for each MMC is obtained
from the low-voltage bus of the corresponding transformer.

of each SM are listed in Table I. There are two complimentary

III. MODULATION AND VOLTAGE BALANCING
switch pairs in each SM (i.e., and ).
STRATEGY OF AN MMC
To describe the operation of the MMC of Fig. 1(b), a func-
Each SM of the MMC of Fig. 1(b) consists of a half bridge tional diagram of one single MMC unit of Fig. 1 is shown by
cell where its output voltage (i.e., ) is either equal to its ca- Fig. 2 where SM switches are replaced by equivalent two-pole
pacitor voltage or zero, depending on the switching states. switches (i.e., for the SMs in the upper arm of phase and
The switching states and the resultant voltage at the output for the SMs in the lower arm). If is equal
SAEEDIFARD AND IRAVANI: DYNAMIC PERFORMANCE OF A MODULAR MULTILEVEL BACK-TO-BACK HVDC SYSTEM 2905

Fig. 3. PD SPWM strategy of the MMC of Fig. 1: (a) Carrier and reference
waveforms. (b) ac-side voltage levels.

Considering the point `` '' as the fictitious dc-side mid-point,

Fig. 2, the ac-side phase voltages , , are described
by

(3)

Based on (1) and (3), by controlling the switching functions of

the SMs in the upper and lower arm of each phase, the arm
Fig. 2. Circuit diagram of one MMC unit of Fig. 1. voltages and, as a result, the ac-side voltages are controlled in
discrete steps. The dc voltage of the MMC arms, in each phase,
is expressed by
to unity, the output of the th, , SM of the upper
(lower) arm of phase is equal to the corresponding
SM capacitor voltage; otherwise, it is zero. In principle, each
MMC arm represents a controllable voltage source which is de-
scribed by
(4)
(1a)
A. PWM Strategy
(1b) To synthesize a seven-level waveform at the ac-side of the
converter, a PD-SPWM strategy is applied [6], [18]. The PD
technique requires six in-phase carrier waveforms displaced
where and denote the total voltage of the upper and symmetrically with respect to the zero-axis [11]. Fig. 3(a) illus-
lower arms of phase , respectively. The arm currents are de- trates the PD-SPWM waveforms of phase-a of the seven-level
scribed by MMC of Fig. 1(b). By comparing a sinusoidal reference wave-
form with the six carrier waveforms, Fig. 3(a), the voltage level
(2a) at the ac-side of the MMC is determined [Fig. 3(b)]. To extend
the linear operating range of the SPWM strategy and increase
(2b) the fundamental component of the ac-side line voltages of the
MMC, a third-harmonic component is also included in the
where , are the circulating currents which circulate modulating reference signal, as shown in Fig. 3.
within the three phases of the MMC and . In the MMC of Fig. 2, the switching functions and
The circulating currents have no effect on the dc- and/or ac-side are controlled so that at any instant
of the converter. However, they have a significant impact on the , as shown in Fig. 2. This implies that at each
rating values of the MMC components and the SM capacitor instant only six SMs out of the twelve SMs of phase are on
voltage ripples. (i.e., SMs in the upper arm and in the
2906 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 25, NO. 4, OCTOBER 2010

lower arm). The values of and are determined by

the desired voltage level of phase from the PD-SPWM modu-
lator. Assuming that each SM capacitor voltage is regulated at
, a seven-level waveform at the ac-side of phase
with respect to the mid-point is synthesized as follows:
• For voltage level 1, , all of the six upper
(lower) SMs are off (on) (i.e., and ).
• For voltage level 2, , out of six upper SMs,
one is on and out of six lower SMs, five are on (i.e.,
and ).
• For voltage level 3, , out of six upper SMs,
two are on and out of six lower SMs, four are on (i.e.,
and ).
• For voltage level 4, , out of six upper SMs, three
are on and out of six lower SMs, three are on (i.e.,
and ).
• For voltage level 5, , out of six upper SMs,
four are on and out of six lower SMs, two are on (i.e.,
and ).
• For voltage level 6, , out of six upper SMs,
five are on and out of six lower SMs, one is on (i.e.,
and ).
• For voltage level 7, , all of six lower (upper)
SMs are off (on) (i.e., and ).

B. Selection of SMs and Capacitor Voltage Balancing

Similar to multilevel topologies, the capacitor voltages of
the individual SMs must be monitored and kept equal [13]. The
PD-SPWM strategy determines the number of SMs that should
be on in the upper and lower arms of the MMC (i.e., and
). As discussed in the previous section, for a specified
number of SMs in the upper and lower arms (i.e.,
there are several switching combinations. Capacitor voltage
values and also the direction of the arm currents are used to
select of the six SMs in the upper (lower) arm and
to determine which SMs should be switched on.
When the current in the upper (lower) arm is positive, if a SM
in the arm is on, the corresponding capacitor will be charged and
its voltage increases. When the current in the upper (lower) arm
is negative, the capacitor of a SM is discharged and its voltage
decreases. Regardless of the direction of the upper (lower) arm
current, if a SM in the arm is off, the corresponding capacitor
will be bypassed and its voltage remains unchanged. To carry
out the capacitor voltage balancing task of the SMs of each
arm, during each PD-PWM period, the SM capacitor voltages
of each arm are measured and sorted in descending order. If
the upper (lower) arm current is positive, out of six SMs of
the corresponding arm, of the SMs with the lowest
voltages are identified and switched on. Consequently, the cor-
responding SM capacitors are charged and their voltages in-
crease. If the upper (lower) arm current is negative, out of six
SMs of the corresponding arm, of the SMs with the
highest voltages are identified and switched on. Consequently,
the corresponding SM capacitors are discharged and their volt-
ages decrease. The corresponding switching functions of each
SM, , is “1,” when it is on. Otherwise, it is “0”. The proce-
dure to implement the PD-SPWM-based balancing strategy is
summarized in the diagram of Fig. 4.
Fig. 4. Block diagram of the per-phase PD-SPWM strategy including SM ca-
pacitor voltage balancing strategy for the MMC of Fig. 1.
),
IV. MATHEMATICAL MODEL OF THE HVDC SYSTEM
Without loss of generality, the dynamic model of the HVDC
system is developed based on the assumption that the nominal
voltage amplitudes of both ac systems are the same. However,
their phases and frequencies are not required to be the same.
Hereinafter, to avoid repetitions in the formulation, the quanti-
ties of MMC-1 and ac System-1 are indexed by “1” and those
of MMC-2 and ac System-2 are indexed by “2”.
A. System Model
This section develops a mathematical model for the MMC-
HVDC system of Fig. 1 to systematically design the controllers
for the net dc-bus voltage regulation and power flow control
under both balanced and unbalanced ac systems operating con-
ditions.
The voltages at the ac-side of the MMC-k terminals are
(5)
where represents the ac-side voltages of MMC-k
and the represents the SPWM modulating signals.
In a SPWM strategy in which the modulating waveforms of
the three-phases are not balanced (with no zero-sequence),
SAEEDIFARD AND IRAVANI: DYNAMIC PERFORMANCE OF A MODULAR MULTILEVEL BACK-TO-BACK HVDC SYSTEM 2907

the modulating waveforms are decomposed into positive- and The dc-bus voltage dynamics are expressed based on the power
negative-sequence components, described by balance equation. For the system of Fig. 1, the instantaneous
outgoing power from the ac-side terminals of MMC-k is [17]

(6a) (14)

where

(6b) (15a)

(6c) (15b)

where and are the amplitudes of the positive- and neg-

ative- sequence components of the , respectively.
are the rotating angles of in Fig. 1, and pro- (15c)
vided by the corresponding PLLs. To analyze the MMC trans-
mission system under both balanced and unbalanced grid opera-
tion, the three-phase voltages and currents are decomposed into
positive- and negative-sequence components by [5] (15d)

(7) Assuming that both MMCs operate at unity power factor (i.e.,
) and the PCC-1 is subject to a single-phase to ground
(8a)
fault, we have
(8b)
(16a)
where

(9)
(16b)
Substituting for from (6) in (5), and transforming the
positive and negative sequence of based on (8), we have

(10a) (16c)

(10b)
(16d)
(11a)
and
(11b)
(17a)
The amplitudes and phases of the sequence components of the
modulating waveforms are (17b)
(17c)
(12a) (17d)

B. AC-Side Current Control of the MMC-Based HVDC System

(12b)
The dynamics of the MMC ac-side variables, in terms of their
-frame components, are expressed as
(13a)
(18a)

(13b) (18b)
2908 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 25, NO. 4, OCTOBER 2010

TABLE II
(19a) PARAMETERS OF THE STUDY SYSTEM OF FIG. 1

(19b)

The system described by (18) and (19) can be visualized as

decomposition into the “positive sequence subsystem” and the
“negative sequence subsystem.” Current control loops are de-
veloped to regulate , , , and at their corresponding
desired values. The positive-sequence current controllers, which
control and are used for the dc-bus voltage regulation
and the reactive power control of the system. The negative se-
quence current controllers, which control and , can be
used to keep either the ac-side currents balanced or to elimi-
nate the dc-bus double line-frequency ripple. The principles of
the sequence current controller design are explained in detail in
[17].
Equation (20) in conjunction with (22)–(24) describes dynamics
C. DC-Bus Voltage Control
of the dc-bus voltage of Fig. 1. The dc-bus voltage controller is
The dc-bus voltage dynamics of Fig. 1 are described by designed based on the procedures explained in [17] and is not
repeated here.
(20)
V. STUDY RESULTS
where is the equivalent capacitance of each MMC.
Substituting for and from (14) in (20), we have A. Study System
The HVDC system of Fig. 1(a), based on the PD-SPWM
strategy of Section III and in conjunction with the control
system described in Sections IV-B and C, is simulated in the
PSCAD/EMTDC environment. Table II provides parameters of
the system of Fig. 1(a) used for the reported studies. The sim-
(21) ulated test cases evaluate dynamic performance of the overall
system of Fig. 1(a), including power and control subsystems,
We define the -axis current references and as
under various conditions.
(22a)
B. Case Studies
(22b)
1) Real/Reactive Power Control Under Balanced AC Systems
where is the current command corresponding to the de- Operation: Initially, the system is in a standby mode of op-
sired power exchange between ac System-1 and ac System-2. A eration (i.e., zero power transfer) and is set to 60 kV.
positive indicates a positive power flow command from Both MMCs operate at unity power factor. Both ac systems are
ac System-1 to ac System-2, and vice versa. commands balanced; therefore, . At , is
small real current components to be drawn from both ac systems ramped up within 12.5 ms, corresponding to power flow from
to compensate for the losses represented by , to regulate the 0 to 25 MW, from ac System-1 to ac System-2. Reactive power
dc-bus voltage. Thus, the responses of the current controllers of demands of both ac systems are step changed, at 0.4 s from
Section IV-B to the commands (22) are 0 to for ac System-1, and at from 0 to 18
MVAr for ac System-2. Fig. 5 shows the dynamic response of
(23a) the system to the changes in real and reactive power commands.
(23b) Fig. 5(a) and (b) shows changes in real and reactive cur-
rent components of ac System-1 and ac System-2, respectively,
where to meet the real and reactive power demands in response to
changes in , , and . Fig. 5(c) and (d) shows
(24a) that the real and reactive power exchange of ac System-1 and ac
(24b) System-2 are proportional to the real and reactive current com-
ponents of Fig. 5(a) and (b), respectively.
and is Fig. 5(e) and (f) shows the zoomed portions of the line-to-line
terminal voltage of the MMC-1 and MMC-2, respectively. The
(25) line-to-line terminal voltages of Fig. 5(e) and (f) show relatively
sinusoidal multilevel waveforms with very low total harmonic
SAEEDIFARD AND IRAVANI: DYNAMIC PERFORMANCE OF A MODULAR MULTILEVEL BACK-TO-BACK HVDC SYSTEM
Fig. 5. Dynamic response of the system of Fig. 1 to changes in real and re-
active power commands: (a) real and reactive current components of MMC-1,
(b) real and reactive power components of MMC-1, (c) real and reactive current
components of MMC-2, (d) real and reactive power components of MMC-2, (e)
and (f) ac-side voltages of MMC-1 and MMC-2, (g) and (h) capacitor voltages
of phase-a SMs of MMC-1 and MMC-2, and (i) net dc-bus voltage.
distortions. Fig. 5(g) and (h) shows the capacitor voltages of
the individual SMs of phase-a of MMC-1 and MMC-2, respec-
tively. As Fig. 5(g) and (h) shows, the capacitor voltages are
kept balanced at their nominal values, i.e., 10 kV, under tran-
2909
sient and steady-state conditions. This confirms that capability
of the PD-SPWM-based balancing strategy to maintain the ca-
pacitor voltages balanced. Fig. 5(i) shows the net dc-bus voltage
response and illustrates that the net dc-link voltage, subsequent
to the disturbances, is well regulated.
Fig. 5 illustrates that the control system effectively controls
the system operating conditions in response to the changes in
power demands. Fig. 5 also highlights the effectiveness of the
SPWM-based capacitor voltages balancing strategy.
2) Real-Power Flow Reversal Under Balanced AC System
Operation: Initially the system is in the standby mode of oper-
ation and is set to 60 kV. In this case study also both ac
systems are balanced; therefore, . Both MMC-1
and MMC-2 are operating at unity power factor. At ,
is ramped up from 0 to 1.09 kA within 12.5 ms, corre-
sponding to a power flow change from 0 to 40 MW, from ac
System-1 to ac System-2. At , is ramped from
1.09 kA to within 25 ms. This change corresponds
to a power flow reversal from 40 MW to , from ac
System-1 to ac System-2.
Fig. 6(a) shows changes in and due to the changes
in real power exchange and real power reversal command. Fig.
6(b) shows the corresponding changes in and , respec-
tively. As Fig. 6(a) and (b) shows, real current components of
both ac systems and consequently real power components are re-
versed as the real power exchange and real power reversal com-
mands are activated. Fig. 6(c) and (d) shows phase-a currents
of ac System-1 and ac System-2, respectively. Fig. 6(c) and (d)
shows that the currents change their phases during the power
flow reversal period. Fig. 6(e) and (f) shows the capacitor volt-
ages of the phase-a SMs of MMC-1 and MMC-2, respectively,
which are kept balanced at their nominal values. Fig. 6(g) shows
the net dc-bus voltage response and demonstrates that the net
dc-link voltage subsequent to real power reversal command is
well regulated.
Fig. 6 indicates that the control system properly tracks the
real power exchange and real power reversal command and the
operating conditions are well controlled in response to the power
demand.
3) DC-Bus Voltage Change Under Balanced AC System Op-
eration: Initially, is set to 60 kV and 40 MW of power
flows from ac System-1 to ac System-2. Both MMCs operate at
unity power factor. At , is stepped down 10%
(i.e., from 60 kV to 54 kV). At , is stepped up
from 60 kV back to 54 kV. The system response to the foregoing
events is shown in Fig. 7. Fig. 7(a) shows the dc-bus voltage
which in response to the ramp command, is changed and set at
the reference value. Fig. 7(b) and (c) demonstrates the capac-
itor voltages of phase-a SMs of MMC-1 and MMC-2 which are
set at their nominal values (i.e., ). Fig. 7(b) and (c) veri-
fies the capability of the proposed PD-SPWM-based balancing
strategy to regulate and maintain the SMs capacitor voltages
at their nominal values. Fig. 7(d) illustrates the corresponding
changes in the real power flow (i.e., and ). Within the time
period of to , as decreases, the real power
flow from ac System-1 to ac System-2 remains constant.
4) Single-Phase-to-Ground Fault: The objective of this case
study is to investigate the behavior of the HVDC system of Fig.
2910
Fig. 6. Dynamic response of the system of Fig. 1 to a real power reversal com-
mand: (a) real current components of ac System-1 and ac System-2, (b) real
power components of ac System-1 and ac System-2, (c) and (d) phase-a cur-
rents of ac System-1 and ac System-2, (e) and (f) capacitor voltages of phase-a
SMs of MMC-1 and MMC-2, and (g) net dc-link voltage.
1 under a temporary single-phase-to-ground fault. The system
of Fig. 1 is initially in a steady-state operating condition. Both
MMCs operate at unity power factor and 40 MW real power
flows from ac System-1 to ac System-2. A line to ground fault,
at is imposed on PCC-1 which lasts for 200 ms. To
keep the ac-side currents of MMC-1 balanced during the fault,
at , the negative-sequence current commands (i.e.,
and ) are set at zero to regulate and at zero.
Hereinafter, the term “post-fault strategy” refers to the control
action corresponding to and at zero. Fig. 8 shows
the transient behavior of the system during and subsequent to
the fault.
IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 25, NO. 4, OCTOBER 2010
Fig. 7. Dynamic response of the system of Fig. 1 to ramp changes in dc-bus
voltage: (a) net dc-bus voltage, (b) and (c) capacitor voltages of phase-a SMs
of MMC-1 and MMC-2, and (d) real power components of ac System-1 and ac
System-2.
Fig. 8(a) shows the three-phase voltages subsequent
to the fault event. Fig. 8(b) shows the corresponding changes in
real power components of ac System-1 and ac System-2, respec-
tively. Fig. 8(c) shows the ac-side voltages MMC-1. Fig. 8(d)
and (e) shows the negative sequence current components (i.e.,
and ), and three-phase ac-side currents of MMC-1, re-
spectively. When the HVDC system of Fig. 1 is subjected to the
fault and no post-fault strategy is activated (i.e., from
to ), the MMC-1 is operating with the balanced SPWM
strategy and its generated ac-side voltages remain balanced, as
shown in Fig. 8(c). As a result, due to the presence of non-zero
negative sequence current components (i.e., and shown
in Fig. 8(d)), the ac-side currents of the MMC-1 become unbal-
anced from to [Fig. 8(e)].
When the post-fault strategy is active, the negative sequence
current components, as shown in Fig. 8(d), are reduced to zero
and keep the ac-side currents of Fig. 8(e) balanced. Based on
Fig. 8(b) and (f), the power and capacitor voltage ripples of the
phase-a SMs subsequent to the fault, within the time period of
to are larger that those within the time period
of to . This is due to the presence of the neg-
ative sequence current components when no post-fault strategy
is adopted. Fig. 8(f) also shows the capability of the proposed
PD-SPWM-based balancing strategy to control the capacitor
voltages under the severe unbalanced condition. Fig. 8(g) and
(h) indicates the ac-side voltages and the capacitor voltages of
SMs of the MMC-2, despite the fault, remain balanced. Fig. 8(i)
also indicates the net dc-bus voltage is well regulated at 60 kV.
Subsequent to the fault, in particular within the time period of
to , due to the presence of negative sequence
SAEEDIFARD AND IRAVANI: DYNAMIC PERFORMANCE OF A MODULAR MULTILEVEL BACK-TO-BACK HVDC SYSTEM
Fig. 8. Dynamic response of the system of Fig. 1 to a line-to-ground fault at
PCC-1: (a) three-phase line voltages at the low voltage side of the transformer-1,
(b) real power components of MMC-1 and MMC-2, (c) three-phase voltages of
MMC-1, (d) negative sequence current components of MMC-1, (e) three-phase
ac-side currents of MMC-1, (f) capacitor voltages of phase-a SMs of MMC-1,
(g) three-phase voltages of MMC-2, (h) capacitor voltages of phase-a SMs of
MMC-2, and (i) net dc-bus voltage.
current components, double line-frequency oscillations appear
on the net dc-bus voltage.
Fig. 8 indicates that the HVDC system of Fig. 1 prevents
propagation of the fault transients of the ac System-1 to ac
2911
System-2. Fig. 8 shows that the post-fault strategy is able to
correct the HVDC system response to the single line-to-ground
fault and keep the ac-side currents balanced during the fault.
VI. DISCUSSIONS
In comparison with the reported multilevel and/or
multi-module converter-based HVDC systems [5], [6], [8],
[17], the HVDC converter configuration of Fig. 1 offers the
following features:
• Compared with the DCC-based HVDC system of [9], the
system of Fig. 1 requires a two-wire connection at the
dc side. The HVDC converter system of [9] necessitates
a five-wire connection between the two converters which
disqualifies it for point-to-point, long-distance dc transmis-
sion. The MMC-based HVDC converter system of Fig. 1
can be adopted for long-distance dc transmission.
• Compared with the series-connected configuration [6] and
[7], the converter system of Fig. 1 eliminates the need for
multiple transformers. The transformer system is a major
cost component in HVDC applications, and the MMC con-
verter system of Fig. 1, in this respect, can offer cost incen-
tives compared with the system of [6] and [7].
• The MMC-based HVDC system of Fig. 1 has a highly
modular converter structure and provides scalability to the
desired voltage/power requirement. This is a salient fea-
ture when compared with the multilevel converter-based
HVDC configuration [5], [6], [8], [17].
• By increasing the number of SMs, and without additional
complexity in the control, low-distortion voltage wave-
forms can be synthesized at the ac-side of the MMC. An
adequate number of converter SMs obviates the need for
characteristic shunt ac filters, simplifies the converter struc-
ture, and reduces the cost and footprint of the station.
VII. CONCLUSION
This paper studies a back-to-back VSC-HVDC transmission
system based on a seven-level MMC converter. The paper
presents and evaluates a PD-SPWM-based capacitor voltage
balancing strategy for the HVDC system. This paper also
develops a mathematical model for the HVDC system to design
the controllers to control power flow and regulate the net dc-bus
voltage, under balanced and unbalanced grid conditions. The
capability of the SPWM-based voltage balancing strategy, per-
formance of the designed controllers, and the overall dynamic
performance of the HVDC system are investigated. The studies
are conducted in time-domain using the PSCAD/EMTDC sim-
ulation environment. The study results demonstrates that the
MMC, based on appropriately designed controllers, provides
the desired dynamic response, under balanced and unbalanced
grid conditions, for HVDC system applications. The studies
also show that the proposed PD-SPWM strategy can effectively
provide voltage balancing for the MMC capacitors under
steady-state and dynamic operational conditions. Furthermore,
the inherent scalability of the MMC renders it as a promising
configuration, compared with the multi-level and multi-module
VSC configurations, for HVDC system applications.
2912
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Maryam Saeedifard (M’08) received the Ph.D. de-
gree in electrical engineering from the University of
Toronto, Toronto, ON, Canada, in 2008.
From 2007 to 2008, she was a Visiting Research
Associate with the Power Electronic Systems Group,
ABB Corporate Research Center, Dättwil-Baden,
Switzerland. Subsequent to her graduation, she
joined the Center for Applied Power Electronics
in the Department of Electrical and Computer
Engineering at the University of Toronto, as a
Postdoctoral Fellow. Currently, she is an Assistant
Professor at Purdue University, West Lafayette, IN. Her research interests
include power electronics and applications of power electronics in power
systems.
Dr. Saeedifard was the recipient of the NSERC Postdoctoral Fellowship of the
Government of Canada in 2008 and the Richard M. Bass Outstanding Young
Power Electronics Engineer award of the IEEE Power Electronics Society in
2010.
Reza Iravani (F’03) received the B.Sc. degree
in electrical engineering from Tehran Polytechnic
University, Tehran, Iran, in 1976, and the M.Sc.
and Ph.D. degrees in electrical engineering from the
University of Manitoba, Winnipeg, MB, Canada, in
1981 and 1985, respectively.
Currently, he is a Professor at the University of
Toronto, Toronto, ON, Canada. His research interests
include power electronics and applications of power
electronics in power systems.