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A novel spice model of photodetector

for OEIC design

Bian, Jiantao, Cheng, Xiang, Chen, Chao

Jiantao Bian, Xiang Cheng, Chao Chen, "A novel spice model of
photodetector for OEIC design," Proc. SPIE 6621, International Symposium
on Photoelectronic Detection and Imaging 2007: Photoelectronic Imaging and
Detection, 66211E (3 March 2008); doi: 10.1117/12.790834

Event: International Symposium on Photoelectronic Detection and Imaging:

Technology and Applications 2007, 2007, Beijing, China

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 A Novel Spice Model of Photodetector for OEIC Design

BIAN Jiantaoa,b, CHENG Xiangb, CHEN Chaob

a
Dept. of Information Science, Jiangsu Polytechnic Univ., Changzhou, Jiangsu, P.R.China, 213164
b
School of Physics and Mechanical & Electrical Engineering, Xiamen Univ./City, Fujian, P.R.China,
361005

ABSTRACT

Silicon monolithically Optoelectronic Integrated Circuit (OEIC) designed in standard CMOS process has been gradually
applied. But Spice models of opticalelectronic devices such as photodetector can not be provided by IC manufactories in
OEIC design. A novel Spice model of photodetector is introduced for compatible-design of OEIC in this paper. An
N+/N-Well/P-Sub photodetector in standard CMOS process is described. The model of CMOS photodetector is
completely based on Hspice EDA design software. It includes optical current, dark current, junction capacitor, series
resistor, parallel resistor, and even noise characteristic. A four-terminal network structure is utilized to take the place of
the photodetector in the model. The whole model can be easily applied to OEIC design as a subcircuit. At 780nm
wavelength, the characteristics of the N+/N-Well/P-Sub photodiode fabricated in 0.5µm CMOS process are simulated
with the Spice model and tested. With a reverse bias of 2.5V, the measured and simulated responsivity is both about
0.25A/W, which indicates the availability of the model. Finally, the compatible-design of OEIC used for optical pickup
unit in optical storage system has been accomplished with the novel photodetector model.

Keywords: Applied optoelectronics, Photodetector, Spice model, CMOS

1. INTRODUCTION

Silicon photodetector can be applied to many fields such as optical storage system pickup unit, 850nm and 650nm optical
fiber communication receivers, and so on. It can be integrated with Silicon IC to get monolithically Optoelectronic
Integrated Circuit (OEIC) in standard CMOS process, whose advantages lie in the supplies from the various functional
ICs and the low cost. References [1-3] have given many reports about it.
Spice models of devices are the basics of IC and OEIC design, but the models of opticalelectronic devices such as
photodetector can not be provided by IC manufactories. There have been several kinds of photodetector spice models4-6.
However, the existing Spice models of photodetector have some disadvantages, such as large noise due to equivalent
resistors, neglect of dynamic characteristic, and so on. Therefore, a novel Spice model of photodetector is introduced for
compatible-design of OEIC in this paper. In order to describe the model, an N+/N-Well/P-Sub photodetector in standard
CMOS process is used. The model of CMOS photodetector is completely based on Hspice EDA design software. It
includes optical current, dark current, junction capacitor, series resistor, parallel resistor, and even noise characteristic. A
four-terminal network structure is utilized to take the place of the photodetector in the model. The whole model can be
easily applied to OEIC design as a subcircuit. The characteristics of the N+/N-Well/P-Sub photodiode fabricated in

International Symposium on Photoelectronic Detection and Imaging 2007:

Photoelectronic Imaging and Detection, edited by Liwei Zhou, Proc. of SPIE Vol. 6621, 66211E, (2008)
0277-786X/08/$18 · doi: 10.1117/12.790834

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 0.5µm CMOS process are simulated and tested at 780nm wavelength. At last, the compatible-design of OEIC used for
optical pickup unit in optical storage system has been accomplished with this photodetector model.

2. STRUCTURE AND OF NOVEL SPICE MODEL PHOTODETECTOR

2.1 Structure of CMOS photodetector

The photodetector with N+/N-Well/P-Sub structure can be compatibly fabricated in standard CMOS process. The
structure of the photodetector in twin-well CMOS technology is shown as Fig.1(a). The N+/N-Well high-low junction
structure is utilized to reduce surface recombination7. The insulated medium layers (SiO2 and Si3N4) in CMOS
technology are not shown in Fig.1(a). Here, P type wafer with doping concentration near 1015cm-3 is used as the substrate.
By ion implantation technology, the N-Well and P-Well are made for both CMOS IC and photodetector. N+ and P+ are
used as the cathode and anode of photodetector, respectively. These electrodes are realized by normal source/drain
implantation.

—
I
od:ceLLLILrn
I ' — N N-*ell
X\\fl X\\p

P-Sub
I I

N—Well XJ I
Lc7 I I

Jieiv' P—Sub P—Wej,

if'
Incident
light
d:d2 Xj Xw J
xs xi x11

(a) Structure of CMOS N+/N-Well/P-Sub Photodetector (b) Physical model of CMOS N+/N-Well/P-Sub Photodetector
Figure 1: Structure and physical model of CMOS photodetector
The physical model of the photodetector is given in Fig.1(b). There are several layers in this model, including insulated
medium and passivation layers (SiO2 & Si3N4, acting as ARC), N+, N-Well and P substrate from left to right. xs, xn and xB
are the thickness of N+, N-Well and P-substrate, respectively. xw is the depletion region thickness of N-Well/P-substrate,
which abides by the relationship8 as equation (1):

2ε s N A + N D 2 KT
xw = ( )(Vbi − −V ) (1)
q N AND q

KT N N
where ε s is the permittivity of silicon，and Vbi = ln( A 2 D ) is the built-in potential. NA and ND are the doping
q ni
concentration of P-substrate and N-Well, respectively. V is the reverse bias voltage.

2.2 Spice model of photodetector

In modern EDA software, there is no exiting spice model for photodetector. So an equivalent circuit is used to instead of
the real photodetector. The equivalent circuit of photodetector can be described as a four-terminal network structure. It is
shown as Fig. 2. The voltage difference between Popt+ and Popt- terminals is utilized to take the place of the incident light
power, which is not included in electronic elements. The right terminals are the cathode and anode of photodetector. In
Fig.2, Iopt and Idark are the optical current and dark current of photodetector, respectively. CPD represents the junction

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 capacitance. Rsh and Rs represent the parallel resistance and series resistance, respectively. I n2 represents the shot noise.

2 2
The thermal noise of parallel resistance and the one of series resistance are shown as I Rs and I Rsh . The frequency

characteristic of photodetector is realized by a first-order system, which is constructed by Ieq, Ceq and Req. In order to
2
realize the shot noise, the resistance Rnoi is applied and its thermal noise is transformed to I n by current controlled

current source(CCCS) technology.

Fopt+ C /

Foptp p

Figure 2: Equivalent circuit of N+/N-Well/P-Substrate photodetector

The Hspice software is one of the famous EDA software. It provides strong function of circuit description. Depended on
the functions of parameter definition, voltage controlled current source(VCCS) and CCCS in Hspice, the equivalent
circuit in Fig.2 can be defined as a subcircuit. And the main function elements of above model are described as follows.
(1) Optical current model
For OEIC design and application with photodetector, the photodetector is not only used in steady-state but also in
dynamic-state conditions. So the model of photodetector should include these two optical current models. In Fig.2, the
steady-state optical current model is described as Ieq, and the other is described as Iopt.

I eq = ℜ es [V ( Popt + ) − V ( Popt − )] (2)

I opt = I Re q = I eq /(1 + jωReqCeq ) (3)

where ℜ es is the spectral responsivity in steady-state, which can be obtained as the method described in reference [9].

Ceq and Req are the equivalent elements, and they have the relationship with the -3dB frequency of photodetector as
follows:

1
= 2π ⋅ f −3dB (4)
ReqCeq
Ceq, Req and f-3dB are all affected by the bias voltage. The -3dB frequency of photodetector, f-3dB, is determined by the
following equality10.

2 .4 2 .4
f −3dB = ≈ (5)
2πt r 2π × 2.2(t N −Well + t P2 −Sub + t depl
2 2
)1 / 2

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 x12 xw l 2τ
t N −Well = , tdepl = , t P − Sub = 2 B n 2 (6)
2.43D p 2.8υ s lB + (πLn )
where lB is the effective length of the P-substrate. It is chosen where the incident light power reduces to 10% or less. In

order to reduce the thermal noise of the Req resistor, Req is selected as 109Ω.

(2) Junction capacitance model

The influence of the lateral capacitance is neglected, and the junction capacitor of photodetector can be described as a
plate capacitor. It is expressed as Eq.(7).

ε s A0 ε s qN A N D
C PD = = A0 (7)
xw 2( N A + N D )(Vbi − 2 KT / q − V )

where ε s and A0 are the dielectric coefficient of Silicon and optical window area, respectively.

(3) Dark current model

Because of low reverse bias voltage, the influence of tunnel current on the whole dark current can be neglected. The dark
current is mainly due to the diffusion current contributed by the thermal-equilibrium carriers in undepletion regions, the
generation-recombination current in depletion region, and the surface recombination current. According to the spectral
response analysis in steady-state condition, the former can be described as follows.

 qV 
I diff = A0 J 0 exp( ) − 1 (8)
 KT 

( D p / L p ) sh( x j / L p ) + S nn+ sh( x j / L p ) qDn n p 0 x B − x2

where J 0 = − qD p pn 0 − cth( ) is the reverse saturation
D p ch( x j / L p ) + S nn+ L p sh( x j / L p ) Ln Ln

current density. S nn+ is the surface high-low junction leakage velocity surface recombination velocity 9.

According to the SNS equation11, the generation-recombination current in depletion region can be written as follows:

A0 qni xw  qV 
I g −r = 1 − exp( ) (9)
τ eq  2kT 

where τ eq = τ n + τ p is the effective carrier-life.

The surface recombination current12 is express as I sf = A0 qS0 ∆ n = A0 qni S 0 / 2 . (10)

And S0 is the carrier recombination velocity on N+ surface. If the Silicon device is passivited by SiO2 layer and the
doping concentration of N+ surface, ND, is larger than 1018cm-3, the surface recombination velocity12 will be about
10-16*ND.

The whole dark current is expressed as I dark = I diff + I g −r + I sf . (11)

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 (4) Resistance model
There are parallel resistance and series one in the photodetector model. The former is the dynamic resistance in the
condition of zero bias and lightless, whose relationship with the reverse saturation current is expressed as Eq.(12).

dV KT
Rsh = ( ) V =0 = (12)
dI Popt =0 qA0 J 0

And it is difficult to obtain the series resistance by numerical calculation directly. Whereas it can still be calculated from
the diode or transistor spice model provided by IC manufactories if a standard process is used.
(5) Noise model
2 2
The thermal noise spectrum densities of series and parallel resistance are I Rs and I Rsh , which are included in EDA

2
software. But the shot noise spectrum density, I n , should be specially defined. In this model, the thermal noise

2 2
spectrum density of Rnoi, I Rnoi , is set to be equal to I n . And the voltage source, namely Vnoi, is zero. The shot noise

spectrum density can be expressed as I n2 = 2q( I opt + I dark ) , so Rnoi = 2 KT /[q( I opt + I dark )] .

3. SIMULATION AND TESTED RESULS

The N+/N-Well/P-Sub photodetector with an optical window area of 50×50µm2 is simulated and fabricated in 0.5µm

standard CMOS process. The Fig.3(a) gives the simulated optical current with an load resistance of 50Ω. And the
short-circuit current of photodetector is tested by Aglilent Muletimeter. The responsivity derived from the optical current
is shown as Fig.3(b). The light wavelength is 780nm and incident light power is 10µw. With a reverse bias of 2.5V, the
simulated and measured responsivity at 780nm wavelength are about 0.251A/W and 0.253A/W, respectively. The
measured results match with the simulated ones, which indicates the availability of the model. And the variation of

optical current with reverse voltage is also taken into consideration in the novel model. It is about 2mA/(W·V) in both

the simulated and tested results. The capacitance of photodetector is measured, too. Its unit area capacitance is about 5.5

×10-5pF/µm2. The dark current of photodiode is less than 0.15nA.

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 0.260

Responsivity (A/W)
0.255

0.250

0.245
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Reverse Bias (V) Reverse Bias (V)

(a) (b)
Figure 3: Simulated optical current and tested responsivity
4. DESIGN OF CMOS OEIC

An OEIC is often made up of photodetector and various integrated circuits. In Fig.4, the OEIC is an optical receiver
composed of a photodetector and a transimpedance amplifie. A three-stage CMOS push-pull inverter is designed as

open-loop amplifier for the transimpedance. If the open-loop gain is A and its bandwidth is ideal ( WT =∞), the –3dB

bandwidth of the OEIC can be expressed as:

1 1+ A
BW = (13)
2π R f C PD + (1 + A) R f C f
where Cf is the compensation capacitance, which is used to avoid gain-peaking or guarantee stability and is much
smaller than junction capacitance of photodetector.

N15

Figure 4: Schematic of CMOS optical receiver

A complementary self-bias differential amplifier(CSDA)13 is used in the first stage, which will stabilize the static
operation point and reduce output offset since the feedback of the CSDA. MN11, MN22, MN33 and M44 are used to
limit the gain of every stage for stability requirement. MP7 and MP8 are the output stage. The novel photodetector spice
model analyzed above is utilized to take the place of photodetector in the simulation of OEIC.

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 ::::::::::::::::::

iou ik ii lebk ik
Frequency (Hz)
lo] !
Figure 5: Frequency response of CMOS optical receiver
Fig.5 is the Hspice simulated results in 0.5µm CMOS technology. With incident light of 780nm wavelength, the OEIC
reaches a bandwidth of 17.5MHz and a gain of 91.1dB (about 35.9mV/µW) with a 10pF load-capacitor and a 10KΩ
load-resistor. This circuit can be used for CD optical-disc signal pickup. The whole low bandwidth is limited by the
intrinsic bandwidth of photodetector.

5. CONCLUSIONS

The N+/N-Well/P-Substrate photodetector discussed in this paper can be used to realize monolithic OEIC in standard
CMOS technology without process step or condition modification. A novel spice model of photodetector is studied in
detail. With a reverse bias of 2.5V, the simulated and measured responsivity of photodetector at 780nm are about
0.251A/W and 0.253A/W, respectively. The co-design of monolithic OEIC is also discussed. A full CMOS monolithic
OEIC based on this novel photodetector spice model is designed for optical storage system. With incident light of 780nm
wavelength, the bandwidth of OEIC reaches 17.5MHz with the gain of 91.1dB under a 10pF load-capacitor and a 10KΩ
load-resistor.

ACKNOWLEDGES

This work is supported by the Leading Research Project for Special Research Program of Fujian Province

(NO:2005HZ1017 )，the Natural Science Foundation of Fujian Province (NO:2006J0241), and the Science program of

Xiamen City (NO:3502Z20063002 ).

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